Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 506 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
• A programmable priority level of 0-3 for each interrupt. A higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
• Level and pulse detection of interrupt signals.
• Interrupt tail-chaining.
• An external Non-Maskable Interrupt (NMI). See Section 28.1 for implementation of
the NMI for specific parts.
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
28.6.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS
CMSIS functions enable software portability between different Cortex-M profile
processors.
To access the NVIC registers when using CMSIS, use the following functions:
[1] The input parameter IRQn is the IRQ number, see Table 428 for more information.
28.6.2.2 Interrupt Set-enable Register
The ISER enables interrupts, and shows which interrupts are enabled. See the register
summary in Table 441
for the register attributes.
The bit assignments are:
Table 441. NVIC register summary
Address Name Type Reset value Description
0xE000E100
ISER RW
0x00000000
Section 28–28.6.2.2
0xE000E180
ICER RW
0x00000000
Section 28–28.6.2.3
0xE000E200
ISPR RW
0x00000000
Section 28–28.6.2.4
0xE000E280
ICPR RW
0x00000000
Section 28–28.6.2.5
0xE000E400
-
0xE
000E41C
IPR0-7 RW
0x00000000
Section 28–28.6.2.6
Table 442. CMISIS access NVIC functions
CMSIS function Description
void NVIC_EnableIRQ(IRQn_Type IRQn)
[1]
Enables an interrupt or exception.
void NVIC_DisableIRQ(IRQn_Type IRQn)
[1]
Disables an interrupt or exception.
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
[1]
Sets the pending status of interrupt or exception to 1.
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
[1]
Clears the pending status of interrupt or exception to 0.
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
[1]
Reads the pending status of interrupt or exception.
This function returns non-zero value if the pending status is set
to 1.
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
[1]
Sets the priority of an interrupt or exception with configurable
priority level to 1.
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
[1]
Reads the priority of an interrupt or exception with configurable
priority level. This function returns the current priority level.