Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 507 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to
pending, but the NVIC never activates the interrupt, regardless of its priority.
28.6.2.3 Interrupt Clear-enable Register
The ICER disables interrupts, and show which interrupts are enabled. See the register
summary in Table 28–441
for the register attributes.
The bit assignments are:
28.6.2.4 Interrupt Set-pending Register
The ISPR forces interrupts into the pending state, and shows which interrupts are
pending. See the register summary in Table 28–441
for the register attributes.
The bit assignments are:
Remark: Writing 1 to the ISPR bit corresponding to:
• an interrupt that is pending has no effect
Table 443. ISER bit assignments
Bits Name Function
[31:0] SETENA Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
Table 444. ICER bit assignments
Bits Name Function
[31:0] CLRENA Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
Table 445. ISPR bit assignments
Bits Name Function
[31:0] SETPEND Interrupt set-pending bits.
Write:
0 = no effect
1 = changes interrupt state to pending.
Read:
0 = interrupt is not pending
1 = interrupt is pending.