Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 51 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
1. Write one to the DPDEN bit in the PCON register (see Table 50).
2. Store data to be retained in the general purpose registers (Table 51
).
3. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 453
).
4. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in
the PDRUNCFG register before entering Deep power-down mode.
Remark: This step is part dependent.
See Section 3.1 for part specific details.
5. Use the ARM WFI instruction.
Remark: The WAKEUP pin must be pulled HIGH externally before entering Deep
power-down mode.
3.9.4.3 Wake-up from Deep power-down mode
Pulling the WAKEUP pin LOW wakes up the LPC111x/LPC11Cxx from Deep power-down,
and the chip goes through the entire reset process (Section 3.6
). The minimum pulse
width for the HIGH-to-LOW transition on the WAKEUP pin is 50 ns.
Follow these steps to wake up the chip from Deep power-down mode:
1. A wake-up signal is generated when a HIGH-to-LOW transition occurs externally on
the WAKEUP pin with a pulse length of at least 50 ns while the part is in Deep
power-down mode.
– The PMU will turn on the on-chip voltage regulator. When the core voltage reaches
the power-on-reset (POR) trip point, a system reset will be triggered and the chip
re-boots.
– All registers except the GPREG0 to GPREG4and PCON will be in their reset state.
2. Once the chip has booted, read the deep power-down flag in the PCON register
(Table 50
) to verify that the reset was caused by a wake-up event from Deep
power-down.
3. Clear the deep power-down flag in the PCON register (Table 50
).
4. (Optional) Read the stored data in the general purpose registers (Table 51
and
Table 52
).
5. Set up the PMU for the next Deep power-down cycle.
Remark: The RESET
pin has no functionality in Deep power-down mode.
3.10 Deep-sleep mode details
3.10.1 IRC oscillator
The IRC is the only oscillator on the LPC111x/LPC11Cxx that can always shut down
glitch-free. Therefore it is recommended that the user switches the clock source to IRC
before the chip enters Deep-sleep mode.
3.10.2 Start logic
The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM
core. The port pins PIO0_0 to PIO0_11 and PIO1_0 are connected to the start logic and
serve as wake-up pins. The user must program the start logic registers for each input to