Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 511 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
[1] See the register description for more information.
28.6.3.1 The CMSIS mapping of the Cortex-M0 SCB registers
To improve software efficiency, the CMSIS simplifies the SCB register presentation. In the
CMSIS, the array
SHP[1]
corresponds to the registers SHPR2-SHPR3.
28.6.3.2 CPUID Register
The CPUID register contains the processor part number, version, and implementation
information. See the register summary in for its attributes. The bit assignments are:
28.6.3.3 Interrupt Control and State Register
The ICSR:
• provides:
– a set-pending bit for the Non-Maskable Interrupt (NMI) exception
– set-pending and clear-pending bits for the PendSV and SysTick exceptions
• indicates:
– the exception number of the exception being processed
– whether there are preempted active exceptions
– the exception number of the highest priority pending exception
Table 449. Summary of the SCB registers
Address Name Type Reset value Description
0xE000ED00
CPUID RO
0x410CC200
Section 28.6.3.2
0xE000ED04
ICSR RW
[1]
0x00000000
Section 28–28.6.3.3
0xE000ED0C
AIRCR RW
[1]
0xFA050000
Section 28–28.6.3.4
0xE000ED10
SCR RW
0x00000000
Section 28–28.6.3.5
0xE000ED14
CCR RO
0x00000204
Section 28–28.6.3.6
0xE000ED1C
SHPR2 RW
0x00000000
Section 28–28.6.3.7.1
0xE000ED20
SHPR3 RW
0x00000000
Section 28–28.6.3.7.2
Table 450. CPUID register bit assignments
Bits Name Function
[31:24] Implementer Implementer code:
0x41
= ARM
[23:20] Variant Variant number, the r value in the rnpn product revision
identifier:
0x0 = Revision 0
[19:16] Constant Constant that defines the architecture of the processor:, reads
as
0xC
= ARMv6-M architecture
[15:4] Partno Part number of the processor:
0xC20
= Cortex-M0
[3:0] Revision Revision number, the p value in the rnpn product revision
identifier:
0x0 = Patch 0