Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 515 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.6.3.6 Configuration and Control Register
The CCR is a read-only register and indicates some aspects of the behavior of the
Cortex-M0 processor. See the register summary in Table 28–449
for the CCR attributes.
The bit assignments are:
28.6.3.7 System Handler Priority Registers
The SHPR2-SHPR3 registers set the priority level, 0 to 3, of the exception handlers that
have configurable priority.
SHPR2-SHPR3 are word accessible. See the register summary in Table 28–449
for their
attributes.
To access to the system exception priority level using CMSIS, use the following CMSIS
functions:
• uint32_t NVIC_GetPriority(IRQn_Type IRQn)
• void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
The input parameter IRQn is the IRQ number, see Table 28–428 for more information.
The system fault handlers, and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field,
and bits[5:0] read as zero and ignore writes.
28.6.3.7.1 System Handler Priority Register 2
The bit assignments are:
Table 454. CCR bit assignments
Bits Name Function
[31:10] - Reserved.
[9] STKALIGN Always reads as one, indicates 8-byte stack alignment on
exception entry.
On exception entry, the processor uses bit[9] of the stacked PSR
to indicate the stack alignment. On return from the exception it
uses this stacked bit to restore the correct stack alignment.
[8:4] - Reserved.
[3] UNALIGN_TRP Always reads as one, indicates that all unaligned accesses
generate a HardFault.
[2:0] - Reserved.
Table 455. System fault handler priority fields
Handler Field Register description
SVCall PRI_11 Section 28–28.6.3.7.1
PendSV PRI_14 Section 28–28.6.3.7.2
SysTick PRI_15