Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 517 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.6.4.1 SysTick Control and Status Register
The SYST_CSR enables the SysTick features. See the register summary in for its
attributes. The bit assignments are:
28.6.4.2 SysTick Reload Value Register
The SYST_RVR specifies the start value to load into the SYST_CVR. See the register
summary in Table 28–458
for its attributes. The bit assignments are:
28.6.4.2.1 Calculating the RELOAD value
The RELOAD value can be any value in the range
0x00000001 - 0x00FFFFFF . You can program a
value of 0, but this has no effect because the SysTick exception request and
COUNTFLAG are activated when counting from 1 to 0.
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD
value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set
RELOAD to 99.
28.6.4.3 SysTick Current Value Register
The SYST_CVR contains the current value of the SysTick counter. See the register
summary in Table 28–458
for its attributes. The bit assignments are:
Table 459. SYST_CSR bit assignments
Bits Name Function
[31:17] - Reserved.
[16] COUNTFLAG Returns 1 if timer counted to 0 since the last read of this register.
[15:3] - Reserved.
[2] CLKSOURCE Selects the SysTick timer clock source:
0 = external reference clock.
1 = processor clock.
[1] TICKINT Enables SysTick exception request:
0 = counting down to zero does not assert the SysTick exception
request.
1 = counting down to zero asserts the SysTick exception request.
[0] ENABLE Enables the counter:
0 = counter disabled.
1 = counter enabled.
Table 460. SYST_RVR bit assignments
Bits Name Function
[31:24] - Reserved.
[23:0] RELOAD Value to load into the SYST_CVR when the counter is enabled and
when it reaches 0, see Section 28.6.4.2.1
.