Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 52 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
set the appropriate edge polarity for the corresponding wake-up event. Furthermore, the
interrupts corresponding to each input must be enabled in the NVIC. Interrupts 0 to 12 in
the NVIC correspond to 13 PIO pins (see Section 3.5.30
).
The start logic does not require a clock to run because it uses the input signals on the
enabled pins to generate a clock edge when enabled. Therefore, the start logic signals
should be cleared (see Table 39
) before use.
The start logic can also be used in Active mode to provide a vectored interrupt using the
LPC111x/LPC11Cxx’s input pins.
3.10.3 Using the general purpose counter/timers to create a self-wake-up
event
If enabled in Deep-sleep mode through the SYSAHBCLKCFG register, the counter/timers
can count clock cycles of the watchdog oscillator and create a match event when the
number of cycles equals a preset match value. The match event causes the
corresponding match output pin to go HIGH, LOW, or toggle. The state of the match
output pin is also monitored by the start logic and can trigger a wake-up interrupt if that pin
is enabled in the NVIC and the start logic trigger is configured accordingly in the start logic
edge control register (see Table 37
).
The following steps must be performed to configure the counter/timer and create a timed
Deep-sleep self-wake-up event:
1. Configure the port pin as match output in the IOCONFIG block. Select from pins
PIO0_1 or PIO0_8 to PIO0_11, which are inputs to the start logic and also hold a
match output function.
2. In the corresponding counter/timer, set the match value, and configure the match
output for the selected pin.
3. Select the watchdog oscillator to run in Deep-sleep mode in the PDSLEEPCFG
register.
4. Switch the clock source to the watchdog oscillator in the MAINCLKSEL register
(Table 18
) and ensure the watchdog oscillator is powered in the PDRUNCFG register.
5. Enable the pin, configure its edge detect function, and reset the start logic in the start
logic registers (Table 37
to Table 40), and enable the interrupt in the NVIC.
6. Disable all other peripherals in the SYSAHBCLKCTRL register.
7. Ensure that the DPDEN bit in the PCON register is set to zero (Table 50
).
8. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register (Table 453
).
9. Start the counter/timer.
10. Use the ARM WFI instruction to enter Deep-sleep mode.
3.11 System PLL functional description
The LPC111x/LPC11Cxx uses the system PLL to create the clocks for the core and
peripherals.