Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 521 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
[1] N is the number of elements.
[2] N is the number of elements in the stack-pop list including PC and assumes load or store
does not generate a HardFault exception.
[3] 3 if taken, 1 if not taken.
[4] Cycle count depends on core and debug configuration.
[5] Excludes time spend waiting for an interrupt or event.
[6] Executes as NOP.
Hint Send event SEV 1
Wait for event WFE 2
[5]
Wait for interrupt WFI 2
[5]
Yield YIELD
[6]
1
No operation NOP 1
Barriers Instruction synchronization ISB 4
Data memory DMB 4
Data synchronization DSB 4
Table 463. Cortex M0- instruction summary
Operation Description Assembler Cycles