Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 524 of 547
NXP Semiconductors
UM10398
Chapter 29: Supplementary information
29.4 Tables
Table 1. LPC111x/LPC11Cxx feature changes. . . . . . . . .5
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .8
Table 3. Ordering options . . . . . . . . . . . . . . . . . . . . . . .11
Table 4. LPC111x memory configuration . . . . . . . . . . . .19
Table 5. LPC11Cxx memory configuration . . . . . . . . . . .19
Table 6. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 7. Register overview: system control block (base
address 0x4004 8000) . . . . . . . . . . . . . . . . . .24
Table 8. System memory remap register
(SYSMEMREMAP, address 0x4004 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 9. Peripheral reset control register (PRESETCTRL,
address 0x4004 8004) bit description. . . . . . . .27
Table 10. System PLL control register (SYSPLLCTRL,
address 0x4004 8008) bit description . . . . . . .27
Table 11. System PLL status register (SYSPLLSTAT,
address 0x4004 800C) bit description . . . . . . .28
Table 12. System oscillator control register (SYSOSCCTRL,
address 0x4004 8020) bit description. . . . . . . .28
Table 13. Watchdog oscillator control register
(WDTOSCCTRL, address 0x4004 8024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 14. Internal resonant crystal control register
(IRCCTRL, address 0x4004 8028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 15. System reset status register (SYSRSTSTAT,
address 0x4004 8030) bit description. . . . . . . .30
Table 16. System PLL clock source select register
(SYSPLLCLKSEL, address 0x4004 8040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 17. System PLL clock source update enable register
(SYSPLLCLKUEN, address 0x4004 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 18. Main clock source select register (MAINCLKSEL,
address 0x4004 8070) bit description. . . . . . . .31
Table 19. Main clock source update enable register
(MAINCLKUEN, address 0x4004 8074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 20. System AHB clock divider register
(SYSAHBCLKDIV, address 0x4004 8078) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 21. System AHB clock control register
(SYSAHBCLKCTRL, address 0x4004 8080) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 22. SPI0 clock divider register (SSP0CLKDIV,
address 0x4004 8094) bit description. . . . . . . .34
Table 23. UART clock divider register (UARTCLKDIV,
address 0x4004 8098) bit description. . . . . . . .34
Table 24. SPI1 clock divider register (SSP1CLKDIV,
address 0x4004 809C) bit description . . . . . . .35
Table 25. WDT clock source select register (WDTCLKSEL,
address 0x4004 80D0) bit description . . . . . . .35
Table 26. WDT clock source update enable register
(WDTCLKUEN, address 0x4004 80D4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 27. WDT clock divider register (WDTCLKDIV, address
0x4004 80D8) bit description . . . . . . . . . . . . . . 36
Table 28. CLKOUT clock source select register
(CLKOUTCLKSEL, address 0x4004 80E0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 29. CLKOUT clock source update enable register
(CLKOUTUEN, address 0x4004 80E4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 30. CLKOUT clock divider registers
(CLKOUTCLKDIV, address 0x4004 80E8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 31. POR captured PIO status registers 0
(PIOPORCAP0, address 0x4004 8100) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 32. POR captured PIO status registers 1
(PIOPORCAP1, address 0x4004 8104) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 33. BOD control register (BODCTRL, address 0x4004
8150) bit description. . . . . . . . . . . . . . . . . . . . . 38
Table 34. System tick timer calibration register
(SYSTCKCAL, address 0x4004 8154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 35. IRQ latency register (IRQLATENCY, address
0x4004 8170) bit description . . . . . . . . . . . . . . 39
Table 36. NMI source selection register (NMISRC, address
0x4004 8174) bit description . . . . . . . . . . . . . . 39
Table 37. Start logic edge control register 0 (STARTAPRP0,
address 0x4004 8200) bit description . . . . . . 40
Table 38. Start logic signal enable register 0 (STARTERP0,
address 0x4004 8204) bit description . . . . . . 40
Table 39. Start logic reset register 0 (STARTRSRP0CLR,
address 0x4004 8208) bit description . . . . . . 40
Table 40. Start logic status register 0 (STARTSRP0,
address 0x4004 820C) bit description . . . . . . 41
Table 41. Allowed values for PDSLEEPCFG register . . . 41
Table 42. Deep-sleep configuration register
(PDSLEEPCFG, address 0x4004 8230) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 43. Wake-up configuration register (PDAWAKECFG,
address 0x4004 8234) bit description . . . . . . 42
T
ab
le 44. Power-down configuration register (PDRUNCFG,
address 0x4004 8238) bit description . . . . . . 43
Table 45. Device ID register (DEVICE_ID, address 0x4004
83F4) bit description . . . . . . . . . . . . . . . . . . . . 45
Table 46. PLL frequency parameters. . . . . . . . . . . . . . . . 54
Table 47. PLL configuration examples. . . . . . . . . . . . . . . 55
Table 48. Flash configuration register (FLASHCFG, address
0x4003 C010) bit description . . . . . . . . . . . . . . 56
Table 49. Register overview: PMU (base address 0x4003
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 50. Power control register (PCON, address 0x4003
8000) bit description . . . . . . . . . . . . . . . . . . . . 57
Table 51. General purpose registers 0 to 3 (GPREG0 -
GPREG3, address 0x4003 8004 to 0x4003 8010)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 52. General purpose register 4 (GPREG4, address
0x4003 8014) bit description . . . . . . . . . . . . . 58