Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 525 of 547
NXP Semiconductors
UM10398
Chapter 29: Supplementary information
Table 53. set_pll routine . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 54. set_power routine . . . . . . . . . . . . . . . . . . . . . .66
Table 55. Connection of interrupt sources to the Vectored
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . .69
Table 56. Register overview: I/O configuration (base
address 0x4004 4000) . . . . . . . . . . . . . . . . . . .74
Table 57. I/O configuration registers ordered by port
number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Table 58. IOCON_PIO2_6 register (IOCON_PIO2_6,
address 0x4004 4000) bit description . . . . . . .77
Table 59. IOCON_PIO2_0 register (IOCON_PIO2_0,
address 0x4004 4008) bit description . . . . . . .78
Table 60. IOCON_RESET_PIO0_0 register
(IOCON_RESET_PIO0_0, address 0x4004
400C) bit description. . . . . . . . . . . . . . . . . . . . .78
Table 61. IOCON_PIO0_1 register (IOCON_PIO0_1,
address 0x4004 4010) bit description . . . . . . .79
Table 62. IOCON_PIO1_8 register (IOCON_PIO1_8,
address 0x4004 4014) bit description . . . . . . .80
Table 63. IOCON_PIO0_2 register (IOCON_PIO0_2,
address 0x4004 401C) bit description . . . . . . .80
Table 64. IOCON_PIO2_7 register (IOCON_PIO2_7,
address 0x4004 4020) bit description . . . . . . .81
Table 65. IOCON_PIO2_8 register (IOCON_PIO2_8,
address 0x4004 4024) bit description . . . . . . .81
Table 66. IOCON_PIO2_1 register (IOCON_PIO2_1,
address 0x4004 4028) bit description . . . . . . .82
Table 67. IOCON_PIO0_3 register (IOCON_PIO0_3,
address 0x4004 402C) bit description . . . . . . .83
Table 68. IOCON_PIO0_4 register (IOCON_PIO0_4,
address 0x4004 4030) bit description . . . . . . .83
Table 69. IOCON_PIO0_5 register (IOCON_PIO0_5,
address 0x4004 4034) bit description . . . . . . .84
Table 70. IOCON_PIO1_9 register (IOCON_PIO1_9,
address 0x4004 4038) bit description . . . . . . .84
Table 71. IOCON_PIO3_4 register (IOCON_PIO3_4,
address 0x4004 403C) bit description . . . . . . .85
Table 72. IOCON_PIO2_4 register (IOCON_PIO2_4,
address 0x4004 4040) bit description . . . . . . .85
Table 73. IOCON_PIO2_5 register (IOCON_PIO2_5,
address 0x4004 4044) bit description . . . . . . .86
Table 74. IOCON_PIO3_5 register (IOCON_PIO3_5,
address 0x4004 4048) bit description . . . . . . .86
Table 75. IOCON_PIO0_6 register (IOCON_PIO0_6,
address 0x4004 404C) bit description . . . . . . .87
Table 76. IOCON_PIO0_7 register (IOCON_PIO0_7,
address 0x4004 4050) bit description. . . . . . . .87
Table 77. IOCON_PIO2_9 register (IOCON_PIO2_9,
address 0x4004 4054) bit description . . . . . . .88
Table 78. IOCON_PIO2_10 register (IOCON_PIO2_10,
address 0x4004 4058) bit description . . . . . . .89
Table 79. IOCON_PIO2_2 register (IOCON_PIO2_2,
address 0x4004 405C) bit description . . . . . . .89
Table 80. IOCON_PIO0_8 register (IOCON_PIO0_8,
address 0x4004 4060) bit description . . . . . . .90
Table 81. IOCON_PIO0_9 register (IOCON_PIO0_9,
address 0x4004 4064) bit description . . . . . . .90
Table 82. IOCON_SWCLK_PIO0_10 register
(IOCON_SWCLK_PIO0_10, address 0x4004
4068) bit description . . . . . . . . . . . . . . . . . . . . 91
Table 83. IOCON_PIO1_10 register (IOCON_PIO1_10,
address 0x4004 406C) bit description . . . . . . 92
Table 84. IOCON_PIO2_11 register (IOCON_PIO2_11,
address 0x4004 4070) bit description . . . . . . . 93
Table 85. IOCON_R_PIO0_11 register
(IOCON_R_PIO0_11, address 0x4004 4074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 86. IOCON_R_PIO1_0 register (IOCON_R_PIO1_0,
address 0x4004 4078) bit description . . . . . . . 94
Table 87. IOCON_R_PIO1_1 register (IOCON_R_PIO1_1,
address 0x4004 407C) bit description . . . . . . 95
Table 88. IOCON_R_PIO1_2 register (IOCON_R_PIO1_2,
address 0x4004 4080) bit description . . . . . . 95
Table 89. IOCON_PIO3_0 register (IOCON_PIO3_0,
address 0x4004 4084) bit description . . . . . . . 96
Table 90. IOCON_PIO3_1 register (IOCON_PIO3_1,
address 0x4004 4088) bit description . . . . . . . 97
Table 91. IOCON_PIO2_3 register (IOCON_PIO2_3,
address 0x4004 408C) bit description . . . . . . 97
Table 92. IOCON_SWDIO_PIO1_3 register
(IOCON_SWDIO_PIO1_3, address 0x4004 4090)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 93. IOCON_PIO1_4 register (IOCON_PIO1_4,
address 0x4004 4094) bit description . . . . . . . 99
Table 94. IOCON_PIO1_11 register (IOCON_PIO1_11,
address 0x4004 4098) bit description . . . . . 100
Table 95. IOCON_PIO3_2 register (IOCON_PIO3_2,
address 0x4004 409C) bit description . . . . . 100
Table 96. IOCON_PIO1_5 register (IOCON_PIO1_5,
address 0x4004 40A0) bit description . . . . . . 101
Table 97. IOCON_PIO1_6 register (IOCON_PIO1_6,
address 0x4004 40A4) bit description . . . . . . 101
T
ab
le 98. IOCON_PIO1_7 register (IOCON_PIO1_7,
address 0x4004 40A8) bit description . . . . . . 102
Table 99. IOCON_PIO3_3 register (IOCON_PIO3_3,
address 0x4004 40AC) bit description . . . . . 103
Table 100. IOCON SCK location register
(IOCON_SCK_LOC, address 0x4004 40B0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 101. IOCON DSR
location register
(IOCON_DSR_LOC, address 0x4004 40B4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 102. IOCON DCD
location register
(IOCON_DCD_LOC, address 0x4004 40B8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 103. IOCON RI
location register (IOCON_RI_LOC,
address 0x4004 40BC) bit description . . . . . 104
Table 104. Register overview: I/O configuration (base
address 0x4004 4000) . . . . . . . . . . . . . . . . . . 108
Table 105. I/O configuration registers ordered by port
number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 106. IOCON_PIO2_6 register (IOCON_PIO2_6,
address 0x4004 4000) bit description . . . . . . 111
Table 107. IOCON_PIO2_0 register (IOCON_PIO2_0,
address 0x4004 4008) bit description . . . . . . 112
Table 108. IOCON_RESET_PIO0_0 register