Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 527 of 547
NXP Semiconductors
UM10398
Chapter 29: Supplementary information
Table 160. LPC1113/14 and LPC11C12/C14 pin description
table (LQFP48 package) . . . . . . . . . . . . . . . .148
Table 161. LPC1111/12/13/14 pin description table
(HVQFN33 package) . . . . . . . . . . . . . . . . . .152
Table 162. LPC1112FHN24 Pin description table (HVQFN24
package). . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Table 163. LPC11C24/C22 pin description table (LQFP48
package). . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Table 164. LPC11D14 pin description table (LQFP100
package) . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Table 165. LPC11xx pin configurations for 20-pin and 28-pin
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Table 166. LPC1110/11/12 pin description table (SO20 and
TSSOP20 package with I
2
C-bus pins) . . . . . .168
Table 167. LPC1112 pin description table (TSSOP20 with
V
DDA
and V
SSA
pins) . . . . . . . . . . . . . . . . . . .171
Table 168. LPC1112/14 pin description table (TSSOP28 and
DIP28 packages) . . . . . . . . . . . . . . . . . . . . . .174
Table 169. LPC1100XL pin configurations. . . . . . . . . . . .177
Table 170. LPC1100XL series: LPC1113/14/15 pin
description table (LQFP48 and TFBGA48
package) . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Table 171. LPC1111/12/13/14XL pin description table
(HVQFN33 package) . . . . . . . . . . . . . . . . . .186
Table 172. GPIO configuration . . . . . . . . . . . . . . . . . . . .190
Table 173. Register overview: GPIO (base address port 0:
0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002
0000; port 3: 0x5003 0000) . . . . . . . . . . . . . .191
Table 174. GPIOnDATA register (GPIO0DATA, address
0x5000 0000 to 0x5000 3FFC; GPIO1DATA,
address 0x5001 0000 to 0x5001 3FFC;
GPIO2DATA, address 0x5002 0000 to 0x5002
3FFC; GPIO3DATA, address 0x5003 0000 to
0x5003 3FFC) bit description . . . . . . . . . . . .191
Table 175. GPIOnDIR register (GPIO0DIR, address 0x5000
8000 to GPIO3DIR, address 0x5003 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .192
Table 176. GPIOnIS register (GPIO0IS, address 0x5000
8004 to GPIO3IS, address 0x5003 8004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .192
Table 177. GPIOnIBE register (GPIO0IBE, address 0x5000
8008 to GPIO3IBE, address 0x5003 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Table 178. GPIOnIEV register (GPIO0IEV, address 0x5000
800C to GPIO3IEV, address 0x5003 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Table 179. GPIOnIE register (GPIO0IE, address 0x5000
8010 to GPIO3IE, address 0x5003 8010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Table 180. GPIOnRIS register (GPIO0RIS, address 0x5000
8014 to GPIO3RIS, address 0x5003 8014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .194
Table 181. GPIOnMIS register (GPIO0MIS, address 0x5000
8018 to GPIO3MIS, address 0x5003 8018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .194
Table 182. GPIOnIC register (GPIO0IC, address 0x5000
801C to GPIO3IC, address 0x5003 801C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .194
Table 183. UART pin description . . . . . . . . . . . . . . . . . . 198
Table 184. Register overview: UART (base address: 0x4000
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 185. UART Receiver Buffer Register (U0RBR -
address 0x4000 8000 when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . 200
Table 186. UART Transmitter Holding Register (U0THR -
address 0x4000 8000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . 200
Table 187. UART Divisor Latch LSB Register (U0DLL -
address 0x4000 8000 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 188. UART Divisor Latch MSB Register (U0DLM -
address 0x4000 8004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 189. UART Interrupt Enable Register (U0IER -
address 0x4000 8004 when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 190. UART Interrupt Identification Register (U0IIR -
address 0x4004 8008, Read Only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 191. UART Interrupt Handling. . . . . . . . . . . . . . . . 203
Table 192. UART FIFO Control Register (U0FCR - address
0x4000 8008, Write Only) bit description . . . . 205
Table 193. UART Line Control Register (U0LCR - address
0x4000 800C) bit description . . . . . . . . . . . . 205
Table 194. UART0 Modem Control Register (U0MCR -
address 0x4000 8010) bit description . . . . . . 206
Table 195. Modem status interrupt generation . . . . . . . . 208
Table 196. UART Line Status Register (U0LSR - address
0x4000 8014, Read Only) bit description . . . 209
Table 197. UART Modem Status Register (U0MSR - address
0x4000 8018) bit description . . . . . . . . . . . . . 211
Table 198. UART Scratch Pad Register (U0SCR - address
0x4000 801C) bit description . . . . . . . . . . . . . 211
Table 199. Auto baud Control Register (U0ACR - address
0x4000 8020) bit description . . . . . . . . . . . . . 212
Table 200. UART Fractional Divider Register (U0FDR -
address 0x4000 8028) bit description . . . . . . 215
Table 201. Fractional Divider setting look-up table . . . . . 218
Table 202. UART Transmit Enable Register (U0TER -
address 0x4000 8030) bit description . . . . . . 219
Table 203. UART RS485 Control register (U0RS485CTRL -
address 0x4000 804C) bit description . . . . . 219
Table 204. UART RS485 Address Match register
(U0RS485ADRMATCH - address 0x4000 8050)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 205. UART RS485 Delay value register (U0RS485DLY
- address 0x4000 8054) bit description . . . . . 220
Table 206. SPI pin descriptions . . . . . . . . . . . . . . . . . . . 225
Table 207. Register overview: SPI0 (base address 0x4004
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 208. Register overview: SPI1 (base address 0x4005
8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 209: SPI/SSP Control Register 0 (SSP0CR0 - address
0x4004 0000, SSP1CR0 - address 0x4005 8000)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 210: SPI/SSP Control Register 1 (SSP0CR1 - address