Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 528 of 547
NXP Semiconductors
UM10398
Chapter 29: Supplementary information
0x4004 0004, SSP1CR1 - address 0x4005 8004)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .228
Table 211: SPI/SSP Data Register (SSP0DR - address
0x4004 0008, SSP1DR - address 0x4005 8008)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .228
Table 212: SPI/SSP Status Register (SSP0SR - address
0x4004 000C, SSP1SR - address 0x4005 800C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .229
Table 213: SPI/SSP Clock Prescale Register (SSP0CPSR -
address 0x4004 0010, SSP1CPSR - address
0x4005 8010) bit description . . . . . . . . . . . . .229
Table 214: SPI/SSP Interrupt Mask Set/Clear register
(SSP0IMSC - address 0x4004 0014, SSP1IMSC -
address 0x4005 8014) bit description. . . . . . .230
Table 215: SPI/SSP Raw Interrupt Status register (SSP0RIS
- address 0x4004 0018, SSP1RIS - address
0x4005 8018) bit description . . . . . . . . . . . . .230
Table 216: SPI/SSP Masked Interrupt Status register
(SSP0MIS - address 0x4004 001C, SSP1MIS -
address 0x4005 801C) bit description . . . . . .231
Table 217: SPI/SSP interrupt Clear Register (SSP0ICR -
address 0x4004 0020, SSP1ICR - address
0x4005 8020) bit description . . . . . . . . . . . . .231
Table 218. I
2
C-bus pin description. . . . . . . . . . . . . . . . . .241
Table 219. Register overview: I
2
C (base address 0x4000
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Table 220. I
2
C Control Set register (I2C0CONSET - address
0x4000 0000) bit description . . . . . . . . . . . . .242
Table 221. I
2
C Status register (I2C0STAT - 0x4000 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Table 222. I
2
C Data register (I2C0DAT - 0x4000 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Table 223. I
2
C Slave Address register 0 (I2C0ADR0-
0x4000 000C) bit description . . . . . . . . . . . . .245
Table 224. I
2
C SCL HIGH Duty Cycle register (I2C0SCLH -
address 0x4000 0010) bit description. . . . . . .245
Table 225. I
2
C SCL Low duty cycle register (I2C0SCLL -
0x4000 0014) bit description . . . . . . . . . . . . .245
Table 226. SCLL + SCLH values for selected I
2
C clock
values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
Table 227. I
2
C Control Clear register (I2C0CONCLR -
0x4000 0018) bit description . . . . . . . . . . . . .246
Table 228. I
2
C Monitor mode control register (I2C0MMCTRL
- 0x4000 001C) bit description . . . . . . . . . . . .247
Table 229. I
2
C Slave Address registers (I2C0ADR[1, 2, 3]-
0x4000 00[20, 24, 28]) bit description . . . . . .248
Table 230. I
2
C Data buffer register (I2C0DATA_BUFFER -
0x4000 002C) bit description . . . . . . . . . . . . .249
Table 231. I
2
C Mask registers (I2C0MASK[0, 1, 2, 3] -
0x4000 00[30, 34, 38, 3C]) bit description . . .249
Table 232. I2C0CONSET and I2C1CONSET used to
configure Master mode. . . . . . . . . . . . . . . . . .250
Table 233. I2C0CONSET and I2C1CONSET used to
configure Slave mode. . . . . . . . . . . . . . . . . . .251
Table 234. Abbreviations used to describe an I
2
C
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
Table 235. I2C0CONSET used to initialize Master
Transmitter mode . . . . . . . . . . . . . . . . . . . . . .257
Table 236. Master Transmitter mode . . . . . . . . . . . . . . . 259
Table 237. Master Receiver mode . . . . . . . . . . . . . . . . . 262
Table 238. I2C0ADR and I2C1ADR usage in Slave Receiver
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 239. I2C0CONSET and I2C1CONSET used to
initialize Slave Receiver mode. . . . . . . . . . . . 264
Table 240. Slave Receiver mode . . . . . . . . . . . . . . . . . 265
Table 241. Slave Transmitter mode . . . . . . . . . . . . . . . . 269
Table 242. Miscellaneous States . . . . . . . . . . . . . . . . . . 271
Table 243. CAN pin description (LPC11C12/C14) . . . . . 284
Table 244. CAN pin description (LPC11C22/C24) . . . . . 284
Table 245. Register overview: CCAN (base address 0x4005
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 246. CAN control registers (CANCNTL, address
0x4005 0000) bit description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 247. CAN status register (CANSTAT, address
0x4005 0004) bit description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 248. CAN error counter (CANEC, address
0x4005 0008) bit description . . . . . . . . . . . . 289
Table 249. CAN bit timing register (CANBT, address
0x4005 000C) bit description . . . . . . . . . . . . . 290
Table 250. CAN interrupt register (CANINT, address
0x4005 0010) bit description . . . . . . . . . . . . . 291
Table 251. CAN test register (CANTEST, address
0x4005 0014) bit description . . . . . . . . . . . . . 291
Table 252. CAN baud rate prescaler extension register
(CANBRPE, address 0x4005 0018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 253. Message interface registers . . . . . . . . . . . . . 293
Table 254. Structure of a message object in the message
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 255. CAN message interface command request
registers (CANIF1_CMDREQ, address
0x4005 0020 and CANIF2_CMDREQ, address
0x4005 0080) bit description . . . . . . . . . . . . . 294
Table 256. CAN message interface command mask
registers (CANIF1_CMDMSK_W, address
0x4005 0024 and CANIF2_CMDMSK_W,
address 0x4005 0084) bit description for write
direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 257. CAN message interface command mask
registers (CANIF1_CMDMSK_R, address
0x4005 0024 and CANIF2_CMDMSK_R, address
0x4005 0084) bit description for read direction .
295
Table 258. CAN message interface mask 1 registers
(CANIF1_MSK1, address 0x4005 0028 and
CANIF2_MASK1, address 0x4005 0088) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 259. CAN message interface mask 2 registers
(CANIF1_MSK2, address 0x4005 002C and
CANIF2_MASK2, address 0x4005 008C) bit
description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 260. CAN message interface arbitration 1 registers
(CANIF1_ARB1, address 0x4005 0030 and