Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller HVQFN 32 (7x7) 32-Bit 50 MHz I/O number 28

531

532

533

534

535

536

537

538

539

540

User manual Rev. 12.3 — 10 June 2014 531 of 547

continued >>

NXP Semiconductors

UM10398

Chapter 29: Supplementary information

Table 351. Register overview: Watchdog timer (base

address 0x4000 4000) . . . . . . . . . . . . . . . . . .401

Table 352. Watchdog Mode register (WDMOD - address

0x4000 4000) bit description . . . . . . . . . . . . .401

Table 353. Watchdog operating modes selection . . . . . .402

Table 354. Watchdog Constant register (WDTC - address

0x4000 4004) bit description . . . . . . . . . . . . .402

Table 355. Watchdog Feed register (WDFEED - address

0x4000 4008) bit description . . . . . . . . . . . . .403

Table 356. Watchdog Timer Value register (WDTV - address

0x4000 000C) bit description . . . . . . . . . . . . .403

Table 357. Register overview: SysTick timer (base address

0xE000 E000). . . . . . . . . . . . . . . . . . . . . . . . .405

Table 358. SysTick Timer Control and status register

(SYST_CSR - 0xE000 E010) bit description .406

Table 359. System Timer Reload value register (SYST_RVR

- 0xE000 E014) bit description . . . . . . . . . . . .406

Table 360. System Timer Current value register (SYST_CVR

- 0xE000 E018) bit description . . . . . . . . . . . .406

Table 361. System Timer Calibration value register

(SYST_CALIB - 0xE000 E01C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .407

Table 362. ADC pin description. . . . . . . . . . . . . . . . . . . .409

Table 363. Register overview: ADC (base address 0x4001

C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409

Table 364. A/D Control Register (AD0CR - address

0x4001 C000) bit description . . . . . . . . . . . . .410

Table 365. A/D Global Data Register (AD0GDR - address

0x4001 C004) bit description . . . . . . . . . . . . .411

Table 366. A/D Interrupt Enable Register (AD0INTEN -

address 0x4001 C00C) bit description . . . . . .412

Table 367. A/D Data Registers (AD0DR0 to AD0DR7 -

addresses 0x4001 C010 to 0x4001 C02C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .412

Table 368. A/D Status Register (AD0STAT - address

0x4001 C030) bit description . . . . . . . . . . . . .413

Table 369. LPC111x/LPC11Cx flash configurations. . . . .414

Table 370. LPC111x flash configuration (LPC1100,

LPC1100L, LPC1100C series) . . . . . . . . . . . .419

Table 371. LPC1100XL flash configuration . . . . . . . . . . .419

Table 372. Code Read Protection options. . . . . . . . . . . .421

Table 373. Code Read Protection hardware/software

interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . .421

Table 374. ISP commands allowed for different CRP

levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422

Table 375. UART ISP command summary . . . . . . . . . . .424

Table 376. UART ISP Unlock command . . . . . . . . . . . . .425

Table 377. UART ISP Set Baud Rate command . . . . . . .425

Table 378. UART ISP Echo command . . . . . . . . . . . . . .425

Table 379. UART ISP Write to RAM command . . . . . . . .426

Table 380. UART ISP Read Memory command . . . . . . .427

Table 381. UART ISP Prepare sector(s) for write operation

command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

Table 382. UART ISP Copy RAM to flash command . . . 428

Table 383. UART ISP Go command. . . . . . . . . . . . . . . . 429

Table 384. UART ISP Erase sector command . . . . . . . . 429

Table 385. UART ISP Blank check sector command . . . 430

Table 386. UART ISP Read Part Identification command430

Table 387. LPC111x and LPC11Cxx part identification

numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

Table 388. UART ISP Read Boot Code version number

command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

Table 389. UART ISP Compare command . . . . . . . . . . . 432

Table 390. UART ISP ReadUID command . . . . . . . . . . . 433

Table 391. UART ISP Return Codes Summary . . . . . . . 433

Table 392. C_CAN ISP and UART ISP command

summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Table 393. C_CAN ISP object directory . . . . . . . . . . . . . 435

Table 394. C_CAN ISP SDO abort codes. . . . . . . . . . . . 438

Table 395. IAP Command Summary . . . . . . . . . . . . . . . 440

Table 396. IAP Prepare sector(s) for write operation

command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

Table 397. IAP Copy RAM to flash command. . . . . . . . . 441

Table 398. IAP Erase Sector(s) command . . . . . . . . . . . 442

Table 399. IAP Blank check sector(s) command . . . . . . 442

Table 400. IAP Read Part Identification command . . . . . 442

Table 401. IAP Read Boot Code version number

command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Table 402. IAP Compare command . . . . . . . . . . . . . . . . 443

Table 403. IAP Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . 444

Table 404. IAP ReadUID command . . . . . . . . . . . . . . . . 444

Table 405. IAP Erase page command . . . . . . . . . . . . . . 444

Table 406. IAP Status Codes Summary . . . . . . . . . . . . . 445

Table 407. Memory mapping in debug mode . . . . . . . . . 445

Table 408. Flash configuration register (FLASHCFG,

address 0x4003 C010) bit description . . . . . . 446

Table 409. Register overview: FMC (base address 0x4003

C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Table 410. Flash Module Signature Start register

(FMSSTART - 0x4003 C020) bit description . 448

Table 411. Flash Module Signature Stop register (FMSSTOP

- 0x4003 C024) bit description. . . . . . . . . . . . 448

Table 412. FMSW0 register bit description (FMSW0,

address: 0x4003 C02C) . . . . . . . . . . . . . . . . 448

Table 413. FMSW1 register bit description (FMSW1,

address: 0x4003 C030) . . . . . . . . . . . . . . . . . 448

Table 414. FMSW2 register bit description (FMSW2,

address: 0x4003 C034) . . . . . . . . . . . . . . . . . 448

Table 415. FMSW3 register bit description (FMSW3,

address: 0x4003 40C8) . . . . . . . . . . . . . . . . 448

Table 416. Flash module Status register (FMSTAT - 0x4003

CFE0) bit description . . . . . . . . . . . . . . . . . . . 449