Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller HVQFN 32 (7x7) 32-Bit 50 MHz I/O number 28

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User manual Rev. 12.3 — 10 June 2014 532 of 547

NXP Semiconductors

UM10398

Chapter 29: Supplementary information

Table 417. Flash Module Status Clear register (FMSTATCLR

- 0x0x4003 CFE8) bit description . . . . . . . . . .449

Table 418. Serial Wire Debug pin description . . . . . . . . .451

Table 419. Summary of processor mode and stack use

options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .455

Table 420. Core register set summary. . . . . . . . . . . . . . .456

Table 421. PSR register combinations . . . . . . . . . . . . . .457

Table 422. APSR bit assignments . . . . . . . . . . . . . . . . . .458

Table 423. IPSR bit assignments. . . . . . . . . . . . . . . . . . .458

Table 424. EPSR bit assignments . . . . . . . . . . . . . . . . . .459

Table 425. PRIMASK register bit assignments . . . . . . . .459

Table 426. CONTROL register bit assignments . . . . . . .460

Table 427. Memory access behavior. . . . . . . . . . . . . . . .464

Table 428. Properties of different exception types. . . . . .466

Table 429. Exception return behavior . . . . . . . . . . . . . . .471

Table 430. Cortex-M0 instructions. . . . . . . . . . . . . . . . . .474

Table 431. CMSIS intrinsic functions to generate some

Cortex-M0 instructions . . . . . . . . . . . . . . . . . .475

Table 432. CMSIS intrinsic functions to access the special

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .476

Table 433. Condition code suffixes . . . . . . . . . . . . . . . . .481

Table 434. Access instructions . . . . . . . . . . . . . . . . . . . .481

Table 435. Data processing instructions . . . . . . . . . . . . .487

Table 436. ADC, ADD, RSB, SBC and SUB operand

restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . .489

Table 437. Branch and control instructions . . . . . . . . . . .496

Table 438. Branch ranges . . . . . . . . . . . . . . . . . . . . . . . .497

Table 439. Miscellaneous instructions. . . . . . . . . . . . . . .498

Table 440. Core peripheral register regions . . . . . . . . . .505

Table 441. NVIC register summary . . . . . . . . . . . . . . . . .506

Table 442. CMISIS access NVIC functions . . . . . . . . . .506

Table 443. ISER bit assignments. . . . . . . . . . . . . . . . . . .507

Table 444. ICER bit assignments . . . . . . . . . . . . . . . . . .507

Table 445. ISPR bit assignments. . . . . . . . . . . . . . . . . . .507

Table 446. ICPR bit assignments . . . . . . . . . . . . . . . . . .508

Table 447. IPR bit assignments. . . . . . . . . . . . . . . . . . . .508

Table 448. CMSIS functions for NVIC control . . . . . . . . .510

Table 449. Summary of the SCB registers . . . . . . . . . . .511

Table 450. CPUID register bit assignments. . . . . . . . . . .511

Table 451. ICSR bit assignments . . . . . . . . . . . . . . . . . .512

Table 452. AIRCR bit assignments . . . . . . . . . . . . . . . . .514

Table 453. SCR bit assignments . . . . . . . . . . . . . . . . . . .514

Table 454. CCR bit assignments . . . . . . . . . . . . . . . . . . .515

Table 455. System fault handler priority fields. . . . . . . . .515

Table 456. SHPR2 register bit assignments . . . . . . . . . .516

Table 457. SHPR3 register bit assignments . . . . . . . . . .516

Table 458. System timer registers summary . . . . . . . . . .516

Table 459. SYST_CSR bit assignments . . . . . . . . . . . . .517

Table 460. SYST_RVR bit assignments . . . . . . . . . . . . .517

Table 461. SYST_CVR bit assignments . . . . . . . . . . . . .518

Table 462. SYST_CALIB register bit assignments . . . . .518

Table 463. Cortex M0- instruction summary . . . . . . . . . .519

Table 464. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .522