Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 538 of 547
NXP Semiconductors
UM10398
Chapter 29: Supplementary information
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
12.1 How to read this chapter. . . . . . . . . . . . . . . . 190
12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.3 Register description . . . . . . . . . . . . . . . . . . . 191
12.3.1 GPIO data register . . . . . . . . . . . . . . . . . . . . 191
12.3.2 GPIO data direction register . . . . . . . . . . . . . 192
12.3.3 GPIO interrupt sense register. . . . . . . . . . . . 192
12.3.4 GPIO interrupt both edges sense register . . 193
12.3.5 GPIO interrupt event register . . . . . . . . . . . . 193
12.3.6 GPIO interrupt mask register . . . . . . . . . . . . 193
12.3.7 GPIO raw interrupt status register . . . . . . . . 193
12.3.8 GPIO masked interrupt status register. . . . . 194
12.3.9 GPIO interrupt clear register . . . . . . . . . . . . 194
12.4 Functional description . . . . . . . . . . . . . . . . . 195
12.4.1 Write/read data operation. . . . . . . . . . . . . . . 195
Write operation. . . . . . . . . . . . . . . . . . . . . . . . 195
Read operation . . . . . . . . . . . . . . . . . . . . . . . 196
Chapter 13: LPC111x/LPC11Cxx UART
13.1 How to read this chapter. . . . . . . . . . . . . . . . 197
13.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 197
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
13.4 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 198
13.5 Register description . . . . . . . . . . . . . . . . . . . 198
13.5.1 UART Receiver Buffer Register (U0RBR -
0x4000 8000, when DLAB = 0, Read Only) . 200
13.5.2 UART Transmitter Holding Register (U0THR -
0x4000 8000 when DLAB = 0, Write Only). . 200
13.5.3 UART Divisor Latch LSB and MSB Registers
(U0DLL - 0x4000 8000 and U0DLM -
0x4000 8004, when DLAB = 1). . . . . . . . . . . 200
13.5.4 UART Interrupt Enable Register (U0IER -
0x4000 8004, when DLAB = 0). . . . . . . . . . . 201
13.5.5 UART Interrupt Identification Register (U0IIR -
0x4004 8008, Read Only). . . . . . . . . . . . . . . 202
13.5.6 UART FIFO Control Register (U0FCR -
0x4000 8008, Write Only). . . . . . . . . . . . . . . 204
13.5.7 UART Line Control Register (U0LCR -
0x4000 800C) . . . . . . . . . . . . . . . . . . . . . . . . 205
13.5.8 UART Modem Control Register . . . . . . . . . . 206
13.5.8.1 Auto-flow control. . . . . . . . . . . . . . . . . . . . . . 207
13.5.8.1.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
13.5.8.1.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
13.5.9 UART Line Status Register (U0LSR -
0x4000 8014, Read Only). . . . . . . . . . . . . . . 209
13.5.10 UART Modem Status Register . . . . . . . . . . . 211
13.5.11 UART Scratch Pad Register (U0SCR -
0x4000 801C) . . . . . . . . . . . . . . . . . . . . . . . . 211
13.5.12 UART Auto-baud Control Register (U0ACR -
0x4000 8020) . . . . . . . . . . . . . . . . . . . . . . . . 212
13.5.13 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.5.14 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 213
13.5.15 UART Fractional Divider Register (U0FDR -
0x4000 8028) . . . . . . . . . . . . . . . . . . . . . . . . 215
13.5.15.1 Baud rate calculation . . . . . . . . . . . . . . . . . . 216
13.5.15.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR =
9600. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
13.5.15.1.2 Example 2: UART_PCLK = 12 MHz, BR =
115200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
13.5.16 UART Transmit Enable Register (U0TER -
0x4000 8030) . . . . . . . . . . . . . . . . . . . . . . . . 218
13.5.17 UART RS485 Control register (U0RS485CTRL -
0x4000 804C) . . . . . . . . . . . . . . . . . . . . . . . 219
13.5.18 UART RS485 Address Match register
(U0RS485ADRMATCH - 0x4000 8050). . . . 220
13.5.19 UART1 RS485 Delay value register
(U0RS485DLY - 0x4000 8054) . . . . . . . . . . 220
13.5.20 RS-485/EIA-485 modes of operation . . . . . . 220
RS-485/EIA-485 Normal Multidrop Mode (NMM)
221
RS-485/EIA-485 Auto Address Detection (AAD)
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
RS-485/EIA-485 Auto Direction Control. . . . . 221
RS485/EIA-485 driver delay time. . . . . . . . . . 222
RS485/EIA-485 output inversion . . . . . . . . . . 222
13.6 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 222
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
14.1 How to read this chapter. . . . . . . . . . . . . . . . 224
14.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 224
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
14.4 General description. . . . . . . . . . . . . . . . . . . . 224
14.5 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 225
14.6 Register description . . . . . . . . . . . . . . . . . . . 226
14.6.1 SPI/SSP Control Register 0 . . . . . . . . . . . . . 226
14.6.2 SPI/SSP0 Control Register 1 . . . . . . . . . . . . 227
14.6.3 SPI/SSP Data Register . . . . . . . . . . . . . . . . 228
14.6.4 SPI/SSP Status Register . . . . . . . . . . . . . . . 229
14.6.5 SPI/SSP Clock Prescale Register . . . . . . . . 229
14.6.6 SPI/SSP Interrupt Mask Set/Clear Register 229
14.6.7 SPI/SSP Raw Interrupt Status Register . . . 230
14.6.8 SPI/SSP Masked Interrupt Status Register . 230
14.6.9 SPI/SSP Interrupt Clear Register . . . . . . . . 231
14.7 Functional description . . . . . . . . . . . . . . . . . 231
14.7.1 Texas Instruments synchronous serial frame
format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
14.7.2 SPI frame format . . . . . . . . . . . . . . . . . . . . . 232
14.7.2.1 Clock Polarity (CPOL) and Phase (CPHA)
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
14.7.2.2 SPI format with CPOL=0,CPHA=0. . . . . . . . 233