Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 542 of 547
NXP Semiconductors
UM10398
Chapter 29: Supplementary information
20.7 Register description . . . . . . . . . . . . . . . . . . . 363
20.7.1 Interrupt Register (TMR32B0IR and
TMR32B1IR). . . . . . . . . . . . . . . . . . . . . . . . . 365
20.7.2 Timer Control Register (TMR32B0TCR and
TMR32B1TCR). . . . . . . . . . . . . . . . . . . . . . . 365
20.7.3 Timer Counter (TMR32B0TC - address
0x4001 4008 and TMR32B1TC - address
0x4001 8008) . . . . . . . . . . . . . . . . . . . . . . . . 366
20.7.4 Prescale Register (TMR32B0PR - address
0x4001 400C and TMR32B1PR - address
0x4001 800C) . . . . . . . . . . . . . . . . . . . . . . . . 366
20.7.5 Prescale Counter Register (TMR32B0PC -
address 0x4001 4010 and TMR32B1PC - address
0x4001 8010) . . . . . . . . . . . . . . . . . . . . . . . . 366
20.7.6 Match Control Register (TMR32B0MCR and
TMR32B1MCR) . . . . . . . . . . . . . . . . . . . . . . 367
20.7.7 Match Registers (TMR32B0MR0/1/2/3 -
addresses 0x4001 4018/1C/20/24 and
TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24) . . . . . . . . . . . . . . . . . . . . . . 368
20.7.8 Capture Control Register (TMR32B0CCR and
TMR32B1CCR) . . . . . . . . . . . . . . . . . . . . . . 368
20.7.9 Capture Register (TMR32B0CR0 - address
0x4001 402C and TMR32B1CR0 - address
0x4001 802C) . . . . . . . . . . . . . . . . . . . . . . . 369
20.7.10 External Match Register (TMR32B0EMR and
TMR32B1EMR) . . . . . . . . . . . . . . . . . . . . . . 369
20.7.11 Count Control Register (TMR32B0CTCR and
TMR32B1TCR) . . . . . . . . . . . . . . . . . . . . . . 371
20.7.12 PWM Control Register (TMR32B0PWMC and
TMR32B1PWMC) . . . . . . . . . . . . . . . . . . . . 372
20.7.13 Rules for single edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
20.8 Example timer operation . . . . . . . . . . . . . . . 374
20.9 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 375
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
21.1 How to read this chapter. . . . . . . . . . . . . . . . 376
21.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 376
21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
21.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 377
21.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
21.6 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 377
21.7 Register description . . . . . . . . . . . . . . . . . . . 377
21.7.1 Interrupt Register (TMR32B0IR and
TMR32B1IR). . . . . . . . . . . . . . . . . . . . . . . . . 380
21.7.2 Timer Control Register (TMR32B0TCR and
TMR32B1TCR). . . . . . . . . . . . . . . . . . . . . . . 380
21.7.3 Timer Counter (TMR32B0TC - address
0x4001 4008 and TMR32B1TC - address
0x4001 8008) . . . . . . . . . . . . . . . . . . . . . . . . 380
21.7.4 Prescale Register (TMR32B0PR - address
0x4001 400C and TMR32B1PR - address
0x4001 800C) . . . . . . . . . . . . . . . . . . . . . . . . 381
21.7.5 Prescale Counter Register (TMR32B0PC -
address 0x4001 4010 and TMR32B1PC - address
0x4001 8010) . . . . . . . . . . . . . . . . . . . . . . . . 381
21.7.6 Match Control Register (TMR32B0MCR and
TMR32B1MCR) . . . . . . . . . . . . . . . . . . . . . . 381
21.7.7 Match Registers (TMR32B0MR0/1/2/3 -
addresses 0x4001 4018/1C/20/24 and
TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24) . . . . . . . . . . . . . . . . . . . . . . 382
21.7.8 Capture Control Register (TMR32B0CCR and
TMR32B1CCR) . . . . . . . . . . . . . . . . . . . . . . 383
21.7.9 Capture Register (TMR32B0CR0/1 - address
0x4001 402C/30 and TMR32B1CR0/1 - address
0x4001 802C/30) . . . . . . . . . . . . . . . . . . . . . 384
21.7.10 External Match Register (TMR32B0EMR and
TMR32B1EMR) . . . . . . . . . . . . . . . . . . . . . . 384
21.7.11 Count Control Register (TMR32B0CTCR and
TMR32B1TCR) . . . . . . . . . . . . . . . . . . . . . . 386
21.7.12 PWM Control Register (TMR32B0PWMC and
TMR32B1PWMC) . . . . . . . . . . . . . . . . . . . . 387
21.8 Functional description . . . . . . . . . . . . . . . . . 388
21.8.1 Example timer operation . . . . . . . . . . . . . . . 388
21.8.2 Rules for single edge controlled PWM
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
21.9 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 390
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer (WDT)
22.1 How to read this chapter. . . . . . . . . . . . . . . . 391
22.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 391
22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
22.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 392
22.5 General description. . . . . . . . . . . . . . . . . . . . 392
22.6 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . 393
22.7 Register description . . . . . . . . . . . . . . . . . . . 394
22.7.1 Watchdog Mode register . . . . . . . . . . . . . . . 394
22.7.2 Watchdog Timer Constant register . . . . . . . 395
22.7.3 Watchdog Feed register . . . . . . . . . . . . . . . 396
22.7.4 Watchdog Timer Value register . . . . . . . . . . 396
22.7.5 Watchdog Timer Warning Interrupt register 396
22.7.6 Watchdog Timer Window register . . . . . . . . 397
22.7.7 Watchdog timing examples . . . . . . . . . . . . . 397
Chapter 23: LPC111x/LPC11Cxx WatchDog Timer (WDT)
23.1 How to read this chapter. . . . . . . . . . . . . . . . 399 23.2 Basic configuration. . . . . . . . . . . . . . . . . . . . 399