Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 543 of 547
NXP Semiconductors
UM10398
Chapter 29: Supplementary information
23.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
23.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 400
23.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
23.6 WDT clocking. . . . . . . . . . . . . . . . . . . . . . . . . 400
23.7 Register description . . . . . . . . . . . . . . . . . . . 401
23.7.1 Watchdog Mode register (WDMOD -
0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 401
23.7.2 Watchdog Timer Constant register (WDTC -
0x4000 4004) . . . . . . . . . . . . . . . . . . . . . . . . 402
23.7.3 Watchdog Feed register (WDFEED -
0x4000 4008) . . . . . . . . . . . . . . . . . . . . . . . . 402
23.7.4 Watchdog Timer Value register (WDTV -
0x4000 400C) . . . . . . . . . . . . . . . . . . . . . . . 403
23.8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 403
Chapter 24: LPC111x/LPC11Cxx System tick timer (SysTick)
24.1 How to read this chapter. . . . . . . . . . . . . . . . 404
24.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 404
24.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
24.4 General description. . . . . . . . . . . . . . . . . . . . 404
24.5 Register description . . . . . . . . . . . . . . . . . . . 405
24.5.1 System Timer Control and status register . . 405
24.5.2 System Timer Reload value register . . . . . . 406
24.5.3 System Timer Current value register . . . . . 406
24.5.4 System Timer Calibration value register
(SYST_CALIB - 0xE000 E01C) . . . . . . . . . . 407
24.6 Functional description . . . . . . . . . . . . . . . . . 407
24.7 Example timer calculations . . . . . . . . . . . . . 407
Example (system clock = 50 MHz). . . . . . . . . 407
Chapter 25: LPC111x/LPC11Cxx ADC
25.1 How to read this chapter. . . . . . . . . . . . . . . . 408
25.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 408
25.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
25.4 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 408
25.5 Register description . . . . . . . . . . . . . . . . . . . 409
25.5.1 A/D Control Register (AD0CR - 0x4001
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
25.5.2 A/D Global Data Register (AD0GDR -
0x4001 C004) . . . . . . . . . . . . . . . . . . . . . . . . 411
25.5.3 A/D Interrupt Enable Register (AD0INTEN -
0x4001 C00C) . . . . . . . . . . . . . . . . . . . . . . . 412
25.5.4 A/D Data Registers (AD0DR0 to AD0DR7 -
0x4001 C010 to 0x4001 C02C) . . . . . . . . . . 412
25.5.5 A/D Status Register (AD0STAT - 0x4001
C030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
25.6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
25.6.1 Hardware-triggered conversion . . . . . . . . . . 413
25.6.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
25.6.3 Accuracy vs. digital receiver . . . . . . . . . . . . 413
Chapter 26: LPC111x/LPC11Cxx Flash programming firmware
26.1 How to read this chapter. . . . . . . . . . . . . . . . 414
26.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
26.3 General description. . . . . . . . . . . . . . . . . . . . 416
26.3.1 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . 416
26.3.2 Memory map after any reset. . . . . . . . . . . . . 417
26.3.3 Criterion for Valid User Code . . . . . . . . . . . . 417
26.3.4 Boot process flowchart . . . . . . . . . . . . . . . . . 418
26.3.5 Flash configuration for LPC1100, LPC1100C,
LPC1100L series . . . . . . . . . . . . . . . . . . . . . 419
26.3.6 Flash configuration for LPC1100XL series . . 419
26.3.7 Flash content protection mechanism . . . . . . 420
26.3.8 Code Read Protection (CRP) . . . . . . . . . . . . 420
26.3.8.1 ISP entry protection . . . . . . . . . . . . . . . . . . . 422
26.4 UART Communication protocol . . . . . . . . . . 423
26.4.1 UART ISP command format. . . . . . . . . . . . . 423
26.4.2 UART ISP response format . . . . . . . . . . . . . 423
26.4.3 UART ISP data format . . . . . . . . . . . . . . . . . 423
26.4.4 UART ISP flow control . . . . . . . . . . . . . . . . . 423
26.4.5 UART ISP command abort. . . . . . . . . . . . . . 423
26.4.6 Interrupts during UART ISP . . . . . . . . . . . . . 423
26.4.7 Interrupts during IAP. . . . . . . . . . . . . . . . . . . 424
26.4.8 RAM used by ISP command handler (for
LPC11Cxx parts). . . . . . . . . . . . . . . . . . . . . . 424
26.4.9 RAM used by ISP command handler (for LPC111x
parts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
26.4.10 RAM used by IAP command handler. . . . . . 424
26.5 UART ISP commands . . . . . . . . . . . . . . . . . . 424
26.5.1 Unlock <Unlock code> (UART ISP) . . . . . . . 425
26.5.2 Set Baud Rate <Baud Rate> <stop bit> (UART
ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
26.5.3 Echo <setting> (UART ISP) . . . . . . . . . . . . . 425
26.5.4 Write to RAM <start address> <number of bytes>
(UART ISP) . . . . . . . . . . . . . . . . . . . . . . . . . 426
26.5.5 Read Memory <address> <no. of bytes> (UART
ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
26.5.6 Prepare sector(s) for write operation <start sector
number> <end sector number> (UART ISP) 427
26.5.7 Copy RAM to flash <Flash address> <RAM
address> <no of bytes> (UART ISP) . . . . . . 427
26.5.8 Go <address> <mode> (UART ISP) . . . . . . 428
26.5.9 Erase sector(s) <start sector number> <end
sector number> (UART ISP) . . . . . . . . . . . . 429
26.5.10 Blank check sector(s) <sector number> <end
sector number> (UART ISP) . . . . . . . . . . . . 430
26.5.11 Read Part Identification number (UART ISP) 430
26.5.12 Read Boot code version number (UART ISP) 432