Datasheet

User manual Rev. 12.3 — 10 June 2014 63 of 547

NXP Semiconductors

UM10398

Chapter 5: LPC111x/LPC11Cxx Power profiles

/* set_pll result0 options */

#define PLL_CMD_SUCCESS 0

#define PLL_INVALID_FRE Q 1

#define PLL_INVALID_MODE 2

#define PLL_FREQ_NOT_FOUND 3

#define PLL_NOT_LOCKED 4

For a simplified clock configuration scheme see Figure 12. For more details see Figure 8.

5.6.1.1 Param0: system PLL input frequency and Param1: expected system clock

set_pll looks for a setup in which the system PLL clock does not exceed 50 MHz. It easily

finds a solution when the ratio between the expected system clock and the system PLL

input frequency is an integer value, but it can also find solutions in other cases.

The system PLL input frequency (Param0) must be between 10000 to 25000 kHz (10

MHz to 25 MHz) inclusive. The expected system clock (Param1) must be between 1 and

50000 kHz inclusive. If either of these requirements is not met, set_pll returns

PLL_INVALID_FREQ and returns Param0 as Result1 since the PLL setting is unchanged.

5.6.1.2 Param2: mode

The first priority of set_pll is to find a setup that generates the system clock at exactly the

rate specified in Param1. If it is unlikely that an exact match can be found, input parameter

mode (Param2) should be used to specify if the actual system clock can be less than or

equal, greater than or equal or approximately the value specified as the expected system

clock (Param1).

A call specifying CPU_FREQ_EQU will only succeed if the PLL can output exactly the

frequency requested in Param1.

CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such

as overall current consumption and/or power budget reasons).

CPU_FREQ_GTE helps applications that need a minimum level of CPU processing

capabilities.

CPU_FREQ_APPROX results in a system clock that is as close as possible to the

requested value (it may be greater than or less than the requested value).

If an illegal mode is specified, set_pll returns PLL_INVALID_MODE. If the expected

system clock is out of the range supported by this routine, set_pll returns

PLL_FREQ_NOT_FOUND. In these cases the current PLL setting is not changed and

Param0 is returned as Result1.

5.6.1.3 Param3: system PLL lock time-out

It should take no more than 100 s for the system PLL to lock if a valid configuration is

selected. If Param3 is zero, set_pll will wait indefinitely for the PLL to lock. A non-zero

value indicates how many times the code will check for a successful PLL lock event

before it returns PLL_NOT_LOCKED. In this case the PLL settings are unchanged and

Param0 is returned as Result1.

Remark: The time it takes the PLL to lock depends on the selected PLL input clock

source (IRC/system oscillator) and its characteristics. The selected source can

experience more or less jitter depending on the operating conditions such as power