Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 48 (7x7) 32-Bit 50 MHz I/O number 40

1. General description

The LPC11U2x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC11U2x operate at CPU frequencies of up to 50 MHz.

Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller, the

LPC11U2x brings unparalleled design flexibility and seamless integration to today’s

demanding connectivity solutions.

The peripheral complement of the LPC11U2x includes up to 32 kB of flash memory, up to

10 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I

C-bus interface,

one RS-485/EIA-485 USART with support for synchronous mode and smart card

interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC

(Analog-to-Digital Converter), and up to 54 general-purpose I/O pins.

For additional documentation related to the LPC11U2x parts, see Section 15

“References”.

2. Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Non-Maskable Interrupt (NMI) input selectable from several input sources.

 System tick timer.

 Memory:

 Up to 32 kB on-chip flash program memory.

 Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.

 Up to 10 kB SRAM data memory.

 16 kB boot ROM.

 In-System Programming (ISP) and In-Application Programming (IAP) for flash and

EEPROM via on-chip bootloader software.

 ROM-based USB drivers. Flash updates via USB supported.

 ROM-based 32-bit integer division routines.

 Debug options:

LPC11U2x

32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up

to 10 kB SRAM and 4 kB EEPROM; USB device; USART

Rev. 2.3 — 27 March 2014 Product data sheet

Summary of content (74 pages)

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LPC11U2x 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up to 10 kB SRAM and 4 kB EEPROM; USB device; USART Rev. 2.3 — 27 March 2014 Product data sheet 1. General description The LPC11U2x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller      LPC11U2X Product data sheet  Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan Description Language).  Serial Wire Debug. Digital peripherals:  Up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode.  Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller      Processor wake-up from Deep power-down mode using one special function pin.  Power-On Reset (POR).  Brownout detect with four separate thresholds for interrupt and forced reset. Unique device serial number for identification. Single 3.3 V power supply (1.8 V to 3.6 V). Temperature range 40 C to +85 C. Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 packages. 3.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 5.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information VDD PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_23/AD7 PIO0_16/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO0_15/AD4/CT32B1_MAT2 27 26 25 PIO0_17/RTS/CT32B0_CAP0/SCLK 28 PIO0_18/RXD/CT32B0_MAT0 30 29 PIO0_19/TXD/CT32B0_MAT1 31 terminal 1 index area 32 6.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller ball A1 index area LPC11U24FET48/301 1 2 3 4 5 6 7 8 A B C D E F G H 002aag623 Transparent top view Fig 3. LPC11U2X Product data sheet Pin configuration (TFBGA48) All information provided in this document is subject to legal disclaimers. Rev. 2.3 — 27 March 2014 © NXP B.V. 2014. All rights reserved.
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LPC11U2x NXP Semiconductors 37 PIO1_14/DSR/CT16B0_MAT1/RXD 38 PIO1_22/RI/MOSI1 39 SWDIO/PIO0_15/AD4/CT32B1_MAT2 40 PIO0_16/AD5/CT32B1_MAT3/WAKEUP 41 VSS 42 PIO0_23/AD7 44 VDD 43 PIO1_15/DCD/CT16B0_MAT2/SCK1 45 PIO0_17/RTS/CT32B0_CAP0/SCLK 46 PIO0_18/RXD/CT32B0_MAT0 47 PIO0_19/TXD/CT32B0_MAT1 48 PIO1_16/RI/CT16B0_CAP0 32-bit ARM Cortex-M0 microcontroller PIO1_25/CT32B0_MAT1 1 36 PIO1_13/DTR/CT16B0_MAT0/TXD PIO1_19/DTR/SSEL1 2 35 TRST/PIO0_14/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 TDO/PIO0_13
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LPC11U2x NXP Semiconductors 49 PIO1_14 50 PIO1_3 51 PIO1_22 52 SWDIO/PIO0_15 53 PIO0_16 54 VSS 55 PIO1_9 56 PIO0_23 58 VDD 57 PIO1_15 59 PIO1_12 60 PIO0_17 61 PIO0_18 62 PIO0_19 63 PIO1_16 64 PIO1_6 32-bit ARM Cortex-M0 microcontroller PIO1_0 1 48 VDD PIO1_25 2 47 PIO1_13 PIO1_19 3 46 TRST/PIO0_14 RESET/PIO0_0 4 45 TDO/PIO0_13 PIO0_1 5 44 TMS/PIO0_12 PIO1_7 6 43 PIO1_11 VSS 7 42 TDI/PIO0_11 XTALIN 8 XTALOUT 9 41 PIO1_29 LPC11U24FBD64/401 40 PIO0_22 VDD 10 39 PI
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO port number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and PIO0_5.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_6/USB_CONNECT/ SCK0 Pin LQFP64 PIO0_5/SDA Pin LQFP48 Symbol Pin TFBGA48 Pin description Pin HVQFN33 Table 3.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller SWDIO/PIO0_15/AD4/ CT32B1_MAT2 PIO0_16/AD5/ CT32B1_MAT3/WAKEUP PIO0_17/RTS/ CT32B0_CAP0/SCLK PIO0_18/RXD/ CT32B0_MAT0 PIO0_19/TXD/ CT32B0_MAT1 PIO0_20/CT16B1_CAP0 PIO0_21/CT16B1_MAT0/ MOSI1 PIO0_22/AD6/ CT16B1_MAT1/MISO1 LPC11U2X Product data sheet Pin LQFP64 TRST/PIO0_14/AD3/ CT32B1_MAT1 Pin LQFP48 Symbol Pin TFBGA48 Pin description Pin HVQFN33 Table 3.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Pin description PIO1_0/CT32B1_MAT0 PIO1_1/CT32B1_MAT1 PIO1_2/CT32B1_MAT2 PIO1_3/CT32B1_MAT3 PIO1_4/CT32B1_CAP0 PIO1_5/CT32B1_CAP1 PIO1_6 PIO1_7 I; PU I/O PIO0_23 — General purpose digital input/output pin. - I AD7 — A/D converter, input 7. I; PU I/O PIO1_0 — General purpose digital input/output pin. - O CT32B1_MAT0 — Match output 0 for 32-bit timer 1. I; PU I/O PIO1_1 — General purpose digital input/output pin.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO1_18/CT16B1_CAP1/ TXD PIO1_19/DTR/SSEL1 PIO1_20/DSR/SCK1 PIO1_21/DCD/MISO1 PIO1_22/RI/MOSI1 Pin LQFP64 PIO1_17/CT16B0_CAP1/ RXD Pin LQFP48 Symbol Pin TFBGA48 Pin description Pin HVQFN33 Table 3.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. Pin description Pin LQFP64 Description Pin LQFP48 Type Pin TFBGA48 Reset state Pin HVQFN33 Symbol PIO1_31 - - 25 - [3] I; PU I/O PIO1_31 — General purpose digital input/output pin. USB_DM 13 G5 19 25 [7] F - USB_DM — USB bidirectional D line. 26 [7] F - USB_DP — USB bidirectional D+ line. - - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.3 SRAM The LPC11U2x contain a total of 8 kB or 10 kB on-chip static RAM memory. 7.4 On-chip ROM The on-chip ROM contains the boot loader and the following Application Programming Interfaces (APIs): • • • • • In-System Programming (ISP) and In-Application Programming (IAP) support for flash IAP support for EEPROM USB API Power profiles for configuring power consumption and PLL settings 32-bit integer division routines 7.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC11U2x 4 GB 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 0xE000 0000 reserved APB peripherals 0x5000 4000 GPIO 25 - 31 reserved 0x5000 0000 reserved 0x4008 4000 USB 23 GPIO GROUP0 INT 22 SSP1 20 - 21 reserved 0x4000 0000 19 GPIO interrupts 18 system control 0x2000 4800 17 IOCON 0x2000 4000 16 15 SSP0 flash/EEPROM controller 14 PMU reserved 2 kB USB RAM reserved 0.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 7.7 IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.8.1 Features • • • • GPIO pins can be configured as input or output by software. All GPIO pins default to inputs with interrupt disabled at reset. Pin registers allow pins to be sensed and set individually. Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • Any pin or pins in each port can trigger a port interrupt. 7.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller The USART uses a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.10.1 Features • • • • • Maximum USART data bit rate of 3.125 Mbit/s. 16 byte receive and transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.12.1 Features • The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s. • • • • • Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master).
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.17 Clocking and power control 7.17.1 Integrated oscillators The LPC11U2x include three independent oscillators: the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC11U2x operates from the internal RC oscillator until software switches to a different clock source.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller SYSTEM CLOCK DIVIDER CPU, system control, PMU system clock n memories, peripheral clocks SYSAHBCLKCTRLn (AHB clock enable) IRC oscillator main clock SSP0 PERIPHERAL CLOCK DIVIDER SSP0 USART PERIPHERAL CLOCK DIVIDER UART SSP1 PERIPHERAL CLOCK DIVIDER SSP1 USB 48 MHz CLOCK DIVIDER USB CLKOUT PIN CLOCK DIVIDER CLKOUT pin watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator SYSPLLCLKSE
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.17.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC11U2x, use the system oscillator to provide the clock source to USB. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. 7.17.1.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.17.5.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times. 7.17.5.5 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin. The LPC11U2x can wake up from Deep power-down mode via the WAKEUP pin. The LPC11U2x can be prevented from entering Deep power-down mode by setting a lock bit in the PMU block.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.18 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC11U2x is in reset.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD supply voltage (core and external rail) VI input voltage Conditions 5 V tolerant digital I/O pins; VDD  1.8 V Min Max Unit [2] 0.5 +4.6 V [5][2] 0.5 +5.5 V V 0.5 +3.6 [2][4] 0.5 +5.5 [2] 0.5 4.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics Table 5. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) IDD supply current Conditions [2] Min Typ[1] Max Unit 1.8 3.3 3.6 V - 2 - mA - 7 - mA - 1 - mA - 360 - A - 2 - A - 220 - nA Active mode; VDD = 3.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOL VOL = 0.4 V 4 - - mA LOW-level output current 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter I2C-bus Conditions Min Typ[1] Max Unit pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V 3.5 - - mA 3 - - 20 - - IOL LOW-level output current I2C-bus VOL = 0.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit pins configured for analog function - - 7.1 pF I2C-bus - - 2.5 pF - - 2.8 pF Pin capacitance input/output capacitance Cio pins (PIO0_4 and PIO0_5) pins configured as GPIO [1] Typical ratings are not guaranteed.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. ADC static characteristics Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol Parameter VIA analog input voltage 0 - VDD V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2] - - 1 LSB integral non-linearity [3] - - 1.5 LSB EO offset error [4] - - 3.5 LSB EG gain error [5] - - 0.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD − VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.1 BOD static characteristics Table 7. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 1 Min Typ Max Unit assertion - 2.22 - V de-assertion - 2.35 - V assertion - 2.52 - V de-assertion - 2.66 - V assertion - 2.80 - V de-assertion - 2.90 - V assertion - 1.46 - V de-assertion - 1.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag749 9 48 MHz(2) IDD (mA) 6 36 MHz(2) 24 MHz(2) 3 12 MHz(1) 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag751 4 IDD (mA) 3 48 MHz(2) 36 MHz(2) 2 24 MHz(2) 12 MHz(1) 1 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aag746 20 IDD (μA) VDD = 3.6 V, 3.3 V VDD = 2.0 V VDD = 1.8 V 15 10 5 0 -40 -15 10 35 60 85 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; USB_DP and USB_DM pulled LOW externally. Fig 13. Typical supply current versus temperature in Power-down mode 002aag747 0.8 IDD (μA) VDD = 3.6 V VDD = 3.3 V VDD = 2.0 V VDD = 1.8 V 0.6 0.4 0.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC11U2X Product data sheet Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz IRC 0.27 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.4 Electrical pin characteristics 002aae990 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 10 20 30 40 50 60 IOH (mA) Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 15. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. 002aaf019 60 T = 85 °C 25 °C −40 °C IOL (mA) 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 16.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae991 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 17. Typical LOW-level output current IOL versus LOW-level output voltage VOL 002aae992 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 18.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae988 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 19. Typical pull-up current Ipu versus input voltage VI 002aae989 80 T = 85 °C 25 °C −40 °C Ipd (μA) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 20.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Flash memory Table 9. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min [1] Nendu endurance tret retention time ter erase time tprog programming time Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 10.3 Internal oscillators Table 12. Dynamic characteristics: IRC Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.88 12 12.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %. [3] See the LPC11Uxx user manual. 10.4 I/O pins Table 14. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [7] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.6 SSP interface Table 16. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit - - ns - - SPI master (in SPI mode) Tcy(clk) full-duplex mode [1] 50 when only transmitting [1] 40 in SPI mode [2] 15 2.0 V  VDD < 2.4 V [2] 20 1.8 V  VDD < 2.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tDH tDS MISO CPHA = 1 DATA VALID CPHA = 0 DATA VALID 002aae829 Fig 24. SSP master timing in SPI mode LPC11U2X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.3 — 27 March 2014 © NXP B.V. 2014. All rights reserved.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 th(Q) CPHA = 0 DATA VALID 002aae830 Fig 25. SSP slave timing in SPI mode LPC11U2X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.3 — 27 March 2014 © NXP B.V. 2014. All rights reserved.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.7 USB interface Table 17. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 Suggested USB interface solutions The USB device can be connected to the USB as self-powered device (see Figure 27) or bus-powered device (see Figure 28). On the LPC11U2x, the PIO0_3/USB_VBUS pin is 5 V tolerant only when VDD is applied and at operating voltage level.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller For a bus-powered device, the VBUS signal does not need to be connected to the USB_VBUS pin (see Figure 28). The USB_CONNECT function can additionally be connected as shown in Figure 27 to prevent the USB from timing out when there is a significant delay between power-up and handling USB traffic. VDD LPC1xxx REGULATOR R1 1.5 kΩ VBUS USB_DP RS = 33 Ω USB_DM RS = 33 Ω USB-B connector VSS aaa-010179 Fig 28.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 29. Slave mode operation of the on-chip oscillator In slave mode, couple the input clock signal with a capacitor of 100 pF (Figure 29), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This signal corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 18.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.5 Reset pad configuration VDD VDD VDD Rpu ESD 20 ns RC GLITCH FILTER reset PIN ESD VSS 002aaf274 Fig 32. Reset pad configuration 11.6 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See Figure 33. ADC Block Source ADC COMPARATOR Rmux Rsw <2 kΩ <1.3 kΩ Cia Rs Rin Cio VEXT VSS 002aah615 Fig 33.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Under nominal operating condition VDD = 3.3 V and with the maximum sampling frequency fs = 400 kHz, the parameters assume the following values: Cia = 1 pF (max) Rmux = 2 kΩ (max) Rsw = 1.3 kΩ (max) Cio = 7.1 pF (max) The effective input impedance with these parameters is Rin = 308 kΩ. 11.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm A B D terminal 1 index area E A A1 c detail X e1 e 9 16 C C A B C v w b y y1 C L 8 17 e e2 Eh 33 1 terminal 1 index area 24 32 X 25 Dh 0 2.5 scale Dimensions Unit mm 5 mm A(1) A1 b max 1.00 0.05 0.35 nom 0.85 0.02 0.28 min 0.80 0.00 0.23 c D(1) Dh E(1) 0.2 7.1 7.0 6.9 4.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm D B A terminal 1 index area A A1 E c detail X C e1 e 9 y1 C C A B C v w 1/2 e b y 16 L 17 8 e e2 Eh 1/2 e 24 1 terminal 1 index area 32 25 X Dh 0 2.5 Dimensions (mm are the original dimensions) Unit(1) mm A(1) A1 b max 0.05 0.30 nom 0.85 min 0.00 0.18 c D(1) Dh E(1) Eh 5.1 3.75 5.1 3.75 0.2 4.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm B D SOT1155-2 A ball A1 index area E A A2 A1 detail X e1 C e C A B C Øv Øw 1/2 e b y1 C y H e G F E e2 D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 solder mask open area not for solder ball 8 0 5 mm scale Dimensions Unit mm X A A1 A2 b max 1.10 0.30 0.80 0.35 nom 0.95 0.25 0.70 0.30 min 0.85 0.20 0.65 0.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 13. Soldering Footprint information for reflow soldering of HVQFN33 package Hx Gx see detail X P nSPx By Hy Gy SLy Ay nSPy C D SLx Bx Ax 0.60 solder land 0.30 solder paste detail X occupied area Dimensions in mm P Ax Ay Bx By C D Gx Gy Hx Hy SLx SLy nSPx nSPy 0.5 5.95 5.95 4.25 4.25 0.85 0.27 5.25 5.25 6.2 6.2 3.75 3.75 3 3 Issue date 11-11-15 11-11-20 002aag766 Fig 39.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of HVQFN33 package OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) W = 0.30 CU SPD = 1.00 SP LaE = 7.95 CU PIE = 7.25 PA+OA LbE = 5.80 CU evia = 4.25 evia = 1.05 0.45 DM SPE = 1.00 SP GapE = 0.70 SP 4.55 SR SEhtot = 2.70 SP EHS = 4.85 CU OwEtot = 5.10 OA OIE = 8.20 OA e = 0.65 0.45 DM GapD = 0.70 SP evia = 2.40 B-side SDhtot = 2.70 SP 4.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 41.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of TFBGA48 package SOT1155-2 Hx P P Hy see detail X solder land solder paste deposit solder land plus solder paste SL occupied area SP SR solder resist detail X DIMENSIONS in mm P SL SP SR Hx Hy 0.50 0.225 0.275 0.325 4.75 4.75 sot1155-2_fr Fig 42.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of LQFP64 package SOT314-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 13.300 13.300 10.300 10.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 10.500 10.500 13.550 13.550 sot314-2_fr Fig 43.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14. Abbreviations Table 20.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 16. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11U2x v.2.3 20140327 Product data sheet - LPC11U2X v.2.2 - LPC11U2X v.2.1 Part LPC11U22FBD48/301 added. LPC11U2X v.2.2 Modifications: LPC11U2X v.2.1 Modifications: 20140311 • • Open-drain I2C-bus and RESET pin descriptions updated for clarity. See Table 3.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 19. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.7 7.7.1 7.8 7.8.1 7.9 7.9.1 7.9.1.1 7.10 7.10.1 7.11 7.11.1 7.12 7.12.1 7.13 7.13.1 7.14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . .
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LPC11U2x NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 17.4 18 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Contact information. . . . . . . . . . . . . . . . . . . . . 72 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2014. All rights reserved.