Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 32-Bit 50 MHz I/O number 48

1. General description

The LPC11U6x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 50 MHz. The LPC11U6x support up to 256 KB of flash memory,

a 4 KB EEPROM, and 36 KB of SRAM.

The ARM Cortex-M0+ is an easy-to-use, energy-efficient core using a two-stage pipeline

and fast single-cycle I/O access.

The peripheral complement of the LPC11U6x includes a DMA controller, a CRC engine,

one full-speed USB device controller with XTAL-less low-speed mode, two I

C-bus

interfaces, up to five USARTs, two SSP interfaces, PWM/timer subsystem with six

configurable multi-purpose timers, a Real-Time Clock, one 12-bit ADC, temperature

sensor, function-configurable I/O ports, and up to 80 general-purpose I/O pins.

For additional documentation related to the LPC11U6x parts, see Section 17

“References”.

2. Features and benefits

 System:

 ARM Cortex-M0+ processor (version r0p1), running at frequencies of up to 50 MHz

with single-cycle multiplier and fast single-cycle I/O port.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 AHB Multilayer matrix.

 System tick timer.

 Serial Wire Debug (SWD) and JTAG boundary scan modes supported.

 Micro Trace Buffer (MTB) supported.

 Memory:

 Up to 256 KB on-chip flash programming memory with page erase.

 Up to 32 KB main SRAM.

 Up to two additional SRAM blocks of 2 KB each.

 Up to 4 KB EEPROM.

 ROM API support:

 Boot loader.

 USART drivers.

 I2C drivers.

 USB drivers.

 DMA drivers.

LPC11U6x

32-bit ARM Cortex-M0+ microcontroller; up to 256 KB flash

and 36 KB SRAM; 4 KB EEPROM; USB; 12-bit ADC

Rev. 1.2 — 26 May 2014 Product data sheet

Summary of content (96 pages)

PAGE 1
LPC11U6x 32-bit ARM Cortex-M0+ microcontroller; up to 256 KB flash and 36 KB SRAM; 4 KB EEPROM; USB; 12-bit ADC Rev. 1.2 — 26 May 2014 Product data sheet 1. General description The LPC11U6x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 50 MHz. The LPC11U6x support up to 256 KB of flash memory, a 4 KB EEPROM, and 36 KB of SRAM. The ARM Cortex-M0+ is an easy-to-use, energy-efficient core using a two-stage pipeline and fast single-cycle I/O access.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller        LPC11U6x Product data sheet  Power profiles.  Flash In-Application Programming (IAP) and In-System Programming (ISP).  32-bit integer division routines. Digital peripherals:  Simple DMA engine with 16 channels and programmable input triggers.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller  Power control:  Integrated PMU (Power Management Unit) to minimize power consumption.  Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode.  Wake-up from Deep-sleep and Power-down modes on external pin inputs and USART activity.  Power-On Reset (POR).  Brownout detect.  Unique device serial number for identification.  Single power supply (2.4 V to 3.6 V).  Separate VBAT supply for RTC.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC11U66JBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U67JBD48 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U67JBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 5. Marking n n Terminal 1 index area 1 aaa-011231 Fig 1. LQFP64/100 package marking Terminal 1 index area Fig 2.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 6.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7. Pinning information 25 PIO1_21 26 PIO0_8 27 PIO0_9 28 SWCLK/PIO0_10 29 PIO0_22 30 TDI/PIO0_11 31 TMS/PIO0_12 32 TDO/PIO0_13 33 TRST/PIO0_14 34 VREFP 35 VREFN 36 PIO1_13 7.
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LPC11U6x NXP Semiconductors 33 PIO2_18 34 VDD 35 PIO1_21 36 PIO2_19 37 PIO0_8 38 PIO0_9 39 SWCLK/PIO0_10 40 PIO0_22 41 PIO1_29 42 TDI/PIO0_11 43 TMS/PIO0_12 44 PIO1_30 45 TDO/PIO0_13 46 TRST/PIO0_14 47 VREFP 48 VREFN 32-bit ARM Cortex-M0+ microcontroller PIO1_13 49 32 PIO2_15 SWDIO/PIIO0_15 50 31 PIO1_28 PIO0_16/WAKEUP 51 30 PIO0_7 PIO0_23 52 29 PIO0_6 VDDA 53 28 PIO1_24 VSSA 54 27 PIO2_7 PIO1_9 55 26 USB_DP PIO0_17 56 25 USB_DM LPC11U6XJBD64 VSS 57 23 PIO1_23 VDD 59 2
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7.2 Pin description LQFP100 RESET/PIO0_0 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions. 3 4 8 [8] Reset Type state[1] Description of pin functions I; PU RESET — External reset input with 20 ns glitch filter.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO0_7 PIO0_8 PIO0_9 SWCLK/PIO0_10 TDI/PIO0_11 TMS/PIO0_12 LPC11U6x Product data sheet LQFP100 PIO0_6 23 29 44 LQFP48 Symbol LQFP64 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller TRST/PIO0_14 SWDIO/PIO0_15 PIO0_16/WAKEUP PIO0_17 PIO0_18 PIO0_19 LPC11U6x Product data sheet LQFP100 TDO/PIO0_13 32 45 68 LQFP48 Symbol LQFP64 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO0_21 PIO0_22 PIO0_23 PIO1_0 PIO1_1 PIO1_2 PIO1_3 PIO1_4 LPC11U6x Product data sheet LQFP100 PIO0_20 10 12 17 LQFP48 Symbol LQFP64 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO1_6 PIO1_7 PIO1_8 PIO1_9 PIO1_10 PIO1_11 PIO1_12 PIO1_13 LPC11U6x Product data sheet LQFP100 PIO1_5 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO1_15 PIO1_16 PIO1_17 PIO1_18 PIO1_19 PIO1_20 PIO1_21 PIO1_22 LPC11U6x Product data sheet LQFP100 PIO1_14 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO1_24 PIO1_25 PIO1_26 PIO1_27 PIO1_28 PIO1_29 PIO1_30 PIO1_31 LPC11U6x Product data sheet LQFP100 PIO1_23 18 23 35 LQFP48 Symbol LQFP64 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LQFP100 PIO2_0 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions. 6 8 12 PIO2_1 7 9 PIO2_2 12 16 [10] Reset Type state[1] Description of pin functions I; PU 13 [10] I; PU 21 [6] I; PU IO PIO2_0 — General-purpose digital input/output pin.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller PIO2_14 PIO2_15 PIO2_16 PIO2_17 PIO2_18 PIO2_19 PIO2_20 PIO2_21 LQFP100 PIO2_13 LQFP64 Symbol LQFP48 Table 3. Pin description Pin functions are selected through the IOCON registers. See Table 2 for availability of USART3 and USART4 pin functions.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LQFP100 Symbol Reset Type state[1] VBAT 47 63 99 - - Battery supply. Supplies power to the RTC. If no battery is used, tie VBAT to VDD. VSSA 41 54 85 - - Analog ground. VSSAshould typically be the same voltage as VSS but should be isolated to minimize noise and error. VSSA should be tied to VSS if the ADC is not used. VSS 43, 57, 91, 2, 3, 7, 5 7 11, 53, 70 - - Ground. [1] LQFP48 LQFP64 Table 3.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8. Functional description 8.1 ARM Cortex-M0+ core The ARM Cortex-M0+ core runs at an operating frequency of up to 50 MHz using a two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer. 8.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller TEST/DEBUG INTERFACE ARM CORTEX-M0+ USB DMA masters System bus slaves FLASH MAIN SRAM0 SRAM USB SRAM1 ROM EEPROM SCTIMER0/PWM SCTIMER1/PWM HS GPIO PINT/PATTERN MATCH CRC USB REGISTERS DMA REGISTERS AHB-TO-APB BRIDGE CT32B0 PMU USART0 WWDT I2C0 AHB MULTILAYER MATRIX CT32B1 ADC FLASHCTRL USART4 SSP1 USART2 I2C1 SSP0 RTC IOCON GROUP0 USART3 CT16B0 CT16B1 DMA TRIGMUX SYSCON GROUP1 USART1 USART2 = master-slave co
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.3 On-chip flash programming memory The LPC11U6x contain up to 256 KB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip bootloader software. The flash memory is divided into 24 x 4 KB and 5 x 32 KB sectors. Individual pages of 256 byte each can be erased using the IAP erase page command. 8.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 4 GB LPC11U6x 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 0xE000 0000 reserved 0xA000 8000 GPIO PINT 0xA000 4000 GPIO 0xA000 0000 APB peripherals reserved 0x5001 0000 SCTIMER1/PWM 0x5000 E000 SCTIMER0/PWM 0x4007 8000 0x5000 C000 reserved 0x5000 8000 DMA 0x5000 4000 CRC 0x4008 4000 28 USART2 27 USART1 24 GPIO GROUP1 interrupt 23 GPIO GROUP0 interrupt 22 SSP1 0x4008 0000 APB peripherals 0x2000 4000 re
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.8.1 Features • Controls system exceptions and peripheral interrupts. • In the LPC11U6x, the NVIC supports vectored interrupts for each of the peripherals and the eight pin interrupts.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Digital filter with programmable filter constant on all pins. The minimum filter constant is 1/50 MHz = 20 ns. 8.9.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LPC11U6x use accelerated GPIO functions: • GPIO registers are on the ARM Cortex M0+ IO bus for fastest possible single-cycle I/O timing, allowing GPIO toggling with rates of up to 25 MHz. • An entire port value can be written in one instruction. • Mask, set, and clear operations are supported for the entire port. 8.10.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.12 GPIO group interrupts The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts. For each port/pin connected to one of the two the GPIO Grouped Interrupt blocks (GINT0 and GINT1), the GPIO grouped interrupt registers determine which pins are enabled to generate interrupts and w the active polarities of each of those inputs.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.14 USB interface The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of the devices. All transactions are initiated by the host controller.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.15.1 Features • Maximum USART0 data bit rate of 3.125 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous slave and master mode. • • • • 16 byte receive and transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • • • • • • Received data and status can optionally be read from a single register Break generation and detection. Receive data is 2 of 3 sample "voting". Status flag set when one sample differs. Built-in Baud Rate Generator with auto-baud function. A fractional rate divider is shared among all USARTs.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.18.1 Features • One I2C-interface (I2C0) is an I2C-bus compliant interface with open-drain pins. The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s. • One I2C-interface (I2C1) uses standard digital pins. The I2C-bus interface supports bit rates up to 400 kbit/s. • • • • • Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 4.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.19.1.1 Features • Each SCTimer/PWM supports: – 5 match/capture registers. – 6 events. – 8 states. – 4 inputs and 4 outputs. • Counter/timer features: – Each SCTimer is configurable as two 16-bit counters or one 32-bit counter. – Counters can be clocked by the system clock or selected input. – Configurable as up counters or up-down counters. – Configurable number of match and capture registers.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.19.2 General purpose external event counter/timers (CT32B0/1 and CT16B0/1) The LPC11U6x includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Optional warning interrupt can be generated at a programmable time before watchdog time-out. • Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is required to disable the WWDT. • • • • Incorrect feed sequence causes reset or interrupt, if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.24 Temperature sensor The temperature sensor transducer uses an intrinsic pn-junction diode reference and outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage varies inversely with device temperature with an absolute accuracy of better than ±5 C over the full temperature range (40 C to +105 C) for typical samples. The temperature sensor is approximately linear with a slight curvature.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.25 Clocking and power control 8.25.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.25.2 Power domains The LPC11U6x provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup registers. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD) is used to operate the RTC whenever VDD is present.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.25.3.1 Internal RC oscillator The IRC can be used as the clock source for the WDT, the USB PLL in low-speed USB applications, or as the clock that drives the system PLL and then the CPU. The nominal IRC frequency is 12 MHz. Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11U6x use the IRC as the clock source. Software can later switch to one of the other available clock sources. 8.25.3.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.25.6 Wake-up process The LPC11U6x begin operation by using the 12 MHz IRC oscillator as the clock source at power-up and when awakened from Deep power-down mode. This mechanism allows chip operation to resume quickly. If the application uses the main oscillator or the PLL, software must enable these components and wait for them to stabilize. Only then can the system use the PLL and main oscillator as a clock source. 8.25.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.25.7.3 Deep-sleep mode In Deep-sleep mode, the LPC11U6x core is in Sleep mode and all peripheral clocks and all clock sources are off except for the IRC. The IRC output is disabled unless the IRC is selected as input to the watchdog timer. In addition, all analog blocks are shut down and the flash is in standby mode.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The internal reset status is reflected on the RSTOUT pin. In Deep power-down mode, an external pull-up resistor is required on the RESET pin.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.27 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC11U6x is in reset.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD supply voltage VDDA analog supply voltage Vref reference voltage VBAT battery supply voltage Conditions [2] on pin VREFP input voltage VI 5 V tolerant I/O pins; only valid when the VDD(IO) supply voltage is present Max Unit 0.5 4.6 V 0.5 4.6 V 0.5 4.6 V 0.5 4.6 V [3][4] 0.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [4] Including the voltage on outputs in 3-state mode. [5] VDD(IO) present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD(IO) is powered down. [6] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 7. Symbol Thermal resistance value (C/W): ±15 % Parameter Conditions Typ Unit thermal resistance junction-to-ambient JEDEC (4.5 in  4 in) 0 m/s 58 C/W 1 m/s 51 C/W 2.5 m/s 47 C/W 0 m/s 81 C/W 1 m/s 66 C/W 2.5 m/s 60 C/W LQFP64 ja 8-layer (4.5 in  3 in) jc thermal resistance junction-to-case 18 C/W jb thermal resistance junction-to-board 23 C/W 0 m/s 49 C/W 1 m/s 44 C/W 2.
PAGE 47
LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions IDD supply current Active mode; code Min Typ[1] Max Unit - 2.3 - mA - 1.5 - mA - 7.8 - mA - 6.4 - mA - 1.2 - mA - 0.8 - mA - 3.3 - mA - 2.8 - mA - 275 350 A - - 640 A - 5 22 A - - 130 A - 1.2 5 A - - 14 - 550 - nA - 0 - - - 0 - - - 1.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage VDD  2.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Typ[1] Max Symbol Parameter Conditions Min Unit VOH HIGH-level output voltage IOH = 12 mA; 2.4 V  VDD  2.5 V VDD  0.4 - - V IOH = 20 mA; 2.5 V  VDD  3.6 V VDD  0.4 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 2.4 V  VDD  2.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOLS LOW-level short-circuit output current drive LOW; pad connected to ground - - 125 mA IOHS HIGH-level short-circuit drive HIGH; pad connected to output current ground - - 125 mA 0.5 1.8 1.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller VDD IOL Ipd pin PIO0_n + A IOH Ipu pin PIO0_n - + A aaa-010819 Fig 13. Pin input/output current measurement LPC11U6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 26 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.1 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW.
PAGE 53
LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,'' P$ 0+] 0+] 0+] 0+] 0+] 0+] WHPSHUDWXUH & Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F; all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz to 6 MHz: IRC enabled; PLL disabled.
PAGE 54
LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,'' ȝ$ 9 9 9 9 9 7 & Conditions: BOD disabled; all oscillators and analog blocks disabled Fig 17. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD DDD ,'' ȝ$ 7 & Conditions: BOD disabled; all oscillators and analog blocks disabled; VDD = 2.4 V to 3.6 V.
PAGE 55
LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,'' ȝ$ 9 9 9 9 9 7 & Conditions: RTC running; VBAT = 0 V Fig 19. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD DDD ,%$7 ȝ$ 7 & Conditions: RTC not running; VBAT = 3.0 V; VDD floating. Fig 20.
PAGE 56
LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.2 CoreMark data aaa-011173 2.5 CM (((iterations/s)/MHz)) 2.25 cpu performance efficiency default/low-current 2 aaa-011174 2.5 CM (((iterations/s)/MHz)) 2.25 cpu performance efficiency default/low-current 2 1.75 1.75 1.5 1.5 1.25 1.25 1 1 0 10 20 30 40 system clock frequency (MHz) 50 Measured with Keil uVision v.4.72. 0 10 20 30 40 system clock frequency (MHz) 50 Measured with Keil uVision v.4.60.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller The power profiles optimize the chip performance for power consumption or core efficiency by controlling the flash access and core power. As shown in Figure 21 and Figure 22, different power modes result in different CoreMark scores reflecting the trade-off of efficiency and power consumption. In CPU and efficiency modes, the power profiles aim to keep the core efficiency at a maximum for the given system frequency.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 9. Power consumption for individual analog and digital blocks …continued Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz RTC - 0.02 0.10 - WWDT - 0.05 0.17 Main clock selected as clock source for the WDT. I2C0 - 0.05 0.22 - I2C1 - 0.05 0.18 - SSP0 - 0.15 0.59 - SSP1 - 0.15 0.58 - USART0 - 0.31 1.19 - USART1 - 0.12 0.50 - USART2 - 0.13 0.49 - USART3 + USART4 - 0.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.4 Electrical pin characteristics DDD 92+ 9 9 & 9 & 9 & 9 & ,2+ P$ 9 & & 9 & & 9 & & 9 & & DDD 92+ 9 Conditions: VDD = 2.4 V; ON pin PIO0_7 and PIO1_31. ,2+ P$ Conditions: VDD = 3.3 V; ON pin PIO0_7 and PIO1_31. Fig 23.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,2/ P$ DDD ,2/ P$ 9 & & 9 & & 9 & & 9 & & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 92/ 9 Conditions: VDD = 2.4 V; standard port pins and high-drive pins PIO0_7 and PIO1_31. 92/ 9 Conditions: VDD = 3.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,38 ȝ$ DDD ,38 ȝ$ 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9, 9 Conditions: VDD = 2.4 V; standard port pins. 9, 9 Conditions: VDD = 3.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12. Dynamic characteristics 12.1 Flash/EEPROM memory Table 10. Flash characteristics Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. W&+&/ W&+&; W&/&+ W&/&; 7F\ FON DDD Fig 29. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 12.3 Internal oscillators Table 13. Dynamic characteristics: IRC Tamb = 40 C to +105 C; 2.7 V  VDD  3.6 V[1].
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 14. Dynamic characteristics: WatchDog oscillator Symbol Parameter Conditions fosc(int) internal oscillator frequency DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register Min Typ[1] Max Unit [2][3] - 9.4 - kHz [2][3] - 2300 - kHz [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 16. Dynamic characteristic: I2C-bus pins[1] …continued Tamb = 40 C to +105 C.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller WI 6'$ W68 '$7 W+' '$7 WI 6&/ W9' '$7 W+,*+ W/2: 6 I6&/ DDD Fig 31. I2C-bus pins clock timing 12.6 SSP interface Table 17.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO DATA VALID tv(Q) th(Q) DATA VALID MOSI DATA VALID tDH tDS DATA VALID MISO CPHA = 1 tDH CPHA = 0 DATA VALID 002aae829 Fig 32.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.7 USART interface The maximum USART bit rate for all USARTs is 3.125 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous slave and master mode. Table 18. USART dynamic characteristics USART0 Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V; CL = 10 pF. Simulated parameters sampled at the 50 % level of the falling or rising edge; values guaranteed by design.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7F\ FON 8QB6&/. &/.32/ 8QB6&/. &/.32/ WY 4 WK 4 67$57 7;' %,7 %,7 WVX ' WK ' 67$57 5;' %,7 %,7 DDD Fig 34. USART timing 12.8 SCTimer/PWM output timing Table 20. SCTimer/PWM output dynamic characteristics Tamb = 40 C to 105 C; 2.4 V <= VDD <= 3.6 V.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 13. Characteristics of analog peripherals Table 21. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 2 Min Typ Max Unit assertion - 2.54 - V de-assertion - 2.68 - V assertion - 2.82 - V de-assertion - 2.93 - V assertion - 2.34 - V de-assertion - 2.49 - V assertion - 2.62 - V de-assertion - 2.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 22. 12-bit ADC static characteristics Tamb = 40 C to +105 C; VDD = 2.4 V to 3.6 V; VREFP = VDDA; VSSA = 0; VREFN = VSSA. ADC calibrated at T = 25C. Symbol Parameter Conditions Min Typ Max Unit [1] VIA analog input voltage [2] 0 - VDDA V Cia analog input capacitance [3] - - 0.32 pF fclk(ADC) ADC clock frequency VDDA 2.7 V 50 MHz VDDA 2.4 V 25 MHz sampling frequency VDDA 2.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP - VSS 4096 002aaf436 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller ADC R1 = 0.25 kΩ...2.5 kΩ ADCn_0 Cio Rsw = 5 Ω...25 Ω ADCn_[1:11] DAC CDAC Cio Cia aaa-011748 Fig 36. ADC input impedance Table 23. Temperature sensor static and dynamic characteristics VDDA = 2.4 V to 3.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD 92 P9 WHPSHUDWXUH & VDDA = 3.3 V; measured on a typical silicon sample. Fig 37. Typical LLS fit of the temperature sensor output voltage LPC11U6x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 26 May 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14. Application information 14.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 22: • The ADC input trace must be short and as close as possible to the LPC11U6x chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the USB connector. The voltage divider ratio should be such that the USB_VBUS pin is greater than 0.7 VDD to indicate a logic HIGH while below the 3.6 V allowable maximum voltage. For the following operating conditions VBUSmax = 5.25 V VDD = 3.6 V, the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LPC1xxx VDD REGULATOR USB_CONNECT USB R1 1.5 kΩ USB_VBUS(1) USB_VBUS(2) RS = 33 Ω USB_DP RS = 33 Ω USB_DM VBUS D+ D- USB-B connector VSS aaa-010821 Two options exist for connecting VBUS to the USB_VBUS pin: (1) Connect the regulator output to USB_VBUS. In this case, the USB_VBUS signal is HIGH whenever the part is powered. (2) Connect the VBUS signal directly from the connector to the USB_VBUS pin.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller SYSCON 12 MHz IRC USB PLL 48 MHz USBCLKDIV /8 USB main clock = 6 MHz VDD USB_CONNECT USB R1 1.5 kΩ USB_VBUS RS = 33 Ω USB_DP RS = 10 Ω RS = 33 Ω USB_DM RS = 10 Ω D+ D- USB-B connector VSS aaa-011021 Fig 40. USB interface for low-speed, XTAL-less operation 14.4 XTAL input and crystal oscillator component selection The input voltage to the on-chip oscillators is limited to 1.8 V.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller External components and models used in oscillation mode are shown in Figure 42 and in Table 26 and Table 27. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 must be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS).
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14.5 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plane.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14.6 RTC oscillator component selection The 32 kHz crystal must be connected to the part via the RTCXIN and RTCXOUT pins as shown in Figure 43. If the RTC is not used, the RTCXIN pin can be grounded. LPC1xxx L RTCXIN RTCXOUT = CL CP XTAL RS CX2 CX1 aaa-010822 Fig 43. RTC oscillator components Select Cx1 and Cx2 based on the external 32 kHz crystal used in the application circuitry.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 3.3 V 3.3 V SWD connector Note 6 ~10 kΩ - 100 kΩ SWDIO/PIO0_15 1 2 3 4 5 6 n.c. 7 8 n.c. 9 10 SWCLK/PIO0_10 PIO2_0/XTALIN ~10 kΩ - 100 kΩ C1 n.c. Note 1 DGND C2 PIO2_1/XTALOUT RESET/PIO0_0 DGND RTCXIN Note 2 C3 VSS DGND C4 RTCXOUT DGND DGND 0.1 μF AGND Note 3 VDD (2 to 5 pins) VSSA 3.3 V 0.01 μF LPC11U6x PIO0_1 DGND Note 4 3.3 V VDDA ISP select pins PIO0_3 0.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14.8 Termination of unused pins Table 28 shows how to terminate pins that are not used in the application. In many cases, unused pins may should be connected externally or configured correctly by software to minimize the overall power consumption of the part. Unused pins with GPIO function should be configured as outputs set to LOW with their internal pull-up disabled.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14.9 Pin states in different power modes Table 29. Pin states in different power modes Pin Active Sleep Deep-sleep/Powerdown PIOn_m pins (not As configured in the IOCON[1]. Default: internal pull-up enabled. I2C) Deep power-down Floating. PIO0_4, PIO0_5 (open-drain I2C-bus pins) As configured in the IOCON[1]. Floating. RESET Reset function enabled. Default: input, internal pull-up enabled.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 15. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M θ bp Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 16. Soldering Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 48.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Footprint information for reflow soldering of LQFP64 package SOT314-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 13.300 13.300 10.300 10.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 10.500 10.500 13.550 13.550 sot314-2_fr Fig 49.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Footprint information for reflow soldering of LQFP100 package SOT407-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 17.300 17.300 14.300 14.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 14.500 14.500 17.550 17.550 sot407-1 Fig 50.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 17. References LPC11U6x Product data sheet [1] LPC11U6x User manual UM10732: http://www.nxp.com/documents/user_manual/UM10732.pdf [2] LPC11U6x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC11U6X.pdf [3] Technical note ADC design guidelines: http://www.nxp.com/documents/technical_note/TN00009.pdf All information provided in this document is subject to legal disclaimers. Rev. 1.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 18. Revision history Table 30. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11U6x v.1.2 20140526 Product data sheet - Modifications: LPC11U6x v.1.1 Modifications: LPC11U6x v.1 LPC11U6x Product data sheet LPC11U6x v.1.1 • • Part marking updated with revision indicator. • • • Section 14.7 “Connecting power, clocks, and debug functions” added.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC11U6x NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 USART interface. . . . . . . . . . . . . . . . . . . . . . . 12.8 SCTimer/PWM output timing . . . . . . . . . . . . . 13 Characteristics of analog peripherals . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 14.1 ADC usage notes . . . . . . . . . . . . . . . . . . . . . . 14.2 Typical wake-up times . . . . . . . . . . . . . . . . . . 14.