LPC1315/16/17/45/46/47 32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM Rev. 3 — 20 September 2012 Product data sheet 1. General description The LPC1315/16/17/45/46/47 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
NXP Semiconductors LPC1315/16/17/45/46/47 32-bit ARM Cortex-M3 microcontroller Debug options: Standard JTAG test interface for BSDL. Serial Wire Debug. Support for ETM ARM Cortex-M3 debug time stamping. Digital peripherals: Up to 51 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, input inverter, and pseudo open-drain mode. Eight pins support programmable glitch filter.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Processor wake-up from Deep-sleep and Power-down modes via reset, selectable GPIO pins, watchdog interrupt, or USB port activity. Processor wake-up from Deep power-down mode using one special function pin. Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes. Power-On Reset (POR).
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 4.1 Ordering options Table 2.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 5.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6. Pinning information PIO0_19/TXD/CT32B0_MAT1 PIO0_18/RXD/CT32B0_MAT0 PIO0_17/RTS/CT32B0_CAP0/SCLK VDD PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_23/AD7 PIO0_16/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO0_15/AD4/CT32B1_MAT2 31 30 29 28 27 26 25 terminal 1 index area 32 6.
LPC1315/16/17/45/46/47 NXP Semiconductors VDD PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_23/AD7 PIO0_16/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO0_15/AD4/CT32B1_MAT2 27 26 25 PIO0_17/RTS/CT32B0_CAP0/SCLK 28 PIO0_18/RXD/CT32B0_MAT0 30 29 PIO0_19/TXD/CT32B0_MAT1 31 terminal 1 index area 32 32-bit ARM Cortex-M3 microcontroller PIO1_19/DTR/SSEL1 1 24 TRST/PIO0_14/AD3/CT32B1_MAT1 RESET/PIO0_0 2 23 TDO/PIO0_13/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE 3 22 TMS/PIO0_12/AD1/CT32B1_CAP0 XTA
LPC1315/16/17/45/46/47 NXP Semiconductors 25 PIO1_31 26 PIO1_21/DCD/MISO1 27 PIO0_8/MISO0/CT16B0_MAT0 28 PIO0_9/MOSI0/CT16B0_MAT1/SWO 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 30 PIO0_22/AD6/CT16B1_MAT1/MISO1 31 PIO1_29/SCK0/CT32B0_CAP1 32 TDI/PIO0_11/AD0/CT32B0_MAT3 33 TMS/PIO0_12/AD1/CT32B1_CAP0 34 TDO/PIO0_13/AD2/CT32B1_MAT0 35 TRST/PIO0_14/AD3/CT32B1_MAT1 36 PIO1_13/DTR/CT16B0_MAT0/TXD 32-bit ARM Cortex-M3 microcontroller PIO1_14/DSR/CT16B0_MAT1/RXD 37 24 PIO1_28/CT32B0_CAP0/SCLK PIO1_22/RI/MOS
LPC1315/16/17/45/46/47 NXP Semiconductors 25 PIO1_31 26 PIO1_21/DCD/MISO1 27 PIO0_8/MISO0/CT16B0_MAT0 28 PIO0_9/MOSI0/CT16B0_MAT1/SWO 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 30 PIO0_22/AD6/CT16B1_MAT1/MISO1 31 PIO1_29/SCK0/CT32B0_CAP1 32 TDI/PIO0_11/AD0/CT32B0_MAT3 33 TMS/PIO0_12/AD1/CT32B1_CAP0 34 TDO/PIO0_13/AD2/CT32B1_MAT0 35 TRST/PIO0_14/AD3/CT32B1_MAT1 36 PIO1_13/DTR/CT16B0_MAT0/TXD 32-bit ARM Cortex-M3 microcontroller PIO1_14/DSR/CT16B0_MAT1/RXD 37 24 PIO1_28/CT32B0_CAP0/SCLK PIO1_22/RI/MOS
LPC1315/16/17/45/46/47 NXP Semiconductors 33 VDD 34 PIO1_2 35 PIO1_21 36 PIO0_8 37 PIO0_9 38 SWCLK/PIO0_10 39 PIO1_8 40 PIO0_22 41 PIO1_29 42 TDI/PIO0_11 43 PIO1_11 44 TMS/PIO0_12 45 TDO/PIO0_13 46 TRST/PIO0_14 47 PIO1_13 48 VREFN 32-bit ARM Cortex-M3 microcontroller PIO1_14 49 32 PIO1_5 PIO1_3 50 31 PIO1_28 PIO1_22 51 30 PIO0_7 SWDIO/PIO0_15 52 29 PIO0_6 PIO0_16 53 28 PIO1_18 VSS 54 27 PIO1_24 VSSA 55 26 n.c. PIO0_23 56 25 n.c.
LPC1315/16/17/45/46/47 NXP Semiconductors 33 VDD 34 PIO1_2 35 PIO1_21 36 PIO0_8 37 PIO0_9 38 SWCLK/PIO0_10 39 PIO1_8 40 PIO0_22 41 PIO1_29 42 TDI/PIO0_11 PIO1_14 49 32 PIO1_5 PIO1_3 50 31 PIO1_28 PIO1_22 51 30 PIO0_7 SWDIO/PIO0_15 52 29 PIO0_6 PIO0_16 53 28 PIO1_18 VSS 54 27 PIO1_24 VSSA 55 26 USB_DP PIO0_23 56 25 USB_DM 24 PIO1_23 VDD 58 23 PIO1_17 VDDA 59 22 PIO0_21 PIO0_17 60 21 PIO0_5 PIO0_18 61 20 PIO0_4 PIO0_19 62 19 PIO0_3 PIO1_16 63 18 PIO1_20
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description (LPC1315/16/17 - no USB) TDI/PIO0_11/AD0/ CT32B0_MAT3 TMS/PIO0_12/AD1/ CT32B1_CAP0 TDO/PIO0_13/AD2/ CT32B1_MAT0 TRST/PIO0_14/AD3/ CT32B1_MAT1 SWDIO/PIO0_15/AD4/ CT32B1_MAT2 PIO0_16/AD5/ CT32B1_MAT3/WAKEUP PIO0_17/RTS/ CT32B0_CAP0/SCLK LPC1315_16_17_45_46_47 Product data sheet HVQFN33 38 29 19 42 44 45 46 52 53 60 32 33 34 35 39 40 45 21 22 23 24 25 26 30 [3] [6] [6] [6] [6
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description (LPC1315/16/17 - no USB) PIO0_20/CT16B1_CAP0 PIO0_21/CT16B1_MAT0/ MOSI1 PIO0_22/AD6/ CT16B1_MAT1/MISO1 HVQFN33 61 46 31 62 11 22 40 47 9 17 30 32 [3] [3] 7 [3] 12 [3] 20 [6] PIO0_23/AD7 56 42 27 [6] PIO1_0/CT32B1_MAT0 1 - - [3] PIO1_1/CT32B1_MAT1 17 - - [3] PIO1_2/CT32B1_MAT2 34 - - [3] PIO1_3/CT32B1_MAT3 50 - - [3] PIO1_4/CT32B1_CAP0 16 - - [3] Description T
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description (LPC1315/16/17 - no USB) PIO1_14/DSR/ CT16B0_MAT1/RXD PIO1_15/DCD/ CT16B0_MAT2/SCK1 HVQFN33 47 36 - 49 57 PIO1_16/RI/CT16B0_CAP0 63 PIO1_17/CT16B0_CAP1/ RXD PIO1_18/CT16B1_CAP1/ TXD PIO1_19/DTR/SSEL1 PIO1_20/DSR/SCK1 PIO1_21/DCD/MISO1 PIO1_22/RI/MOSI1 PIO1_23/CT16B1_MAT1/ SSEL1 PIO1_24/CT32B0_MAT0 LPC1315_16_17_45_46_47 Product data sheet 23 28 3 18 35 51 24 27 37 43 48 - - 2 1
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description (LPC1315/16/17 - no USB) PIO1_26/CT32B0_MAT2/ RXD PIO1_27/CT32B0_MAT3/ TXD PIO1_28/CT32B0_CAP0/ SCLK HVQFN33 2 1 - 14 15 31 11 12 24 31 [3] - [3] [3] - [3] - PIO1_29/SCK0/ CT32B0_CAP1 41 PIO1_31 - 25 - n.c. 25 19 - n.c. 26 20 - [3] - [3] Description Type LQFP48 PIO1_25/CT32B0_MAT1 LQFP64 Symbol Reset state[1] Table 3.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description (LPC1315/16/17 - no USB) LQFP48 HVQFN33 Reset state[1] Type Description LQFP64 Symbol VREFP 64 - - - - ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC. This pin should be tied to 3.3 V if the ADC is not used.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description (LPC1345/46/47 - with USB) HVQFN33 4 3 2 5 PIO0_2/SSEL0/ CT16B0_CAP0 13 PIO0_3/USB_VBUS 19 PIO0_4/SCL PIO0_5/SDA 20 21 PIO0_6/USB_CONNECT/ SCK0 29 PIO0_7/CTS 30 PIO0_8/MISO0/ CT16B0_MAT0 LPC1315_16_17_45_46_47 Product data sheet 36 4 10 14 15 16 22 23 27 [2] 3 [3] 8 [3] 9 [3] 10 [4] 11 15 [4] [3] 16 [5] 17 [3] Description Type PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGG
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description (LPC1345/46/47 - with USB) SWCLK/PIO0_10/SCK0/ CT16B0_MAT2 TDI/PIO0_11/AD0/ CT32B0_MAT3 TMS/PIO0_12/AD1/ CT32B1_CAP0 TDO/PIO0_13/AD2/ CT32B1_MAT0 TRST/PIO0_14/AD3/ CT32B1_MAT1 SWDIO/PIO0_15/AD4/ CT32B1_MAT2 PIO0_16/AD5/ CT32B1_MAT3/WAKEUP LPC1315_16_17_45_46_47 Product data sheet HVQFN33 37 28 18 38 42 44 45 46 52 53 29 32 33 34 35 39 40 19 21 22 23 24 25 26 [3] [3] [6] [6]
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description (LPC1345/46/47 - with USB) PIO0_19/TXD/ CT32B0_MAT1 HVQFN33 60 45 30 61 62 46 47 31 32 [3] [3] [3] PIO0_20/CT16B1_CAP0 11 9 7 [3] PIO0_21/CT16B1_MAT0/ MOSI1 22 17 12 [3] PIO0_22/AD6/ CT16B1_MAT1/MISO1 PIO0_23/AD7 PIO1_0/CT32B1_MAT0 PIO1_1/CT32B1_MAT1 PIO1_2/CT32B1_MAT2 PIO1_3/CT32B1_MAT3 PIO1_4/CT32B1_CAP0 PIO1_5/CT32B1_CAP1 PIO1_7 PIO1_8 LPC1315_16_17_45_46_47 Product data sheet 40
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin description (LPC1345/46/47 - with USB) PIO1_13/DTR/ CT16B0_MAT0/TXD PIO1_14/DSR/ CT16B0_MAT1/RXD PIO1_15/DCD/ CT16B0_MAT2/SCK1 LPC1315_16_17_45_46_47 Product data sheet I; PU I/O PIO1_11 — General purpose digital input/output pin. - [3] HVQFN33 47 49 57 23 3 PIO1_23/CT16B1_MAT1/ SSEL1 - LQFP48 43 PIO1_19/DTR/SSEL1 PIO1_22/RI/MOSI1 PIO1_10 — General purpose digital input/output pin.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Pin description (LPC1345/46/47 - with USB) PIO1_25/CT32B0_MAT1 HVQFN33 27 21 - 2 PIO1_26/CT32B0_MAT2/ RXD 14 PIO1_27/CT32B0_MAT3/ TXD 15 PIO1_28/CT32B0_CAP0/ SCLK PIO1_29/SCK0/ CT32B0_CAP1 PIO1_31 31 41 - 1 11 12 24 31 25 [3] - [3] [3] - [3] - [3] - [3] - Description Type LQFP48 PIO1_24/CT32B0_MAT0 LQFP64 Symbol Reset state[1] Table 4.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin description (LPC1345/46/47 - with USB) LQFP48 HVQFN33 Reset state[1] Type Description LQFP64 Symbol VREFP 64 - - - - ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC. This pin should be tied to 3.3 V if the ADC is not used.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7. Functional description 7.1 On-chip flash programming memory The LPC1315/16/17/45/46/47 contain up to 64 kB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. Flash updates via USB are supported as well. The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1315/16/17/45/46/47 4 GB 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 0xE000 0000 reserved APB peripherals 26 - 31 reserved 0x5000 4000 GPIO 0x5000 0000 reserved 0x4008 4000 USB reserved 2 kB USB SRAM (LPC134x) 24 GPIO GROUP1 interrupt 23 GPIO GROUP0 interrupt 22 SSP1 20 - 21 reserved 0x4000 0000 19 GPIO pin interrupt 0x2000 4800 18 system control 0x2000 4000 17 IOCON 0x2000 0800 16 15 S
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.7 IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.8.1 Features • • • • GPIO pins can be configured as input or output by software. All GPIO pins default to inputs with interrupt disabled at reset. Pin registers allow pins to be sensed and set individually. Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • Port interrupts can be triggered by any pin or pins in each port. 7.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The USART includes full modem control, support for synchronous mode, and a smart card interface. The RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The USART uses a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.10.1 Features • • • • • Maximum USART data bit rate of 3.125 Mbit/s.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.12.1 Features • The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.14.1 Features • A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. • Counter or timer operation. • One capture channel per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.17.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller SYSTEM CLOCK DIVIDER CPU, system control, PMU system clock n memories, peripheral clocks SYSAHBCLKCTRLn (AHB clock enable) IRC oscillator main clock SSP0 PERIPHERAL CLOCK DIVIDER SSP0 USART PERIPHERAL CLOCK DIVIDER UART SSP1 PERIPHERAL CLOCK DIVIDER SSP1 USB 48 MHz CLOCK DIVIDER USB CLKOUT PIN CLOCK DIVIDER CLKOUT pin watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillat
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC1315/16/17/45/46/47 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.18.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC1315/16/17/45/46/47, the system oscillator must be used to provide the clock source to USB.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.18.5.4 Power-down mode In Power-down mode, the LPC1315/16/17/45/46/47 is in Sleep-mode and all peripheral clocks and all clock sources are off with the exception of watchdog oscillator if selected. In addition all analog blocks and the flash are shut down. In Power-down mode, the user has the option to keep the BOD circuit running for BOD protection.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.18.6.3 Code security (Code Read Protection - CRP) This feature of the LPC1315/16/17/45/46/47 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP.
NXP Semiconductors LPC1315/16/17/45/46/47 32-bit ARM Cortex-M3 microcontroller The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC1315/16/17/45/46/47 is in reset. Remark: Boundary scan operations should not be started until 250 s after POR, and the test TAP should be reset after the boundary scan. Boundary scan is not affected by Code Read Protection.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD supply voltage (core and external rail) VI input voltage Conditions 5 V tolerant I/O pins; only valid when the VDD supply voltage is present [2] Min Max Unit 2.0 3.6 V 0.5 +5.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9. Static characteristics Table 6. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) IDD supply current Conditions [2] Min Typ[1] Max Unit 2.0 3.3 3.6 V - 0.5 - mA - 2 - mA - 14 - mA - 1 - mA Active mode; VDD = 3.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 6. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOH 2.5 V VDD 3.6 V; VOH = VDD 0.4 V 4 - - mA 2.0 V VDD 2.5 V; VOH = VDD 0.4 V 3 - - mA 2.5 V VDD 3.6 V; VOL = 0.4 V 4 - - mA IOL HIGH-level output current LOW-level output current 2.0 V VDD 2.5 V; VOL = 0.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 6. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Ipu VI = 0 V 15 50 85 A 10 50 85 A 0 0 0 A pull-up current 2.0 V < VDD 3.6 V VDD = 2.0 V VDD < VI < 5 V I2C-bus pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [3] System oscillator enabled; PLL and IRC disabled. [4] IRC enabled; system oscillator disabled; system PLL disabled. [5] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [6] BOD disabled. [7] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the syscon block.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC1315/16/17/45/46/47 user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aag901 18 72 MHz 60 MHz 48 MHz 36 MHz 24 MHz 12 MHz 6 MHz 3 MHz 1 MHz IDD (mA) 14.4 10.8 7.2 3.6 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; USB_DP and USB_DM pulled LOW externally.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aag891 300 IDD (μA) 290 3.6 V 3.3 V 2.0 V 280 270 260 250 -40 -15 10 35 60 temperature (°C) 85 Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; USB_DP and USB_DM pulled LOW externally. Fig 13. Typical supply current versus temperature in Deep-sleep mode 002aag892 18 IDD (μA) 12 3.6 V 3.3 V 2.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aag893 0.8 IDD (μA) 0.6 3.6 V 3.3 V 2.0 V 0.4 0.2 0 -40 -15 10 35 60 temperature (°C) 85 Fig 15. Typical supply current versus temperature in Deep power-down mode Table 8.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 8. Power consumption for individual analog and digital blocks The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCTRL or PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aaf019 60 T = 85 °C 25 °C −40 °C IOL (mA) 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 17. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL 002aae991 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 18.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aae992 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 19. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aae988 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 20.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aae989 80 T = 85 °C 25 °C −40 °C Ipd (μA) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 21. Typical pull-down current Ipd versus input voltage VI LPC1315_16_17_45_46_47 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 September 2012 © NXP B.V. 2012. All rights reserved.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10. Dynamic characteristics 10.1 Flash/EEPROM memory Table 9. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min [1] Nendu endurance tret retention time ter erase time tprog programming time Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 22. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC1315_16_17_45_46_47 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 September 2012 © NXP B.V. 2012. All rights reserved.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.3 Internal oscillators Table 12. Dynamic characteristics: IRC Tamb = 40 C to +85 C; 2.7 V VDD 3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.4 I/O pins Table 14. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +85 C; 3.0 V VDD 3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 10.5 I2C-bus Table 15. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.6 SSP interface Table 16. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter Conditions Min Max Unit clock cycle time full-duplex mode [1] 40 - ns when only transmitting [1] 27.8 - ns in SPI mode; [2] 15 - ns [2] SSP master Tcy(clk) data set-up time tDS 2.4 V VDD 3.6 V 2.0 V VDD < 2.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tclk(H) tclk(L) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tDH tDS MISO CPHA = 1 DATA VALID CPHA = 0 DATA VALID 002aae829 Fig 25. SSP master timing in SPI mode LPC1315_16_17_45_46_47 Product data sheet All information provided in this document is subject to legal disclaimers. Rev.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tclk(H) tclk(L) tDS tDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tv(Q) MISO th(Q) DATA VALID DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 th(Q) CPHA = 0 DATA VALID 002aae830 Fig 26. SSP slave timing in SPI mode LPC1315_16_17_45_46_47 Product data sheet All information provided in this document is subject to legal disclaimers. Rev.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11. ADC electrical characteristics Table 17. ADC characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; 12-bit resolution.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP − VREFN 4096 002aad948 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12. Application information 12.1 Suggested USB interface solutions VDD USB_CONNECT LPC1345/46/47 soft-connect switch R1 1.5 kΩ USB_VBUS USB_DP RS = 33 Ω USB_DM USB-B connector RS = 33 Ω VSS 002aag564 Fig 28. USB interface on a self-powered device VDD LPC1345/46/47 R1 1.5 kΩ USB_VBUS USB-B connector USB_DP RS = 33 Ω USB_DM RS = 33 Ω VSS 002aag565 Fig 29. USB interface on a bus-powered device 12.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1xxx XTALIN Ci 100 pF Cg 002aae788 Fig 30. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 30), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 18.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12.5 Reset pad configuration VDD VDD VDD Rpu ESD 20 ns RC GLITCH FILTER reset PIN ESD VSS 002aaf274 Fig 33. Reset pad configuration 12.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 17: • The ADC input trace must be short and as close as possible to the LPC1315/16/17/45/46/47 chip.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 13. Package outline HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm A B D terminal 1 index area E A A1 c detail X e1 e 9 16 C C A B C v w b y y1 C L 8 17 e e2 Eh 33 1 terminal 1 index area 24 32 X 25 Dh 0 2.5 scale Dimensions Unit mm 5 mm A(1) A1 b max 1.00 0.05 0.35 nom 0.85 0.02 0.28 min 0.80 0.00 0.23 c D(1) Dh E(1) 0.2 7.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14. Soldering Footprint information for reflow soldering of HVQFN33 package OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR chamfer (4×) W = 0.30 CU SPD = 1.00 SP LaE = 7.95 CU PIE = 7.25 PA+OA LbE = 5.80 CU evia = 4.25 evia = 1.05 0.45 DM SPE = 1.00 SP GapE = 0.70 SP 4.55 SR SEhtot = 2.70 SP EHS = 4.85 CU OwEtot = 5.10 OA OIE = 8.20 OA e = 0.65 0.45 DM GapD = 0.70 SP evia = 2.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 38.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP64 package SOT314-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 13.300 13.300 10.300 10.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 10.500 10.500 13.550 13.550 sot314-2_fr Fig 39.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15. Abbreviations Table 20.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 16. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1315_16_17_45_46_47 v.3 20120920 Product data sheet - LPC1315_16_17_45_46_47 v.2 • • • LPC1315_16_17_45_46_47 v.2 Modifications: LPC1315_16_17_45_46_47 v.1 LPC1315_16_17_45_46_47 Product data sheet Reflow soldering drawing corrected for the HVQFN33 package. See Figure 37.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 19. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . .
LPC1315/16/17/45/46/47 NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 17.2 17.3 17.4 18 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .