D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D LPC15xx D R R A FT R R R D D D F FT FT A A Objective data sheet A Rev. 1.0 — 16 January 2014 D D FT FT A A R R D 32-bit ARM Cortex-M3 microcontroller; up to 256 kB flash and 36 kB SRAM; FS USB, CAN, RTC, SPI, USART, I2C D FT FT A A R R D D D R A FT 1. General description D R The LPC15xx operate at CPU frequencies of up to 72 MHz.
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D ROM API support: Boot loader with boot options from flash or external source via USART, C_CAN, or USB USB drivers ADC drivers SPI drivers USART drivers I2C drivers Power profiles and power mode configuration with low-power mode configur
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Analog peripherals: Two 12-bit ADC with up to 12 input channels per ADC and with multiple internal and external trigger inputs and sample rates of up to 2 Msamples/s. Each ADC supports two independent conversion sequences.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D Single power supply 2.4 V to 3.6 V. Temperature range -40 °C to +105 °C. Available as LQFP100, LQFP64, and LQFP48 packages. FT FT FT LPC15xx FT FT NXP Semiconductors D FT FT A A R R D D D R 3. Applications A FT D R A Motor control 4.
D D D D D R R R R R D R R D A FT R R 36 yes 3 1 2 1 4 12/12 1 76 LPC1549JBD64 256 4 36 yes 3 1 2 1 4 12/12 1 44 LPC1549JBD48 256 4 36 yes 3 1 2 1 4 9/7 1 30 FT FT A 4 A R LPC1549JBD100 256 D D R 1 2 1 4 12/12 1 76 yes 3 1 2 1 4 12/12 1 44 LPC1547JBD64 64 4 12 yes 3 1 2 1 4 12/12 1 44 LPC1547JBD48 64 4 12 yes 3 1 2 1 4 9/7 1 30 LPC1519JBD100 256 4 36 no 3 1 2 1 4 12/12 1 78 LPC1519JBD64 256 4 36
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 5.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 6.1 Pinning A FT FT A A R R D D D 6.
D D D D D R R R R R D R R R R FT FT A A R D R 25 XTALOUT 26 XTALIN 27 VDD A 28 PIO0_17/WAKEUP/ D 29 SWCLK/ PIO0_19/TCK FT 30 VBAT A 31 RTCXIN R 32 RTCXOUT D 22 PIO0_14/ADC1_7/ SCT1_OUT5 VSS 40 21 PIO0_13/ADC1_6 VSS 41 20 VSS 19 PIO0_12/DAC_OUT LPC1517JBD48 18 PIO0_11/ADC1_3 PIO0_25/ACMP0_I4 44 17 VSSA PIO0_26/ACMP0_I3/ SCT3_OUT3 45 16 VDDA PIO0_27/ACMP_I1 46 15 PIO0_10/ADC1_2 PIO0_28/ACMP1_I3 47 14 VREFP_DAC_VDDCMP PIO0_9/ADC1_1/TDI 12 VREFN 11 VREFP_ADC 10
D D D D D R R R R R D R R A 33 PIO1_4 D R 34 PIO1_5 FT 35 XTALOUT A 36 XTALIN R 37 VDD D D 38 PIO1_11 FT FT A 39 PIO0_17/WAKEUP F R R 40 SWCLK/ PIO0_19 A D D 41 VBAT R FT FT 42 RTCXIN D A A 43 RTCXOUT FT R R 44 SWDIO/ PIO0_20 R A D D 45 RESET/PIO0_21 D R FT FT A A R R D D D 46 PIO1_6 FT FT FT FT A A A A R R D D D 47 USB_DP FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller 48 USB_DM A A A A A NXP Semiconducto
D D D D D R R R R R D R R A 3,2 B D R 3,2 B FT ;7$/287 A ;7$/,1 R 9'' D D 3,2 B FT FT A 3,2 B :$.(83 F R R 6:&/.
D D D D D R R R R R D R R FT ADC0_7 — ADC0 input 7. O SCT0_OUT4 — SCTimer0/PWM output 4. IO PIO0_2 — General purpose port 0 input/output 2. FT D FT D R A I; PU A LQFP100 A A LQFP64 PIO0_1 — General purpose port 0 input/output 1. I; PU R LQFP48 SCT0_OUT3 — SCTimer0/PWM output 3. IO ADC0_6 — ADC0 input 6. 4 7 10 [2] 8 13 PIO0_5/ADC0_3 6 9 14 [2] 16 [2] 7 8 9 10 11 12 17 [2] 19 [2] I; PU I; PU I; PU I; PU I; PU I; PU O SCT1_OUT3 — SCTimer1/PWM output 3.
D D D D D R R R R R D R R PIO0_13 — General purpose port 0 input/output 13. R A FT FT A D D R A IO PIO0_14 — General purpose port 0 input/output 14. On the LQFP48 package, this pin is assigned to U0_RXD in ISP USART mode. 23 31 47 [2] I; PU A ADC1_7 — ADC1 input 7. O SCT1_OUT5 — SCTimer1/PWM output 5. IO PIO0_15 — General purpose port 0 input/output 15. On the LQFP48 package, this pin is assigned to U0_TXD in ISP USART mode.
D D D D D R R R R R D R R LQFP100 I; PU A ACMP0_I3 — Analog comparator 0 input 3. O SCT3_OUT3 — SCTimer3/PWM output 3. IO PIO0_27 — General purpose port 0 input/output 27. A ACMP_I1 — Analog comparator common input 1. IO PIO0_28 — General purpose port 0 input/output 28. A ACMP1_I3 — Analog comparator 1 input 3. IO PIO0_29 — General purpose port 0 input/output 29. A ACMP2_I3 — Analog comparator 2 input 3. O SCT2_OUT4 — SCTimer2/PWM output 4.
D D D D D R R R R R D R R D ADC1_10 — ADC1 input 10. IO PIO1_5 — General purpose port 1 input/output 5. A ADC1_11 — ADC1 input 11. IO PIO1_6 — General purpose port 1 input/output 6. A ACMP_I2 — Analog comparator common input 2. IO PIO1_7 — General purpose port 1 input/output 7. A ACMP3_I4 — Analog comparator 3 input 4. IO PIO1_8 — General purpose port 1 input/output 8. A ACMP3_I3 — Analog comparator 3 input 3. O SCT3_OUT4 — SCTimer3/PWM output 4.
D D D D D R R R R R D R R LQFP48 LQFP64 LQFP100 PIO1_27 — General purpose port 1 input/output 27. - 55 [5] I; PU IO PIO1_28 — General purpose port 1 input/output 28. 56 [5] I; PU IO PIO1_29 — General purpose port 1 input/output 29. 59 [5] I; PU IO PIO1_30 — General purpose port 1 input/output 30. D FT IO PIO2_1 — General purpose port 2 input/output 1. 72 I; PU IO PIO2_2 — General purpose port 2 input/output 2. I; PU IO PIO2_3 — General purpose port 2 input/output 3.
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R LQFP48 LQFP64 LQFP100 16 20 30 - Analog supply voltage. VDD and the analog reference voltages VREFP_ADC and VREFP_DAC_VDDCMP must not exceed the voltage level on VDDA. VDDAshould typically be the same voltages as VDD but should be isolated to minimize noise and error. VDDA should be tied to VDD if the ADC is not used. VDD 39, 27, 42 22, 52, 37, 57 4, 32, 70, 83, 57, 89 - 3.3 V supply voltage (2.4 V to 3.6 V).
D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R F FT FT [10] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. A A A R R D D D Special analog pin.
D D D D D R R R R R D R R D R D D R A I DAC shut-off external input. ACMP0_O O Analog comparator 0 output. ACMP1_O O Analog comparator 1 output. ACMP2_O O Analog comparator 2 output. ACMP3_O O Analog comparator 3 output. CLKOUT O Clock output. ROSC O Analog comparator ring oscillator output. ROSC_RESET I Analog comparator ring oscillator reset. USB_FTOGGLE O USB frame toggle.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The LPC15xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. F FT FT A A R R D D D 7.
D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D PIO0_13 PIO2_7 CAN0_TD PIO0_18 PIO0_31 PIO2_8 CAN0_RD PIO0_13 PIO0_11 PIO2_9 PIO0_16 PIO1_11 PIO2_4 F PIO0_14 A U0_RXD D R R D A FT FT LQFP100 R LQFP64 A LQFP48 FT Boot pin FT A A R R D D D Pin assignments for ISP modes FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller Table 6.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT D FT FT A A R R D The on-chip ROM contains the boot loader and the following Application Programming Interfaces (APIs): FT A A R R D D D 7.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 7.
D D D D D R R R R R D R R D A FT R 0xE000 0000 16 USART2 15 flash ctrl FMC 14 SCTIPU 13 RIT 12 reserved 11 GINT1 10 GINT0 9 PINT 8 MRT reserved 0x400F 0000 APB peripherals 1 0x4008 0000 APB peripherals 0 0x4000 0000 reserved 0x1C02 8000 SCTimer3/PWM 0x1C02 4000 SCTimer2/PWM SCTimer1/PWM SCTimer0/PWM reserved 7:1 0x1C01 C000 0 0x1C01 8000 31:30 reserved 29 SYSCON 28:23 reserved 0x1C01 4000 CRC USB reserved DMA GPIO reserved 22 QEI 0x1C00 C000 21 reserved 0x
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. F FT FT A A R R D D D 7.
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R FT FT A A R D D R A FT D R Digital input: Input glitch filter enabled/disabled on select pins A Analog input 9'' 9'' RSHQ GUDLQ HQDEOH VWURQJ SXOO XS (6' GDWD RXWSXW 3,1 VWURQJ SXOO GRZQ (6' 966 9'' ZHDN SXOO XS SXOO XS HQDEOH UHSHDWHU PRGH HQDEOH 352*5$00$%/( ',*,7$/ ),/7(5 ZHDN SXOO GRZQ SXOO GRZQ HQDEOH GDWD LQSXW SLQ FRQILJXUHG DV GLJLWDO LQSXW VHOHFW GDWD LQYHUWHU VHOHFW JOLWFK ILOWHU QV */,7&+ )
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D Device pins that are not connected to a specific peripheral function through the switch matrix are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. F FT FT A A R R D D D 7.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The GPIO pins can be used in several ways to set pins as inputs or outputs and use the inputs as combinations of level and edge sensitive interrupts.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The input mux allows to select from multiple external and internal sources for the SCT inputs, DMA trigger inputs, and the frequency measure block. The input mux is implemented as a register interface with one source selection register for each input.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A D FT FT A A R R D Remark: All USART functions are movable functions and are assigned to pins through the switch matrix. Do not connect USART functions to the open-drain pins PIO0_22 and PIO0_23. F FT FT A A R R D D D 7.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R F FT FT A A R R D D • Maximum data rates of 17 Mbit/s in master mode and slave mode for SPI functions connected to all digital pins except PIO0_22 and PIO0_23. A FT FT A A R R D D D 7.19.1 Features FT FT FT LPC15xx FT FT NXP Semiconductors D D • Data transmits of 1 to 16 bits supported directly.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D Controller Area Network (CAN) is the definition of a high performance communication protocol for serial data communication. The C_CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2.0B.
D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D digital peripheral A A A A R R D D D analog peripheral analog signal from/to pins FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller digital signal from/to pins A A A A A NXP Semiconductors digital signal internal D D R A analog signal internal FT SWITCH MATRIX THRESHOLD CROSSING INTERRUPTS A ANALOG IN R TRIG
D D D D D R R R R R D R R R A FT R F D FT FT A A R R D INPUT MUX A FT FT A A R R D D D D D R A FT analog signal internal D R FT FT A A R R D D D digital peripheral digital signal internal FT FT FT FT analog signal from/to pins A A A A R R D D D DMA analog peripheral FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller digital signal from/to pins A A A A A NXP Semiconductors D R A VOLTAGE REFERENCE SCT IPU INPUT MUX TEMP
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R FT FT A A R D D R A FT – Counters clocked by system clock or selected input. D R – Configurable as up counters or up-down counters. A – Configurable number of match and capture registers. Up to 16 match and capture registers total. – Upon match create the following events: stop, halt, limit counter or change counter direction; toggle outputs; create an interrupt; change the state.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT FT FT A A R R D D – Three outputs connected to external pins through the switch matrix as movable functions.
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D FT FT A A R R D D D R A FT D – Match register 0 can be used as an automatic limit. R A – In bi-directional mode, events can be enabled based on the count direction. – Match events can be held until another qualifying event occurs. • State control features: – A state is defined by events that can take place in the state while the counter is running. – A state changes into another state as result of an event.
D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D D R A D FT FT A A R R D • Four additional outputs which can be sampled at certain times and latched at others F FT FT A A R R D D • Four registers to indicate which specific input sources caused the abort input to the before being routed to SCT inputs. FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller SCTs.
D D D D D R R R R R D R R FT D R FT FT A A R D D R Input multiplexing among 12 pins and up to 4 internal sources. A flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger latency and can eliminate uncertainty and jitter in response to a trigger. 7.25 Digital-to-Analog Converter (DAC) The DAC supports a resolution of 12 bits. Conversions can be triggered by an external pin input or an internal timer.
D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT D D R • 32-stage voltage ladder internal reference for selectable voltages on each FT A A R R D input channel. A comparator; configurable on either positive or negative comparator input. FT input on each comparator. • Temperature sensor voltage selectable as either positive or negative input on each comparator.
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D A F FT FT A A measure the power supply voltage. This requires calibration by recording the ADC code of the internal voltage reference at different power supply levels yielding a different ADC code value for each supply voltage level.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The repetitive interrupt timer provides a free-running 48-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection.
D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D IRC system oscillator watchdog oscillator D D D n R A memories, peripheral clocks RTC oscillator 32 kHz SYSAHBCLKCTRLn (AHB clock enable) MAINCLKSELB (main clock select B) SYSTICK PERIPHERAL CLOCK DIVIDER IRC SYSTEM PLL system oscillator USART PERIPHERAL CLOCK DIVIDER SYSPLLCLKSEL (system PLL clock select) FRACTIONAL RATE GENERATOR ARM core
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The LPC15xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. F FT FT A A R R D D D 7.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT The IRC can be used as the clock that drives the system PLL and then the CPU. In addition, the IRC can be selected as input to various clock dividers and as the clock source for the USB PLL and the SCT PLL (see Figure 12). The nominal IRC frequency is 12 MHz. F FT A A R R D D D 7.36.
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D and bypassed following a chip reset. Software can enable the PLL later. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s.
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and can generate interrupts to cause the processor to resume execution.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D A F D FT Reset has four sources on the LPC15xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin.
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F D FT FT A A R R D There are three levels of Code Read Protection: D FT FT A A R R D D In addition, ISP entry the external pins can be disabled without enabling CRP. For details, see the LPC15xx user manual. D D R 1.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A D FT FT A A R R D Debug functions are integrated into the ARM Cortex-M3. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M3 is configured to support up to four breakpoints and two watch points. F FT FT A A R R D D D 7.
D D D D D R R R R R D R R FT - 100 mA 65 +150 C - 150 C - 1.5 W 5 kV FT FT D D R FT D R A [11] A [1] A A [10] human body model; all pins R R Tj < 125 C electrostatic discharge voltage The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge.
D D D D D R R R R R D R R FT 55 C/W 2.5 m/s 50 C/W 96 C/W 1 m/s 76 C/W 2.5 m/s 67 C/W R FT FT A A R D D R A FT D R 0 m/s A 8-layer (4.5 in 3 in) 0 m/s jc thermal resistance junction-to-case 13 C/W jb thermal resistance junction-to-board 16 C/W 0 m/s 51 C/W 1 m/s 45 C/W 2.5 m/s 41 C/W 0 m/s 75 C/W 1 m/s 60 C/W 2.5 m/s 54 C/W LQFP64 ja thermal resistance junction-to-ambient JEDEC (4.5 in 4 in) 8-layer (4.
D D D D D R R R R R D R R FT D R A FT Typ[1] Max Unit 2.4 3.3 VDDA V 2.4 3.3 3.6 V on pin VREFP_DAC_VDDCMP 2.4 - VDDA V on pin VREFP_ADC 2.7 - VDDA V 2.4 3.3 3.6 V - 4.3 - mA - 2.7 - mA - 19.3 - mA - 18 - mA - 2.1 - mA - 1.6 - mA - 8.0 - mA - 7.8 - mA 300 380 A - 620 A 3.8 8 A - - 163 A - 1.1 1.3 A - - 11 - 560 - A R A while(1){} system clock = 12 MHz; default mode; VDD = 3.
D D D D D R R R R R D R R FT D - nA 1 - A FT FT A A R R 0 Unit D Max D Typ[1] D D R A R A LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage VDD 2.4 V; 5 V tolerant pins except PIO0_12 0 - 5 V VDD 2.
D D D D D R R R R R D R R FT A 3.6 V output active 0 - VDD V V A R R - D A 0 D VDD = 0 V Unit F FT FT 5.0 FT V FT D D [17] R A A - VDD 2.4 V D R R 0 input voltage R A D D Max [15] D R FT FT A A R R D D D Typ[1] Conditions FT FT FT FT VI Min Parameter A A A A R R D D D Table 10. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified.
D D D D D R R R R R D R R FT D [21] 5.0 - - mA IOLS LOW-level short-circuit output current drive LOW; pad connected to ground - - 125 mA IOHS HIGH-level short-circuit drive HIGH; pad connected to output current ground - - 125 mA A A R R VOL = 0.3 V D LOW-level output current D - Unit FT FT mA D D R A D R crystal input voltage on pin XTALIN 0.5 1.8 1.95 V crystal output voltage on pin XTALOUT 0.5 1.8 1.
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D FT FT FT FT $ R SLQ 3,2 BQ A A A A R R D D D 9'' FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller ,2/ ,SG A A A A A NXP Semiconductors A FT D R A ,2+ ,SX SLQ 3,2 BQ $ DDD Fig 15.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions: F FT FT A A R R D D D 10.
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D D FT FT A A R R D D D R A 60 MHz FT D R 12 A 48 MHz 36 MHz 8 24 MHz 4 12 MHz 6 MHz 1 MHz 0 -40 -10 20 50 80 temperature (°C) 110 Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D D FT FT A A R R D D D R 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V A FT D R A 340 320 300 280 -40 -10 20 50 80 temperature (°C) 110 Conditions: BOD disabled; all oscillators and analog blocks disabled use API power_mode_configure() with mode parameter set to DEEP_SLEEP and peripheral parameter set to 0xFF. Fig 19.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R F FT FT D FT FT A A R R D IDD (μA) A A A R R D D D aaa-011236 4 A A A A A NXP Semiconductors D D R A 3 FT D 3.3 V 3.6 V R A 2 1 2.4 V 0 -40 -10 20 50 80 temperature (°C) 110 VBAT = 0 V. Fig 21.
D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 001aac984 A FT FT A A R R D D D 10.2 CoreMark data FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller X A A A A A NXP Semiconductors D D X (X) R A FT D X R A X X X X X X X X X X (X) Conditions: VDD = 3.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers.
D D D D D R R R R R D R R D A FT R - 0.02 0.15 - USART1 - 0.02 0.16 - USART2 - 0.02 0.15 - C_CAN - 0.50 3.00 USB - 0.10 0.50 R USART0 FT FT A A R 72 MHz D D R A FT D R A Comparator ACMP0/1/2/3 - 0.01 0.03 - ADC0 - 0.05 0.33 - ADC1 - 0.04 0.33 - temperature sensor - 0.03 0.03 internal voltage reference/band gap 0.03 0.04 DAC - 0.02 0.09 DMA - 0.36 1.5 CRC - 0.01 0.08 - 10.4 Electrical pin characteristics aaa-011257 3.
D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D D FT FT A A R R D R -40 °C C 25 °C C 90 °C C 105 °C C A FT D R A 30 D D 40 20 10 0 0 0.1 0.2 0.3 0.4 VOL (V) 0.5 Conditions: VDD = 3.3 V; on pins PIO0_22 and PIO0_23. Fig 26.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D aaa-011276 D FT FT A A R R D 3.3 IOH (mA) A A A A A NXP Semiconductors R A FT D 3.1 D D -40 °C C 25 °C C 90 °C C 105 °C C R A 2.9 2.7 0 3 6 9 VOH (V) 12 Conditions: VDD = 3.3 V; standard port pins. Fig 28.
D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D aaa-011278 D FT FT A A R R D Ipu (μA) FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller 80 A A A A A NXP Semiconductors D D R -40 °C 25 °C 25 90 °C 90 105105 °C A 60 FT D R A 40 20 0 0 1 2 3 4 VI (V) 5 Conditions: VDD = 3.3 V; standard port pins. Fig 30.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 11.1 Flash/EEPROM memory A FT FT A A R R D D D 11. Dynamic characteristics FT FT FT LPC15xx FT FT NXP Semiconductors D D R A FT D R Table 12. Flash characteristics Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A D R A F FT FT A A R R D D Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. FT FT FT A A R R D D D [2] A A A A A NXP Semiconductors D FT FT A A R R D D D R A FT W&+&; W&/&+ R A W&/&; D W&+&/ 7F\ FON DDD Fig 31.
D D D D D R R R R R D R R R F D R FT FT A kHz A 503 R - D Typ[1] Max Unit FT Min - A FT A A R R R [2] D D D Conditions D FT FT FT A A A internal oscillator frequency R R R fosc(int) D D D Parameter FT FT FT FT Symbol A A A A R R D D D Dynamic characteristics: Watchdog oscillator FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller Table 16. A A A A A NXP Semiconductors D D R Typical ratings are not guaranteed.
D D D D D R R R R R D R R D R A FT FT FT A A R R R R Unit 250 - ns Fast-mode 100 - ns Fast-mode Plus; on pins PIO0_22 and PIO0_23 50 - ns R FT FT A A R D D R A R A [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D A A R R D The maximum data bit rate is 17 Mbit/s in master mode and in slave mode. A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller 11.6 SPI interfaces FT FT FT LPC15xx FT FT NXP Semiconductors FT FT Remark: SPI functions can be assigned to all digital pins.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 7F\ FON FT FT FT LPC15xx FT FT NXP Semiconductors D FT FT A A R R D 6&. &32/ D D R A FT D 6&.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R F D FT FT A A R R D The maximum USART bit rate is 15 Mbit/s in synchronous mode master mode and 18 Mbit/s in synchronous slave mode. A FT FT A A R R D D D 11.7 USART interface FT FT FT LPC15xx FT FT NXP Semiconductors D D Remark: USART functions can be assigned to all digital pins.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D Table 21. QEI dynamic characteristics Simulated parameters sampled at the 50 % level of the falling or rising edge. Signal properties allow the signal to be captured by the QEI. Additional digital filtering is required. F FT FT A A R R D D D 11.
D D D D D R R R R R D R R FT R D FT FT A A R R D 2.55 - V de-assertion - 2.69 - V D - FT assertion A Unit R Max D Typ D 2.83 - V - 2.96 - V assertion - 2.34 - V de-assertion - 2.49 - V assertion - 2.64 - V de-assertion - 2.79 - V reset level 3 Objective data sheet Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the LPC15xx user manual.
D D D D D R R R R R D R R FT 0.1 pF VDDA 2.7 V 50 MHz VDDA 2.4 V 25 MHz - 2 Msamples/s FT FT A A R D D R A FT Msamples/s - +/- 2 LSB integral non-linearity [3] - +/- 2 LSB offset error [4] - +/- 3 LSB full-scale error voltage [5] - fs = 2 Msamples/s [6][7] A 1 EL(adj) input resistance R - differential linearity error 2 Msamples/s D VDDA 2.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT gain error EG FT A A R R D D D D FT FT A A R R D offset error EO FT FT FT LPC15xx FT FT NXP Semiconductors D D 4095 R A FT D 4094 R A 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D A A R R D Unit 500 kSamples/s FT FT Max D D [1] A FT FT A A R R D D D Typ FT FT FT FT Min A A A A R R D D D Table 25. DAC static and dynamic characteristics VDDA = 2.4 V to 3.6 V; Tamb = 40 C to +105 C unless otherwise specified; CL = 100 pF; RL = 10 k..
D D D D D R R R R R D R R R A F A FT D A FT s 125 R - R - mV D 905 to 99% of VO D D power-up settling time mV FT ts(pu) FT 925 A - D A 875 Unit R Max Tamb = 25 C R FT R Typ D Min FT VO [1] D A D A Tamb = 40 C to +105 C R output voltage D Conditions R FT FT A A R R D D D Parameter FT FT FT FT Symbol A A A A R R D D D Internal voltage reference static and dynamic characteristics FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M
D D D D D R R R R R D R R D R D - - 5 C - 81 110 s A FT FT C D D R A FT [3] Internal voltage reference must be powered before the temperature sensor can be turned on. [4] Settling time applies to switching between comparator and ADC channels. Fit parameter Range Min Typ Max Unit Tamb = 40 C to +105 C [1] LLS slope LLS intercept at 0 C - -2.29 - mV/C Tamb = 40 C to +105 C [1] - 577.
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D D D D R FT D - D 48 Unit FT - A VP > VM A R Max R VDDA V DVO output voltage variation 0 - VDD V Voffset offset voltage VIC = 0.1 V - +/- 3 - mV VIC = 1.5 V - +/- 3 - mV VIC = 2.9 V - +/- 6 - mV - 4.5 6 s Dynamic characteristics tstartup start-up time nominal process tPD propagation delay HIGH to LOW; VDDA = 3.
D D D D D R R R R R D R R FT 20 D D R A D R A LPC15xx Objective data sheet Parameter EV(O) output voltage error Min Typ Max[1] Unit - 0 3 mV decimal code = 08 -1.5 0 +1.5 % decimal code = 16 -1.5 0 +1.5 % decimal code = 24 -1.5 0 +1.5 % decimal code = 30 -1.5 0 +1.5 % decimal code = 31 -1.5 0 +1.5 % Conditions decimal code = 00 [2] [1] Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V.
D D D D D R R R R R A A A A A D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 13.1 Suggested USB interface solutions A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller 13. Application information FT FT FT LPC15xx FT FT NXP Semiconductors D D The USB device can be connected to the USB as self-powered device (see Figure 42) or bus-powered device (see Figure 43).
D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT REGULATOR FT A A R R D LPC1xxx FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller VDD A A A A A NXP Semiconductors D D R A FT USB_CONNECT D R A USB R1 1.5 kΩ VBUS RS = 33 Ω USB_DP RS = 33 Ω USB_DM USB-B connector VSS aaa-010821 Fig 43.
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D LPC1xxx D D R A FT XTALIN D R A Ci 100 pF Cg 002aae788 Fig 44.
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R < 300 18 pF, 18 pF 20 pF < 200 39 pF, 39 pF 30 pF < 100 57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF 20 pF < 60 39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF R FT FT A A R D D R A FT D R A Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Select Cx1 and Cx2 based on the external 32 kHz crystal used in the application circuitry.The pad capacitance CP of the RTCXIN and RTCXOUT pad is 3 pF.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 14. Package outline FT FT FT LPC15xx FT FT NXP Semiconductors D FT A A R R D LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT A A R R D LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.
D D D D D R R R R R A A A A A FT FT FT LPC15xx FT FT D R R FT FT FT FT 32-bit ARM Cortex-M3 microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT A A R R D LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 15. Soldering FT FT FT LPC15xx FT FT NXP Semiconductors D FT FT A A R R D Footprint information for reflow soldering of LQFP48 package D D SOT313-2 R A FT D R A Hx Gx P2 Hy (0.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D Footprint information for reflow soldering of LQFP64 package FT FT FT LPC15xx FT FT NXP Semiconductors SOT314-2 D FT FT A A R R D D D R A FT Hx D R Gx A P2 Hy (0.
D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R A SOT407-1 F FT FT A A R R D D D Footprint information for reflow soldering of LQFP100 package FT FT FT LPC15xx FT FT NXP Semiconductors D FT FT A A R R D D D R A FT Hx D R Gx A P2 Hy (0.
D D D D D R R R R R D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R F D Objective data sheet - LPC15xx v.0.4 D LPC15xx v.1 FT Supersedes A Change notice R Data sheet status D Release date FT Document ID FT A A R R D Revision history A FT FT A A R R D D D Table 34. FT FT FT FT FT LPC15xx 32-bit ARM Cortex-M3 microcontroller 16.
D D D D D R R R R R FT FT FT FT FT LPC15xx D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M3 microcontroller D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 17.1 Data sheet status A FT FT A A R R D D D 17. Legal information A A A A A NXP Semiconductors D D R Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development.
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R A F D FT FT A A R R D D D R A FT D 17.4 Trademarks For sales office addresses, please send an email to: salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1.0 — 16 January 2014 © NXP B.V. 2014. All rights reserved. 96 of 98 A I2C-bus — logo is a trademark of NXP B.V.
D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R F D FT FT A A R R D D D 97 of 98 A © NXP B.V. 2014. All rights reserved. R Rev. 1.0 — 16 January 2014 D All information provided in this document is subject to legal disclaimers. FT 7.22.4.1 7.22.5 7.22.5.1 7.23 7.23.1 7.24 7.24.1 7.25 7.25.1 7.26 7.26.1 7.27 7.28 7.29 7.29.1 7.30 7.30.1 7.31 7.31.1 7.32 7.33 7.33.1 7.34 7.35 7.36 7.36.1 7.36.2 7.36.3 7.36.4 7.37 7.38 7.39 7.40 7.40.1 7.40.2 7.40.3 7.40.4 7.
D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT D R A 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 49 49 50 52 57 61 62 63 67 67 67 68 69 69 71 73 74 74 75 83 83 84 A A A A R R D D D 13.3 Emulation and debugging . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . .