Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TFBGA 180 (12x12) 32-Bit 120 MHz I/O number 141

1. General description

The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications

requiring a high level of integration and low power dissipation.

The ARM Cortex-M3 is a next generation core that offers better performance than the

ARM7 at the same clock rate and other system enhancements such as modernized

debug features and a higher level of support block integration. The ARM Cortex-M3 CPU

incorporates a 3-stage pipeline and has a Harvard architecture with separate local

instruction and data buses, as well as a third bus with slightly lower performance for

peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that

supports speculative branches.

The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal

performance when executing code from flash. The LPC178x/7x operates at up to

120 MHz CPU frequency.

The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program

memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,

External Memory Controller (EMC), LCD (LPC178x only), Ethernet, USB

Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,

three I

C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers,

two general purpose PWMs with six outputs each and one motor control PWM, an

ultra-low power RTC with separate battery supply and event recorder, a windowed

watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more.

The analog peripherals include one eight-channel 12-bit ADC and a 10-bit DAC.

The pinout of LPC178x/7x is intended to allow pin function compatibility with the LPC24xx

and LPC23xx.

For additional documentation, see Section 18 “

References”.

2. Features and benefits

 Functional replacement for the LPC23xx and LPC24xx family devices.

 System:

 ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory

Protection Unit (MPU) supporting eight regions is included.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and

96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC

Rev. 5 — 9 September 2014 Product data sheet

Summary of content (122 pages)

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LPC178x/7x 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC Rev. 5 — 9 September 2014 Product data sheet 1. General description The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller      LPC178X_7X Product data sheet  Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, USB, Ethernet, and the General Purpose DMA controller. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time.  Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller  Three enhanced I2C-bus interfaces, one with a true open-drain output supporting the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.  I2S-bus (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.  CAN controller with two channels.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller       The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes.  Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, PORT0/2 pin interrupt, and NMI).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1788 LPC1788FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC1788FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 ´ 15 ´ 0.7 mm SOT950-1 LPC1788FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 2. LPC178x/7x ordering options All parts include two CAN channels, three SSP interfaces, three I2C interfaces, one I2S interface, DAC, and an 8-channel 12-bit ADC.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 5.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 6. Pinning information 157 208 6.1 Pinning 1 156 LPC178x/7xFBD208 105 53 104 52 Fig 2. 002aaf518 Pin configuration (LQFP208) ball A1 index area 2 1 4 3 6 5 8 7 9 10 12 14 16 11 13 15 17 A B C D E F G H J LPC178x/7x K L M N P R T U 002aaf529 Transparent top view Fig 3. LPC178X_7X Product data sheet Pin configuration (TFBGA208) All information provided in this document is subject to legal disclaimers. Rev.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller ball A1 index area LPC178x/7x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P 002aaf519 Transparent top view 109 Pin configuration (TFBGA180) 144 Fig 4. 1 108 LPC178x/7x Fig 5. 72 73 37 36 002aaf520 Pin configuration (LQFP144) 6.2 Pin description I/O pins on the LPC178x/7x are 5 V tolerant and have input hysteresis unless otherwise indicated in the table below.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Type[2] Reset state[1] Description Pin LQFP144 Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P0[6] P0[7] 166 C12 164 D13 162 C13 LPC178X_7X Product data sheet 115 D11 B12 113 112 [3] [3] [4] Type[2] B11 Reset state[1] Pin LQFP144 P0[5] Description Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P0[9] P0[10] P0[11] P0[12] 160 A15 158 C14 98 T15 100 R14 41 LPC178X_7X Product data sheet R1 111 A13 L10 P12 J4 109 69 70 29 [4] [4] [3] [3] [5] Type[2] C12 Reset state[1] Pin LQFP144 P0[8] Description Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P0[20] P0[21] P0[22] P0[23] P0[24] 120 M17 K14 118 116 18 16 LPC178X_7X Product data sheet M16 K11 N17 H1 G2 L14 F5 E1 83 82 80 13 11 [3] [3] [6] [5] [5] Type[2] Reset state[1] Description Pin LQFP144 Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P1[17] P1[18] P1[19] P1[20] 180 D10 178 A9 66 68 70 LPC178X_7X Product data sheet P7 U6 U7 125 C9 L5 P5 K6 123 46 47 49 [3] [3] [3] [3] [3] Type[2] B8 Reset state[1] Pin LQFP144 P1[16] Description Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). P1[30] Pin LQFP144 U14 N10 64 42 P2 K3 30 [3] [5] Type[2] Ball TFBGA180 92 Reset state[1] Ball TFBGA208 P1[29] Description Pin LQFP208 Symbol I; PU I; PU I/O P1[29] — General purpose digital input/output pin.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P2[2] P2[3] P2[4] 152 E14 150 D15 144 E16 142 D17 LPC178X_7X Product data sheet 106 E11 E13 E14 105 100 99 [3] [3] [3] [3] Type[2] C14 Reset state[1] Pin LQFP144 P2[1] Description Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P2[6] P2[7] P2[8] 140 F16 138 E17 136 G16 134 H15 LPC178X_7X Product data sheet 97 F13 G11 96 95 G14 93 [3] [3] [3] [3] Type[2] F12 Reset state[1] Pin LQFP144 P2[5] Description Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P2[10] 132 H16 110 N15 92 M13 76 [3] [10] Type[2] H11 Reset state[1] Pin LQFP144 P2[9] Description Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). I; PU I; PU I/O P2[9] — General purpose digital input/output pin. O USB_CONNECT1 — USB1 SoftConnect control.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P2[13] P2[14] P2[15] P2[16] P2[17] P2[18] P2[19] P2[20] P2[21] P2[22] 102 T16 91 99 87 95 59 67 73 81 85 LPC178X_7X Product data sheet R12 P13 R11 R13 U3 R7 T8 U11 U12 M11 71 - - P9 P11 P3 N5 P6 N8 - - - - [10] [3] [3] [3] - [3] - [6] - [6] - [3] - [3] - [3] Type[2] Reset state[1] Description Pin LQFP144 Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P3[18] P3[19] P3[20] P3[21] P3[22] P3[23] P3[24] 143 F15 151 C15 161 B14 167 A13 175 C10 195 C6 65 58 LPC178X_7X Product data sheet T6 R5 - - - - - - M4 N3 - - - - - 45 40 [3] [3] [3] [3] [3] [3] [3] [3] Type[2] - Reset state[1] Pin LQFP144 P3[17] Description Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Ball TFBGA180 [3] I; PU I/O P4[19] — General purpose digital input/output pin. I/O EMC_A[19] — External memory address line 19. - [3] I; PU I/O P4[20] — General purpose digital input/output pin. I/O EMC_A[20] — External memory address line 20.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P4[30] P4[31] 176 B10 187 B7 193 A4 122 C7 E7 130 134 [3] [3] [3] Type[2] B9 Reset state[1] Pin LQFP144 P4[29] Description Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller P5[4] 206 C3 Pin LQFP144 G10 98 C4 143 [11] [3] Type[2] 141 G14 Description Reset state[1] P5[3] Ball TFBGA180 Pin LQFP208 Symbol Ball TFBGA208 Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). I I/O I; PU P5[3] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC pins). Pin LQFP144 Reset state[1] Type[2] Ball TFBGA208 VBAT 38 M3 VDD(REG)(3V3) Description Ball TFBGA180 Pin LQFP208 Symbol K1 27 - I RTC power supply: 3.0 V on this pin supplies power to the RTC. 26, H4, G1, 86, P11, N9, 174 D11 E9 18, 60, 121 - S 3.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [1] PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. [2] I = Input; O = Output; OL = Output driving LOW; G = Ground; S = Supply. [3] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The LPC178x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 7.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 7.7 Memory map Table 6.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.8 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.8.1 Features • • • • • • Controls system exceptions and peripheral interrupts. On the LPC178x/7x, the NVIC supports 40 vectored interrupts. 32 programmable interrupt priority levels, with hardware priority level masking.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 7.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The LPC178x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. See Table 6 for EMC memory access. 7.10.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.11.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation. – 16-bit write: 2-cycle operation (8-bit x 2-cycle). – 32-bit write: 4-cycle operation (8-bit x 4-cycle). 7.13 LCD controller Remark: The LCD controller is available on parts LPC1788/87/86/85. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.14 Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.15 USB interface Remark: The USB Device/Host/OTG controller is available on parts LPC1788/87/86/85 and LPC1778/77/76. The USB Device-only controller is available on parts LPC1774.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Two downstream ports. • Supports per-port power switching. 7.15.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • • • • All GPIO registers are byte and half-word addressable. Entire port value can be written in one instruction. Support for Cortex-M3 bit banding. Support for use with the GPDMA controller.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.19.1 Features • • • • • • • 10-bit DAC. Resistor string architecture. Buffered output. Power-down mode. Selectable output drive. Dedicated conversion timer. DMA support. 7.20 UARTs Remark: USART4 is not available on part LPC1774FBD144. The LPC178x/7x contain five UARTs.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.21.1 Features • Maximum SSP speed of 33 Mbit/s (master) or 10 Mbit/s (slave). • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.23 I2S-bus serial I/O controllers The LPC178x/7x contain one I2S-bus interface. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.25 General purpose 32-bit timers/external event counters The LPC178x/7x include four 32-bit timer/counters.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2n (see Table 8). Table 8. PWM speed at operating frequency 120 MHz PWM resolution PWM speed 6 bit 1.875 MHz 8 bit 0.468 MHz 10 bit 0.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.30 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.30.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller • • • • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. Periodic interrupts can be generated from increments of any field of the time registers. Backup registers (20 bytes) powered by VBAT. RTC power supply is isolated from the rest of the chip. 7.32 Event monitor/recorder The event monitor/recorder allows recording of tampering events in sealed product enclosures.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC178x/7x IRC oscillator MAIN PLL0 main oscillator (osc_clk) pll_clk sysclk CLKSRCSEL (system clock select) ALT PLL1 alt_pll_clk sysclk pll_clk CCLKSEL (CPU clock select) CPU CLOCK DIVIDER cclk PERIPHERAL CLOCK DIVIDER pclk EMC CLOCK DIVIDER emc_clk USB CLOCK DIVIDER usb_clk sysclk pll_clk alt_pll_clk USBCLKSEL (USB clock select) 002aaf531 Fig 7. 7.33.1.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.33.1.3 RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe. 7.33.1.4 Watchdog oscillator The Watchdog Timer has a dedicated watchdog oscillator that provides a 500 kHz clock to the Watchdog Timer. The watchdog oscillator is always running if the Watchdog Timer is enabled.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The alternate PLL accepts an input clock frequency from the main oscillator in the range of 10 MHz to 25 MHz only. When used as the USB clock, the input frequency is multiplied up to a multiple of 48 MHz (192 MHz or 288 MHz as described above). 7.33.3 Wake-up timer The LPC178x/7x begin operation at power-up and when awakened from Power-down mode by using the 12 MHz IRC oscillator as the clock source.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this, four IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 7.34 System control 7.34.1 Reset Reset has four sources on the LPC178x/7x: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.33.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.34.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. 7.34.5 AHB multilayer matrix The LPC178x/7x use an AHB multilayer matrix.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) external rail 2.4 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.6 V VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT 0.5 +4.6 V Vi(VREFP) input voltage on pin VREFP 0.5 +4.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation Table 10. Thermal characteristics VDD = 3.0 V to 3.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10. Static characteristics Table 13. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Min Typ[1] Max Unit 2.4 3.3 3.6 V 2.4 3.3 3.6 V [3] 2.7 3.3 3.6 V input voltage on pin VBAT [4] 2.1 3.0 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.7 3.3 VDDA V IDD(REG)(3V3) regulator supply current active mode; code (3.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 13. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 13. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Min Typ[1] Max Unit (D+)  (D) [20] 0.2 - - V includes VDI range [20] 0.8 - 2.5 V [20] 0.8 - 2.0 V RL of 1.5 k to 3.6 V [20] - - 0.18 V RL of 15 k to GND [20] 2.8 - 3.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.1 Power consumption 002aah051 1.5 IDD(REG)(3V3) (mA) VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.4 V 1.1 0.7 0.3 -40 -15 10 35 60 85 temperature (°C) Conditions: BOD disabled. Fig 9. Deep-sleep mode: Typical regulator supply current IDD(REG)(3V3) versus temperature 002aah052 900 IDD(REG)(3V3) (μA) 600 300 0 -40 VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.4 V -15 10 35 60 85 temperature (°C) Conditions: BOD disabled. Fig 10.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aah074 2.0 IBAT (μA) 1.6 1.2 0.8 0.4 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VDD(REG)(3V3) = VDDA = VDD(3V3) = 0; VBAT = 3.0 V. Fig 11. Part powered off: Typical battery supply current (IBAT) versus temperature LPC178X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 September 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock was set to PCLK = CCLK/4 with CCLK = 12 MHz, 48 MHz, and 120 MHz.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 14. Power consumption for individual analog and digital blocks …continued Tamb = 25 C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4. Peripheral Conditions Typical supply current in mA 12 MHz[1] 48 MHz[1] 120 MHz[2] LPC178X_7X Product data sheet EMC - 0.82 3.17 7.63 RTC - 0.01 0.01 0.05 USB + PLL1 - 0.62 0.97 1.67 Ethernet PCENET bit set 0.54 to 1 in the PCONP register 2.08 5.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 10.3 Electrical pin characteristics 002aaf112 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2.0 0 8 16 24 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aaf111 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 13.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 002aaf108 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 14. Typical pull-up current Ipu versus input voltage VI 002aaf109 90 Ipd (μA) 70 T = 85 °C 25 °C −40 °C 50 30 10 −10 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 15.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11. Dynamic characteristics 11.1 Flash memory Table 15. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min [1] Typ Max Unit Nendu endurance - 10000 100000 - cycles tret retention time powered 10 - - years unpowered 20 - - years 95 100 105 ms 0.95 1 1.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.2 External memory interface Table 17. Dynamic characteristics: Static external memory interface CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter[1] Read cycle Conditions[1] Min Typ Max Unit 2.7 3.5 4.7 ns parameters[2] tCSLAV CS LOW to address valid time RD1 tCSLOEL CS LOW to OE LOW time RD2 [3] 2.7 + Tcy(clk)  WAITOEN 3.4 + Tcy(clk)  WAITOEN 4.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 17. Dynamic characteristics: Static external memory interface …continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter[1] Conditions[1] Min Typ Max Unit 2.7 3.4 4.7 ns tdeact deactivation time WR8; PB = 0; PB = 1 [3] tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [3] 2.8 + Tcy(clk)  (1 + WAITWEN) 3.7 + Tcy(clk)  (1 + WAITWEN) 5.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller EMC_Ax RD1 WR1 EMC_CSx WR8 RD2 RD4 EMC_OE RD3 WR4 RD7 EMC_BLSx WR8 RD7 WR3 WR5 WR7 EMC_WE RD5 RD5 RD5 RD6 RD5 WR2 WR6 EMC_Dx EOR EOW 002aag215 Fig 17. External static memory read/write access (PB =1) EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE RD5 RD5 RD5 RD5 EMC_Dx 002aag216 Fig 18.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit Common to read and write cycles clock cycle time [1] 12.5 - - ns td(SV) chip select valid delay time [2] (CLKDLY + 1)  0.25 + 4.1 (CLKDLY + 1)  0.25 + 5.7 (CLKDLY + 1)  0.25 + 8.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 19. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit 12.5 - - ns Common to read and write cycles [1] Tcy(clk) clock cycle time td(SV) chip select valid delay time (CMDDLY + 1)  0.25 + 4.6 (CMDDLY + 1)  0.25 + 6.4 (CMDDLY + 1)  0.25 + 9.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) EMC_CLKn delay = 0 td(xV) EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn th(x) td(QV) th(Q) EMC_D[31:0] write tsu(D) th(D) EMC_D[31:0] read 002aah129 Fig 19. Dynamic external memory interface signal timing Table 20. Dynamic characteristics: Dynamic external memory interface programmable clock delays CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V.Values guaranteed by design.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.3 External clock Table 21. Dynamic characteristic: external clock (see Figure 36) Tamb = 40 C to +85 C; VDD(3V3) over specified ranges. Symbol Parameter Min Typ Max Unit fosc oscillator frequency 1 12 25 MHz Tcy(clk) clock cycle time 40 83.3 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.6 SSP interface Table 24. Dynamic characteristics: SSP pins in SPI mode CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions clock cycle time full-duplex mode Min Max Unit 30 - ns 30 - ns SSP master Tcy(clk) [1] when only transmitting tDS data set-up time in SPI mode [2] 14.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO DATA VALID tv(Q) th(Q) DATA VALID MOSI DATA VALID tDH tDS DATA VALID MISO CPHA = 1 tDH CPHA = 0 DATA VALID 002aae829 Fig 21.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 11.7 I2C-bus Table 25. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz [4][5][6][7] fall time tf Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.7 - s Fast-mode 1.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S 002aaf425 Fig 23. I2C-bus pins clock timing 11.8 I2S-bus interface Table 26. Dynamic characteristics: I2S-bus interface pins CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) tf tr I2S_TX_SCK tWH tWL I2S_TX_SDA tv(Q) I2S_TX_WS 002aag202 tv(Q) Fig 24. I2S-bus timing (transmit) Tcy(clk) tf tr I2S_RX_SCK tWH tWL I2S_RX_SDA tsu(D) th(D) I2S_RX_WS tsu(D) 002aag203 tsu(D) Fig 25. I2S-bus timing (receive) 11.9 LCD Remark: The LCD controller is available on parts LPC1788/87/86/85. Table 27. Dynamic characteristics: LCD CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Tcy(clk) LCD_DCLK td(QV) th(Q) LCD_VD[n] 002aah325 The LCD panel clock is shown with the default polarity. The clock can be inverted via the IPC bit in the LCD_POL register. Typically, the LCD panel uses the falling edge of the LCD_DCLK to sample the data. Fig 26. LCD timing 11.10 SD/MMC Remark: The SD/MMC card interface is available on parts LPC1788/87/86 and parts LPC1778/77/76. Table 28.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 12. ADC electrical characteristics Table 29. 12-bit ADC characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller [6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 28. [7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 28.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP - VSS 4096 002aaf436 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC178x/7x C3 Rcmp 90 Ω - 300 Ω 1.6 pF ADC COMPARATOR BLOCK Rsw 500 Ω - 2 kΩ C1 110 fF AD0[n] C2 80 fF Cia Rvsi VSS VEXT 002aag613 The values of resistor components Rcmp and Rsw vary with temperature and input voltage and are process-dependent. Fig 29. ADC interface to pins ADC0_IN[n] Table 30. ADC interface components Component Range Description Rcmp 90  to 300  Switch-on resistance for the comparator input switch.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 14. Application information 14.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1788/87/86/85 and LPC1778/77/76 and as device-only controller on parts LPC1774. VDD(3V3) USB_UP_LED USB_CONNECT LPC17xx SoftConnect switch R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSS 002aad939 Fig 30.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD R1 R2 R3 R4 RSTOUT RESET_N VBUS ADR/PSW ID OE_N/INT_N VDD SPEED SUSPEND R4 R5 ISP1302 DP 33 Ω DM 33 Ω R6 USB_SCL1 SCL USB_SDA1 SDA USB_INT1 Mini-AB connector VSSIO, VSSCORE INT_N USB_D+1 USB_D-1 VDD USB_UP_LED1 LPC178x/7x R7 5V VDD IN USB_PPWR2 ENA LM3526-L OUTA FLAGA USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω D+ USB_D-2 33 Ω D15 kΩ 15 kΩ USB-A connector VSSIO, VSSCORE VDD USB_UP_LED2 R8 0
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD RSTOUT RESET_N OE_N/INT_N USB_TX_E1 USB_TX_DP1 DAT_VP USB_TX_DM1 SE0_VM RCV USB_RCV1 USB_RX_DP1 USB_RX_DM1 VP VBUS VM ID VDD ISP1302 LPC178x/7x ADR/PSW SPEED DP 33 Ω DM 33 Ω USB MINI-AB connector VSSIO, VSSCORE SUSPEND USB_SCL1 SCL SDA USB_SDA1 INT_N USB_INT1 VDD USB_UP_LED1 002aag507 Fig 33.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D-1 33 Ω D15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA OUTA 5V IN LPC178x/7x USB_PPWR2 LM3526-L ENB VDD OUTB FLAGB USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω USB_D-2 33 Ω D+ USB-A connector D15 kΩ VSSIO, 15 kΩ VSSCORE VDD USB_UP_LED2 002aag508 Fig 34.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D-1 33 Ω D15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA 5V IN LM3526-L OUTA LPC178x/7x VDD USB_UP_LED2 VDD USB_CONNECT2 VSSIO, VSSCORE USB_D+2 33 Ω D+ USB_D-2 33 Ω D- VBUS USB-B connector VBUS 002aag509 Fig 35. USB device port configuration: port 1 host and port 2 device 14.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LPC1xxx XTAL1 Ci 100 pF Cg 002aae835 Fig 36. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 36), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 32.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller VDD VDD open-drain enable pin configured as digital output driver strong pull-up output enable ESD data output PIN strong pull-down ESD VSS VDD weak pull-up pull-up enable pin configured as digital input weak pull-down repeater mode enable pull-down enable data input select analog input pin configured as analog input analog input 002aaf272 Fig 38. Standard I/O pin configuration with analog input 14.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller To eliminate the loss of time counts in the RTC due to voltage swing or ramp rate of the RESET signal, connect an RC filter between the RESET pin and the external reset input. 10 kΩ RESET pin 0.1 μF External RESET input 002aag552 Fig 40. Reset input with RC filter LPC178X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 9 September 2014 © NXP Semiconductors N.V. 2014.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 15. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 105 156 157 104 ZE e E HE (A 3) A A2 A1 wM θ Lp bp L detail X pin 1 index 208 53 1 52 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller TFBGA180: thin fine-pitch ball grid array package; 180 balls SOT570-3 A B D ball A1 index area E A2 A A1 detail X e1 e 1/2 e ∅v ∅w b M M C C A B C y y1 C P N M L K J H G F E D C B A ball A1 index area e e2 1/2 e 1 2 3 4 5 6 7 8 9 10 11 12 13 X 14 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A A1 A2 b D E e e1 e2 v w y y1 1.20 1.06 0.95 0.40 0.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 73 72 108 109 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 16. Soldering Footprint information for reflow soldering of LQFP208 package SOT459-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 31.300 31.300 28.300 28.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 28.500 28.500 31.550 31.550 sot459-1_fr Fig 45.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of TFBGA180 package SOT570-3 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 0.80 0.400 0.400 0.550 Hx Hy 12.575 12.575 sot570-3_fr Fig 46.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 23.300 23.300 20.300 20.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 20.500 20.500 23.550 23.550 sot486-1_fr Fig 47.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 17. Abbreviations Table 34.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 18. References LPC178X_7X Product data sheet [1] LPC178x/7x User manual UM10470: http://www.nxp.com/documents/user_manual/UM10470.pdf [2] LPC177x/8x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC177X_8X.pdf [3] Technical note ADC design guidelines: http://www.nxp.com/documents/technical_note/TN00009.pdf All information provided in this document is subject to legal disclaimers. Rev.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 19. Revision history Table 35. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC178X_7X v.5.1 20140909 Product data sheet - LPC178X_7X v.5 Modifications: LPC178X_7X v.5 Modifications: • Updated parameter tsu(D) in Table 18 “Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00”: Minimum value changed to (FBCLKDLY + 1)  0.25 + 0.3.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 35. Revision history …continued Document ID Modifications: LPC178X_7X v.4 Modifications: LPC178X_7X v.3 LPC178X_7X Product data sheet Release date Data sheet status Change notice Supersedes • LCD timing characteristics updated in Table 27 “Dynamic characteristics: LCD” and Figure 26 added. • Removed table note “The peak current is limited to 25 times the corresponding maximum current.” in Table 9.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Table 35. Revision history …continued Document ID Modifications: LPC178X_7X v.2 Modifications: LPC178X_7X v.1 LPC178X_7X Product data sheet Release date • • • • • • • • • • • • • • • • • • Change notice Supersedes IBAT and IDD(REG)(3V3) updated for Deep power-down mode in Table 13. Maximum SDRAM clock of 80 MHz specified in Section 2, Table 18, and Table 19. Power consumption data added (Figure 9 and Figure 10).
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 Pinning . . .
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LPC178x/7x NXP Semiconductors 32-bit ARM Cortex-M3 microcontroller 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 12 13 14 14.1 14.2 14.3 14.4 14.5 14.6 15 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 69 Thermal characteristics . . . . . . . . . . . . . . . . . 70 Static characteristics. . . . . . . . . . . . . . . . . . . . 71 Power consumption . . . . . . . . . . . . . . . . . . . .