LPC2131/32/34/36/38 Single-chip 16/32-bit microcontrollers; 32/64/128/256/512 kB ISP/IAP flash with 10-bit ADC and DAC Rev. 5.1 — 29 July 2011 Product data sheet 1. General description The LPC2131/32/34/36/38 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine the microcontroller with 32 kB, 64 kB, 128 kB, 256 kB and 512 kB of embedded high-speed flash memory.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers One (LPC2131/32) or two (LPC2134/36/38) 8-channel 10-bit ADCs provide a total of up to 16 analog inputs, with conversion times as low as 2.44 s per channel. Single 10-bit DAC provides variable analog output (LPC2132/34/36/38). Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 3.1 Ordering options Table 2.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 4.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 5. Pinning information 49 VBAT 50 VSS 51 VDD 52 P1.30/TMS 53 P0.18/CAP1.3/MISO1/MAT1.3 54 P0.19/MAT1.2/MOSI1/CAP1.2 55 P0.20/MAT1.3/SSEL1/EINT3 56 P1.29/TCK 57 RESET 58 P0.23 59 VSSA 60 P1.28/TDI 61 XTAL2 62 XTAL1 63 VREF 64 P1.27/TDO 5.1 Pinning P0.21/PWM5/CAP1.3 1 48 P1.20/TRACESYNC P0.22/CAP0.0/MAT0.0 2 47 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 3 46 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 4 45 P0.
LPC2131/32/34/36/38 NXP Semiconductors 49 VBAT 50 VSS 51 VDD 52 P1.30/TMS 53 P0.18/CAP1.3/MISO1/MAT1.3 54 P0.19/MAT1.2/MOSI1/CAP1.2 55 P0.20/MAT1.3/SSEL1/EINT3 56 P1.29/TCK 57 RESET 58 P0.23 59 VSSA 60 P1.28/TDI 61 XTAL2 62 XTAL1 63 VREF 64 P1.27/TDO Single-chip 16/32-bit microcontrollers P0.21/PWM5/CAP1.3 1 48 P1.20/TRACESYNC P0.22/CAP0.0/MAT0.0 2 47 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 3 46 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 4 45 P0.15/EINT2 RTCX2 5 44 P1.
LPC2131/32/34/36/38 NXP Semiconductors 49 VBAT 50 VSS 51 VDD 52 P1.30/TMS 53 P0.18/CAP1.3/MISO1/MAT1.3 54 P0.19/MAT1.2/MOSI1/CAP1.2 55 P0.20/MAT1.3/SSEL1/EINT3 56 P1.29/TCK 57 RESET 58 P0.23 59 VSSA 60 P1.28/TDI 61 XTAL2 62 XTAL1 63 VREF 64 P1.27/TDO Single-chip 16/32-bit microcontrollers P0.21/PWM5/AD1.6/CAP1.3 1 48 P1.20/TRACESYNC P0.22/AD1.7/CAP0.0/MAT0.0 2 47 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 3 46 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 4 45 P0.15/RI1/EINT2/AD1.
LPC2131/32/34/36/38 NXP Semiconductors 49 VBAT 50 VSS 51 VDD 52 P1.30/TMS 53 P0.18/CAP1.3/MISO1/MAT1.3 54 P0.19/MAT1.2/MOSI1/CAP1.2 55 P0.20/MAT1.3/SSEL1/EINT3 56 P1.29/TCK 57 RESET 58 P0.23 59 VSSA 60 P1.28/TDI 61 XTAL2 62 XTAL1 terminal 1 index area 63 VREF 64 P1.27/TDO Single-chip 16/32-bit microcontrollers P0.21/PWM5/AD1.6/CAP1.3 1 48 P1.20/TRACESYNC P0.22/AD1.7/CAP0.0/MAT0.0 2 47 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 3 46 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 4 45 P0.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 5.2 Pin description Table 3. Pin description Symbol Pin P0.0 to P0.31 Type Description I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while P0.31 is output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pin P0.24 is not available.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description P0.11/CTS1/ CAP1.1/SCL1 37[3] I CTS1 — Clear to Send input for UART1. Available in LPC2134/36/38. I CAP1.1 — Capture input for Timer 1, channel 1. I/O SCL1 — I2C1 clock input/output. Open drain output (for I2C-bus compliance) I DSR1 — Data Set Ready input for UART1. Available in LPC2134/36/38. O MAT1.0 — Match output for Timer 1, channel 0.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description P0.23 58[1] I/O General purpose digital input/output pin. P0.25/AD0.4/ AOUT 9[5] I AD0.4 — ADC 0, input 4. This analog input is always connected to its pin. O AOUT — DAC output. Not available in LPC2131. P0.26/AD0.5 10[4] I AD0.5 — ADC 0, input 5. This analog input is always connected to its pin. P0.27/AD0.0/ 11[4] CAP0.1/MAT0.1 I AD0.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description P1.26/RTCK 24[6] I/O RTCK — Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate as Debug port after reset. P1.27/TDO 64[6] O TDO — Test Data out for JTAG interface. P1.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 6. Functional description 6.1 Architectural overview The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 6.4 Memory map The LPC2131/32/34/36/38 memory map incorporates several distinct regions, as shown in Figure 6. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in Section 6.18 “System control”. 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 0xF000 0000 3.75 GB APB PERIPHERALS 3.5 GB 0xE000 0000 3.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt ReQuest (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers Table 4.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 6.7.2 Fast I/O features available in LPC213x/01 only • • • • Fast I/O registers are located on the ARM local bus for the fastest possible I/O timing. All GPIO registers are byte addressable. Entire port value can be written in one instruction. Mask registers allow single instruction to set or clear any number of bits in one port. 6.8 10-bit ADC The LPC2131/32 contain one and the LPC2134/36/38 contain two ADCs.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers • Built-in baud rate generator. • Standard modem interface signals included on UART1. (LPC2134/36/38 only) • The LPC2131/32/34/36/38 transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs and hardware (CTS/RTS) flow control on the LPC2134/36/38 UART1 only. 6.10.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 6.12.1 Features • • • • Compliant with Serial Peripheral Interface (SPI) specification. Synchronous, Serial, Full Duplex, Communication. Combined SPI master and slave. Maximum data bit rate of one eighth of the input clock rate. 6.13 SSP serial I/O controller The LPC2131/32/34/36/38 each contain one Serial Synchronous Port controller (SSP). The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Four external outputs per timer/counter corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. 6.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 6.17 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2131/32/34/36/38. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. 6.18 System control 6.18.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 6.18.8 Power Control The LPC2131/32/34/36/38 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers The ARM core has a Debug Communication Channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions VDD supply voltage (core and external rail) VDDA analog 3.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 8. Static characteristics Table 6. Static characteristics Tamb = 40 C to +85 C for commercial applications, unless otherwise specified. Min Typ[1] Max Unit supply voltage (core and external rail) 3.0 3.3 3.6 V VDDA analog 3.3 V pad supply voltage 2.5 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT 2.0 3.3 3.6 V Vi(VREF) input voltage on pin VREF 2.5 3.3 3.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers Table 6. Static characteristics …continued Tamb = 40 C to +85 C for commercial applications, unless otherwise specified. Min Typ[1] Max Unit - 14 - A VDD = 3.0 V; Vi(VBAT) = 3.0 V - 16 - A VDD = 3.3 V; Vi(VBAT) = 3.3 V - 18 - A VDD = 3.6 V; Vi(VBAT) = 3.6 V - 20 - A VDD = 3.0 V; Vi(VBAT) = 3.0 V - 78 - A VDD = 3.3 V; Vi(VBAT) = 3.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers [4] VDD supply voltages must be present. [5] 3-state outputs go into 3-state mode when VDD is grounded. [6] Please also see the errata note mentioned in the errata sheet. [7] Accounts for 100 mV voltage drop in all supply lines. [8] Only allowed for a short time period. [9] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V. [10] Applies to P1.16 to P1.25. [11] On pin VBAT.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 9.1 Timing tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 7. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 9.2 LPC2138 power consumption measurements 002aab404 40 (1) (2) (3) (4) (5) IDD (mA) 30 20 10 0 0 10 20 30 40 50 60 frequency (MHz) Test conditions: code executed from flash; all peripherals are enabled in PCONP register; PCLK = CCLK/4. (1) VDD = 3.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 002aab403 15 IDD (mA) (1) (2) (3) (4) (5) 10 5 0 0 10 20 30 40 50 60 frequency (MHz) Test conditions: Idle mode entered executing code from flash; all peripherals are enabled in PCONP register; PCLK = CCLK/4. (1) VDD = 3.6 V at 140 C (max) (2) VDD = 3.6 V at 60 C (3) VDD = 3.6 V at 25 C (4) VDD = 3.3 V at 25 C (typical) (5) VDD = 3.3 V at 95 C (typical) Fig 9.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 10. ADC electrical characteristics Table 8. ADC static characteristics VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = Vi(VREF) − VSSA 1024 002aae604 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers LPC2131/32/34/36/38 20 kΩ ADx.y ADx.ySAMPLE 3 pF Rvsi 5 pF VEXT VSS 002aad452 Fig 12. Suggested ADC interface - LPC2131/32/34/36/38 ADx.y pin LPC2131_32_34_36_38 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 29 July 2011 © NXP B.V. 2011. All rights reserved.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 11. DAC electrical characteristics Table 9. DAC electrical characteristics VDDA = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol Parameter ED Min Typ Max Unit differential linearity error - 1 - LSB EL(adj) integral non-linearity - 1.5 - LSB EO offset error - 0.6 - % EG gain error - 0.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 12. Application information 12.1 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers LPC2xxx L XTAL1 XTAL2 = CL CP XTAL RS CX2 CX1 002aag469 Fig 14. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 10.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 12.2 RTC 32 kHz oscillator component selection LPC2xxx L RTCX1 RTCX2 = CL CP 32 kHz XTAL RS CX1 CX2 002aaf495 Fig 15. RTC oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation The RTC external oscillator circuit is shown in Figure 15.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 13. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm SOT804-2 B D D1 A terminal 1 index area A A4 E1 E c A1 detail X C e1 e 1/2 17 y1 C v M C A B w M C b e y 32 L 33 16 e e2 Eh 1/2 1 terminal 1 index area e 48 49 64 X Dh 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 14. Abbreviations Table 13.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 15. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC2131_32_34_36_38 v.5.1 20110729 Product data sheet - LPC2131_32_34_36_38 v.5 Modifications: LPC2131_32_34_36_38 v.5 Modifications: • • Parameter Isink added in Table 5 “Limiting values”.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
LPC2131/32/34/36/38 NXP Semiconductors Single-chip 16/32-bit microcontrollers Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
NXP Semiconductors LPC2131/32/34/36/38 Single-chip 16/32-bit microcontrollers 18. Contents 1 2 2.1 2.2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.6 6.7 6.7.1 6.7.2 6.8 6.8.1 6.8.2 6.9 6.9.1 6.10 6.10.1 6.10.2 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Enhancements brought by LPC213x/01 devices . . . . . . . . . . . . . . . . . . .