LPC2468 Single-chip 16-bit/32-bit micro; 512 kB flash, Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 6.2 — 11 January 2013 Product data sheet 1. General description NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2468 has 512 kB of on-chip high-speed flash memory.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro LPC2468 Product data sheet 16 kB SRAM for general purpose DMA use also accessible by the USB. 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain. Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Two independent power domains allow fine tuning of power consumption based on needed features. Each peripheral has its own clock divider for further power saving. These dividers help reduce active power by 20 % to 30 %. Brownout detect with separate thresholds for interrupt and forced reset. On-chip power-on reset. On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 5.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 6. Pinning information 157 208 6.1 Pinning 1 156 LPC2468FBD208 105 53 104 52 Fig 2. 002aac734 LPC2468 pinning LQFP208 package ball A1 index area 2 1 4 3 6 5 8 7 9 10 12 14 16 11 13 15 17 A B C D E F G H LPC2468FET208 J K L M N P R T U 002aac735 Transparent top view Fig 3. Table 3.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 3.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row H 1 P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] 2 P3[14]/D14 3 P3[30]/D30/ MAT1[1]/RTS1 4 VDD(DCDC)(3V3) 14 VSSIO 15 P2[8]/TD2/ TXD2/TRACEPKT3 16 P2[9]/ USB_CONNECT1/ RXD2/EXTIN0 17 P4[9]/A9 Row J 1 P3[6]/D6 2 VSSA 3 P3[31]/D31/MAT1[2] 4 n.c.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 3.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P0[3]/RXD0 204[1] D6[1] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. P0[4]/ I2SRX_CLK/ RD2/CAP2[0] 168[1] B12[1] I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P0[12]/ USB_PPWR2/ MISO1/AD0[6] 41[2] R1[2] I/O P0[12] — General purpose digital input/output pin. O USB_PPWR2 — Port Power enable signal for USB port 2. I/O MISO1 — Master In Slave Out for SSP1. I AD0[6] — A/D converter 0, input 6. P0[13]/ USB_UP_LED2/ MOSI1/AD0[7] 45[2] I/O P0[13] — General purpose digital input/output pin.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P0[21]/RI1/ MCIPWR/RD1 118[1] M16[1] I/O P0[21] — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. O MCIPWR — Power Supply Enable for external SD/MMC power supply.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P1[0]/ ENET_TXD0 196[1] A3[1] I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). P1[1]/ ENET_TXD1 194[1] B5[1] I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P1[13]/ ENET_RX_DV 147[1] D16[1] I/O P1[13] — General purpose digital input/output pin. I ENET_RX_DV — Ethernet Receive Data Valid (MII interface). P1[14]/ ENET_RX_ER 184[1] A7[1] I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error (RMII/MII interface).
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P1[24]/ USB_RX_DM1/ PWM1[5]/MOSI0 78[1] T9[1] I/O P1[24] — General purpose digital input/output pin. I USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver). O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P2[1]/PWM1[2]/ RXD1/ PIPESTAT0 152[1] E14[1] I/O P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P2[11]/EINT1/ MCIDAT1/ I2STX_CLK 108[6] T17[6] I/O P2[11] — General purpose digital input/output pin. I EINT1 — External interrupt 1 input. I/O MCIDAT1 — Data line 1 for SD/MMC interface. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P2[23]/DYCS3/ CAP3[1]/SSEL0 64[1] U5[1] I/O P2[23] — General purpose digital input/output pin. O DYCS3 — SDRAM chip select 3. I CAP3[1] — Capture input for Timer 3, channel 1. I/O SSEL0 — Slave Select for SSP0. I/O P2[24] — General purpose digital input/output pin. P2[24]/ CKEOUT0 53[1] P5[1] O CKEOUT0 — SDRAM clock enable 0.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P3[5]/D5 17[1] G1[1] I/O P3[5] — General purpose digital input/output pin. I/O D5 — External memory data line 5. P3[6]/D6 23[1] J1[1] I/O P3[6] — General purpose digital input/output pin. I/O D6 — External memory data line 6. P3[7]/D7 27[1] L1[1] I/O P3[7] — General purpose digital input/output pin. I/O D7 — External memory data line 7.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P3[20]/D20/ PWM0[5]/DSR1 167[1] A13[1] I/O P3[20] — General purpose digital input/output pin. I/O D20 — External memory data line 20. O PWM0[5] — Pulse Width Modulator 0, output 5.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P3[30]/D30/ MAT1[1]/ RTS1 19[1] H3[1] I/O P3[30] — General purpose digital input/output pin. I/O D30 — External memory data line 30. O MAT1[1] — Match output for Timer 1, channel 1. P3[31]/D31/ MAT1[2] 25[1] J3[1] P4[0] to P4[31] O RTS1 — Request to Send output for UART1. I/O P3[31] — General purpose digital input/output pin.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P4[15]/A15 173[1] A11[1] I/O P4[15] — General purpose digital input/output pin. I/O A15 — External memory address line 15. P4[16]/A16 101[1] U17[1] I/O P4[16] — General purpose digital input/output pin. I/O A16 — External memory address line 16. P4[17]/A17 104[1] P14[1] I/O P4[17] — General purpose digital input/output pin.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball Type Description P4[29]/BLS3/ MAT2[1]/RXD3 176[1] B10[1] I/O P4[29] — General purpose digital input/output pin. O BLS3 — LOW active Byte Lane select signal 3. O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. I/O P4[30] — General purpose digital input/output pin. P4[30]/CS0 187[1] B7[1] O CS0 — LOW active Chip Select 0 signal.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 4. Pin description …continued Symbol Pin Ball VDD(3V3) 15, 60, 71, 89, 112, 125, 146, 165, 181, 198[15] G3, P6, I P8, U13, P17, K16, C17, B13, C9, D7[15] Type Description 3.3 V supply voltage: This is the power supply voltage for the I/O ports. n.c. 30, 117, 141[16] J4, L14, I G14[16] not connected pins: These pins must be left unconnected (floating). VDD(DCDC)(3V3) 26, 86, 174[17] H4, P11, I D11[17] 3.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 7. Functional description 7.1 Architectural overview The LPC2468 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro The Thumb set’s 16-bit instruction length allows it to approach higher density compared to standard ARM code while retaining most of the ARM’s performance. 7.2 On-chip flash programming memory The LPC2468 incorporates 512 kB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0).
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 5.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 0xFFFF FFFF 4.0 GB AHB PERIPHERALS 0xF000 0000 3.75 GB APB PERIPHERALS 0xE000 0000 0xDFFF FFFF 3.5 GB EXTERNAL STATIC AND DYNAMIC MEMORY 2.0 GB 0x8000 0000 0x7FFF FFFF BOOT ROM AND BOOT FLASH (BOOT FLASH REMAPPED FROM ON-CHIP FLASH) RESERVED ADDRESS SPACE ON-CHIP STATIC RAM 1.0 GB 0x4000 0000 0x3FFF FFFF SPECIAL REGISTERS 0x3FFF 8000 RESERVED ADDRESS SPACE 0x0008 0000 0x0007 FFFF ON-CHIP NON-VOLATILE MEMORY 0.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control CKE and CLKOUT to SDRAMs • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048, 4096, and 8192 row address synchronous memory parts.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro • One AHB master for transferring data. This interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral. • Internal four-word FIFO per channel.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.10 Ethernet The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.11 USB interface The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.11.2.1 Features • OHCI compliant. • Two downstream ports. • Supports per-port power switching. 7.11.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro • Acceptance Filter can provide Full CAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.13 10-bit ADC The LPC2468 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.13.1 Features • • • • • • • • 10-bit successive approximation ADC Input multiplexing among 8 pins Power-down mode Measurement range 0 V to Vi(VREF) 10-bit conversion time 2.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • UART3 includes an IrDA mode to support infrared communication. 7.16 SPI serial I/O controller The LPC2468 contains one SPI controller.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.18.1 Features • The MCI interface provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. • Can be used as a multimedia card bus or a secure digital memory card bus host.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC2468 provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.20.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2468. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power is removed, the RTC can supply an alarm output that can be used by external hardware to restore chip power and resume operation. 7.24.1 Features • Measures the passage of time to maintain a calendar and clock.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.25.2 for additional information. 7.25.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU. 7.25.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.25.4 Power control The LPC2468 supports a variety of power control features. There are four special modes of processor power reduction: Idle mode, Sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro the meantime, the flash Wake-up Timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. The customers need to reconfigure the PLL and clock dividers accordingly. 7.25.4.4 Deep power-down mode Deep power-down mode is similar to the Power-down mode, but now the on-chip regulator that supplies power to the internal logic is also shut off.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 7.26 System control 7.26.1 Reset Reset has four sources on the LPC2468: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up Timer (see description in Section 7.25.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.26.4 AHB The LPC2468 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate. 7.27.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.6 V 3.0 3.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +4.6 V 0.5 +5.1 V [2] 0.5 +6.0 V other I/O pins [2][3] 0.5 VDD(3V3) + 0.5 V per supply pin [4] - 100 mA - 100 mA 65 +150 C - 1.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb + P D R th j – a (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 10. Static characteristics Table 9. Static characteristics Tamb = 40 C to +85 C for commercial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V VDD(DCDC)(3V3) DC-to-DC converter supply voltage (3.3 V) 3.0 3.3 3.6 V VDDA analog 3.3 V pad supply voltage 3.0 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT 2.0 3.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 9. Static characteristics …continued Tamb = 40 C to +85 C for commercial applications, unless otherwise specified.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 9. Static characteristics …continued Tamb = 40 C to +85 C for commercial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 1.8 1.95 V Vo(RTCX2) output voltage on pin RTCX2 0.5 1.8 1.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 10.1 Power-down mode 002aae049 4 IDD(IO) (μA) 2 VDD(3V3) = 3.3 V VDD(3V3) = 3.0 V 0 −2 −4 −40 −15 10 35 60 85 temperature (°C) Vi(VBAT) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C. Fig 5. I/O maximum supply current IDD(IO) versus temperature in Power-down mode 002aae050 40 IBAT (μA) 30 Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C. Fig 6.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 002aae051 800 IDD(DCDC)pd(3v3) (μA) 600 400 VDD(DCDC)(3V3) = 3.3 V 200 0 −40 VDD(DCDC)(3V3) = 3.0 V −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 C. Fig 7. Total DC-to-DC converter supply current IDD(DCDC)pd(3V3) at different temperatures in Power-down mode 10.2 Deep power-down mode 002aae046 300 IDD(IO) (μA) 200 100 VDD(3V3) = 3.3 V VDD(3V3) = 3.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 002aae047 40 IBAT (μA) 30 Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 C Fig 9. RTC battery maximum supply current IBAT versus temperature in Deep power-down mode 002aae048 100 IDD(DCDC)dpd(3v3) (μA) 80 60 VDD(DCDC)(3V3) = 3.3 V 40 VDD(DCDC)(3V3) = 3.0 V 20 0 −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 C. Fig 10.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 10.3 Electrical pin characteristics 002aaf112 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2.0 0 8 16 24 IOH (mA) Conditions: VDD(3V3) = 3.3 V; standard port pins. Fig 11. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aaf111 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD(3V3) = 3.3 V; standard port pins. Fig 12.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 11. Dynamic characteristics Table 10. Dynamic characteristics Tamb = 40 C to +85 C for commercial applications; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Typ[2] Min Max Unit External clock fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) 0.4 - - ns tCLCX clock LOW time Tcy(clk) 0.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.1 Internal oscillators Table 11. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 3.0 V VDD(3V3) 3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz fi(RTC) RTC input frequency - - 32.768 - kHz Max Unit [1] Parameters are valid over operating temperature range unless otherwise specified.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.4 Flash memory Table 14. Dynamic characteristics of flash Tamb = 40 C to +85 C, unless otherwise specified; VDD(3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Symbol Parameter Conditions Min Typ Max Unit 0.78 + Tcy(CCLK) 2.54 + Tcy(CCLK) 5.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.6 Dynamic external memory interface Table 16. Dynamic characteristics: Dynamic external memory interface CL = 30 pF, Tamb = 40 C to 85 C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V, EMC Dynamic Read Config Register = 0x0 (RD = 00) Symbol Parameter Conditions Min Typ Max Unit 1.05 1.76 ns Common chip select valid delay time [1] - th(S) chip select hold time [1] 0.1 1.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 17. Dynamic characteristics: Dynamic external memory interface CL = 30 pF on all pins, Tamb = 40 C to 85 C, VDD(DCDC)(3V3) = VDD(3V3) = 3.3 V, EMC Dynamic Read Config Register = 0x1 (RD = 01), Tcy(CCLK) = 1/CCLK Symbol Parameter Conditions Min Typ Max Unit 3 + Tcy(CCLK) 1.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.7 Timing tCSLAV tCSHOEH CS addr tam th(D) data tCSLOEL tOELAV tOEHANV tOELOEH OE tCSHBLSH tBLSLAV BLS 002aad955 Fig 14. External memory read access CS tCSLAV tCSLWEL tWELWEH tBLSLBLSH BLS/WE tWEHANV tCSLBLSL tWELDV tBLSHANV addr tCSLDV tWEHDNV tBLSHDNV data OE 002aad956 Fig 15. External memory write access LPC2468 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 16. Differential data-to-EOP transition skew and EOP width shifting edges SCK sampling edges MOSI MISO tsu(SPI_MISO) 002aad326 Fig 17.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 12. ADC electrical characteristics Table 18. ADC static characteristics VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = Vi(VREF) − VSSA 1024 002aae604 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro LPC2XXX 20 kΩ AD0[y] AD0[y]SAMPLE 3 pF Rvsi 5 pF VEXT VSSIO, VSSCORE 002aad586 Fig 20. Suggested ADC interface - LPC2468 AD0[y] pin LPC2468 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.2 — 11 January 2013 © NXP B.V. 2013. All rights reserved.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 13. DAC electrical characteristics Table 19. DAC electrical characteristics VDDA = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol Parameter ED Min Typ Max Unit differential linearity error - 1 - LSB EL(adj) integral non-linearity - 1.5 - LSB EO offset error - 0.6 - % EG gain error - 0.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 14. Application information 14.1 Suggested USB interface solutions VDD(3V3) USB_UP_LED USB_CONNECT LPC24XX soft-connect switch R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB_D− USB-B connector RS = 33 Ω VSSIO, VSSCORE 002aad587 Fig 21. LPC2468 USB interface on a self-powered device VDD(3V3) R2 LPC24XX USB_UP_LED R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSSIO, VSSCORE 002aad588 Fig 22.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro VDD R1 R2 R3 R4 RSTOUT RESET_N VBUS ADR/PSW ID OE_N/INT_N VDD SPEED SUSPEND R4 R5 ISP1302 DP 33 Ω DM 33 Ω R6 VSSIO, VSSCORE SCL USB_SCL1 Mini-AB connector SDA USB_SDA1 USB_INT1 INT_N USB_D+1 USB_D−1 VDD USB_UP_LED1 LPC24XX R7 5V VDD IN USB_PPWR2 ENA LM3526-L OUTA FLAGA USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω D+ USB_D−2 33 Ω D− 15 kΩ 15 kΩ USB-A connector VSSIO, VSSCORE VDD USB_UP_LED2 R8 002aad589
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro VDD RSTOUT RESET_N OE_N/INT_N USB_TX_E1 USB_TX_DP1 DAT_VP USB_TX_DM1 SE0_VM RCV USB_RCV1 USB_RX_DP1 USB_RX_DM1 VP VBUS VM ID VDD ISP1302 LPC24XX ADR/PSW SPEED DP 33 Ω DM 33 Ω USB MINI-AB connector VSSIO, VSSCORE SUSPEND USB_SCL1 SCL USB_SDA1 SDA INT_N USB_INT1 VDD USB_UP_LED1 002aad590 Fig 24.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D−1 33 Ω D− 15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA 5V IN LM3526-L OUTA LPC24XX VDD USB_UP_LED2 VDD USB_CONNECT2 VSSIO, VSSCORE USB_D+2 33 Ω D+ USB_D−2 33 Ω D− VBUS USB-B connector VBUS 002aad595 Fig 25.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D−1 33 Ω D− 15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA OUTA 5V IN LPC24XX USB_PPWR2 LM3526-L ENB VDD OUTB FLAGB USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω D+ USB_D−2 33 Ω D− 15 kΩ USB-A connector VSSIO, VSSCORE 15 kΩ VDD USB_UP_LED2 002aad596 Fig 26. LPC2468 USB OTG port configuration: USB port 1 host, USB port 2 host 14.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 27), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTAL2 pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 28 and in Table 20 and Table 21.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Table 21. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF 20 pF < 100 39 pF, 39 pF 10 pF < 160 18 pF, 18 pF 20 pF < 80 39 pF, 39 pF 20 MHz to 25 MHz 14.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors CX1, CX2, and CX3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 14.6 Reset pin configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 31. Reset pin configuration LPC2468 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.2 — 11 January 2013 © NXP B.V. 2013. All rights reserved.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 15. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 105 156 157 104 ZE e E HE (A 3) A A2 A1 wM θ Lp bp L detail X pin 1 index 208 53 1 52 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 28.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm B D SOT950-1 A ball A1 index area A2 A E A1 detail X e1 ∅v ∅w b e M M C C A B C y y1 C U T R P N M L K J H G F E D C B A e e2 ball A1 index area 1 3 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.2 0.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 16. Abbreviations Table 23.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 17. Revision history Table 24. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC2468 v.6.2 20130111 Product data sheet - LPC2468 v.6.1 Modifications: LPC2468 v.6.1 Modifications: LPC2468 v.6 Modifications: LPC2468 v.5 • • • Table 4 “Pin description”, Table note 6: Changed glitch filter spec from 5 ns to 10 ns. Table 10 “Dynamic characteristics”: Changed min clock cycle time from 42 to 40.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
LPC2468 NXP Semiconductors Single-chip 16-bit/32-bit micro 11.5 11.6 11.7 12 13 14 14.1 14.2 14.3 14.4 14.5 14.6 15 16 17 18 18.1 18.2 18.3 18.4 19 20 Static external memory interface . . . . . . . . . . Dynamic external memory interface . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC electrical characteristics . . . . . . . . . . . . DAC electrical characteristics . . . . . . . . . . . . Application information. . . . . . . . . . . . . . . . . .