LPC408x/7x 32-bit ARM Cortex-M4 MCU; up to 512 kB flash, 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC; SPIFI Rev. 3.1 — 1 September 2014 Product data sheet 1. General description The LPC408x/7x is an ARM Cortex-M4 based digital signal controller for embedded applications requiring a high level of integration and low power dissipation.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LPC408X_7X Product data sheet Hardware floating-point unit (not all versions). Non-maskable Interrupt (NMI) input. JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points. System tick timer. System: Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, and General Purpose DMA controller.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one UART (USART4) supports IrDA, synchronous mode, and a smart card mode conforming to ISO7816-3. Three SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. Two analog comparators. Power control: Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC4088 LPC4088FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1 LPC4088FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 2.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller slave ARM CORTEX-M4 I-code bus LPC408x/7x FPU(1) TEST/DEBUG INTERFACE GPDMA CONTROLLER MPU EMULATION TRACE MODULE 5.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 6. Pinning information 156 105 6.1 Pinning 157 104 LPC408x/7x 53 1 52 208 Pin configuration (LQFP208) 73 108 Fig 2. 002aag732 109 72 LPC408x/7x 37 1 36 144 51 Pin configuration (LQFP144) 75 Fig 3. 002aag735 76 50 LPC407x Fig 4. LPC408X_7X Product data sheet 25 26 1 100 002aah638 Pin configuration (LQFP100) All information provided in this document is subject to legal disclaimers. Rev. 3.
LPC408x/7x NXP Semiconductors 41 60 32-bit ARM Cortex-M4 microcontroller 61 40 LPC408x/7x 21 1 20 80 Fig 5. 002aag865 Pin configuration (LQFP80) ball A1 index area 2 1 4 3 6 5 8 7 9 10 12 14 16 11 13 15 17 A B C D E F G H J LPC408x/7x K L M N P R T U 002aag733 Transparent top view Fig 6. LPC408X_7X Product data sheet Pin configuration (TFBGA208) All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 1 September 2014 © NXP Semiconductors N.V.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller ball A1 index area LPC408x/7x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P 002aag734 Transparent top view Fig 7. Pin configuration (TFBGA180) ball A1 index area LPC4072FET80 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 002aah684 Transparent top view Fig 8. Pin configuration (TFBGA80) 6.
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LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [10] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. [11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 1 MHz specification. It requires an external pull-up to provide output functionality.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.5 EEPROM The LPC408x/7x contains up to 4032 byte of on-chip byte-erasable and byte-programmable EEPROM data memory. 7.6 On-chip SRAM The LPC408x/7x contain a total of up to 96 kB on-chip SRAM data memory. This includes 64 kB main SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and up to two additional 16 kB peripheral SRAM blocks situated on a separate slave port on the AHB multilayer matrix.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 4.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.10 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupts being enabled.
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LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.11.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. • • • • • Low transaction latency. Read and write buffers to reduce latency and to improve performance. 8/16/32 data and 16/20/26 address lines wide static memory support. 16 bit and 32 bit wide chip select SDRAM memory support.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.14 LCD controller Remark: The LCD controller is available on parts LPC4088. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024 768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.16 USB interface Remark: The USB Device/Host/OTG controller is available on parts LPC4088/78/76. The USB Device-only controller is available on part LPC4074/72. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.16.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface controls an external OTG transceiver. 7.16.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • • • • All GPIO registers are byte and half-word addressable. Entire port value can be written in one instruction. Support for Cortex-M4 bit banding. Support for use with the GPDMA controller.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller • • • • • Buffered output. Power-down mode. Selectable output drive. Dedicated conversion timer. DMA support. 7.21 Comparator Remark: The comparator is available on parts LPC4088/7876. Two embedded comparators are available to compare the voltage levels on external pins or against internal voltages. Up to four voltages on external pins and several internal reference voltages are selectable on each comparator.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller • • • • 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto-baud capability.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.24.1 Features • Maximum SSP speed of 33 Mbit/s (master) or 10 Mbit/s (slave). • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses. • • • • • Synchronous serial communication. Master or slave operation. 8-frame FIFOs for both transmit and receive. 4-bit to 16-bit frame. DMA transfers supported by GPDMA. 7.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC408x/7x provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.26.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller • FullCAN messages can generate interrupts. 7.28 General purpose 32-bit timers/external event counters The LPC408x/7x include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2n (see Table 6). Table 6. PWM speed at operating frequency 120 MHz PWM resolution PWM speed 6 bit 1.875 MHz 8 bit 0.468 MHz 10 bit 0.117 MHz 7.31 Quadrature Encoder Interface (QEI) Remark: The QEI is available on parts LPC4088/78/76.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.33.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller • RTC power supply is isolated from the rest of the chip. 7.35 Event monitor/recorder The event monitor/recorder allows recording of tampering events in sealed product enclosures. Sensors report any attempt to open the enclosure, or to tamper with the device in any other way. The event monitor/recorder stores records of such events when the device is powered only by the backup battery. 7.35.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LPC408x/7x IRC oscillator MAIN PLL0 main oscillator (osc_clk) pll_clk sysclk CLKSRCSEL (system clock select) ALT PLL1 alt_pll_clk sysclk pll_clk CCLKSEL (CPU clock select) CPU CLOCK DIVIDER cclk PERIPHERAL CLOCK DIVIDER pclk EMC CLOCK DIVIDER emc_clk USB CLOCK DIVIDER usb_clk sysclk pll_clk alt_pll_clk USBCLKSEL (USB clock select) 002aag737 Fig 10. LPC408x/7x clock generation block diagram 7.36.1.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.36.1.3 RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe. 7.36.1.4 Watchdog oscillator The Watchdog Timer has a dedicated oscillator that provides a 500 kHz clock to the Watchdog Timer that is always running if the Watchdog Timer is enabled.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.36.3 Wake-up timer The LPC408x/7x begin operation at power-up and when awakened from Power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller The DMA controller can continue to work in Sleep mode and has access to the peripheral RAMs and all peripheral registers. The flash memory and the main SRAM are not available in Sleep mode, they are disabled in order to save power. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs. 7.36.4.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.36.4.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly” while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.37 System control 7.37.1 Reset Reset has four sources on the LPC408x/7x: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.36.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.37.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. 7.37.5 AHB multilayer matrix The LPC408x/7x use an AHB multilayer matrix.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 7. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Vi(VREFP) input voltage on pin VREFP VIA analog input voltage on ADC related pins VI input voltage 5 V tolerant digital I/O pins; [2] Min Max Unit 0.5 +4.6 V 0.5 +5.1 V 0.5 +5.5 V 0.5 +3.6 V 0.5 VDD(3V3) + 0.5 V VDD(3V3) 2.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 8. Thermal characteristics VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; Symbol Parameter Tj(max) maximum junction temperature Conditions Min Typ Max Unit - - 125 C Table 9. Thermal resistance (LQFP packages) Tamb = 40 C to +85 C unless otherwise specified. Thermal resistance value (C/W): ±15 % LQFP80 LQFP144 LQFP208 0 m/s 41 31 27 1 m/s 35 28 25 2.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10. Static characteristics Table 11. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Min Typ[1] Max Unit 2.4 3.3 3.6 V 2.4 3.3 3.6 V [3] 2.7 3.3 3.6 V input voltage on pin VBAT [4] 2.1 3.0 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.7 3.3 VDDA V IDD(REG)(3V3) regulator supply current active mode; code (3.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function 0 - 5.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit [20] 0.8 - 2.5 V [20] 0.8 - 2.0 V Conditions VCM differential common mode voltage range includes VDI range Vth(rs)se single-ended receiver switching threshold voltage VOL LOW-level output voltage for low-/full-speed RL of 1.5 k to 3.6 V [20] - - 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10.1 Power consumption 002aah051 1.5 IDD(REG)(3V3) (mA) VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.4 V 1.1 0.7 0.3 -40 -15 10 35 60 85 temperature (°C) Conditions: BOD disabled. Fig 12. Deep-sleep mode: Typical regulator supply current IDD(REG)(3V3) versus temperature 002aah052 900 IDD(REG)(3V3) (μA) 600 300 0 -40 VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.4 V -15 10 35 60 85 temperature (°C) Conditions: BOD disabled. Fig 13.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 002aah074 2.0 IBAT (μA) 1.6 1.2 0.8 0.4 0 -40 -15 10 35 60 85 temperature (°C) Conditions: VDD(REG)(3V3) = VDDA = VDD(3V3) = 0; VBAT = 3.0 V. Fig 14. Part powered off: Typical battery supply current (IBAT) versus temperature 10.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 12. Power consumption for individual analog and digital blocks …continued Tamb = 25 C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4. Peripheral Conditions Typical supply current in mA 12 MHz[1] 48 MHz[1] 120 MHz[2] Motor control PWM 0.04 0.15 0.36 I2C0 0.01 0.03 0.08 I2C1 0.01 0.03 0.1 I2C2 0.01 0.03 0.08 I2C0 + I2C1 + I2C2 0.02 0.1 0.26 SSP0 0.03 0.1 0.26 SSP1 0.02 0.11 0.27 DAC 0.3 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 10.3 Electrical pin characteristics 002aaf112 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2.0 0 8 16 24 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 15. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aaf111 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 16.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 002aaf108 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 17. Typical pull-up current Ipu versus input voltage VI 002aaf109 90 Ipd (μA) 70 T = 85 °C 25 °C −40 °C 50 30 10 −10 0 1 2 3 4 5 VI (V) Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 18.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11. Dynamic characteristics 11.1 Flash memory Table 13. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Nendu endurance tret retention time ter erase time tprog programming time Conditions Min [1] Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 15. Dynamic characteristics: Static external memory interface …continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter[1] Conditions[1] Min Typ Max Unit (WAITRD WAITOEN + 1) Tcy(clk) 9.6 (WAITRD WAITOEN + 1) Tcy(clk) 13.2 (WAITRD WAITOEN + 1) Tcy(clk) 20.2 ns 5.0 7.2 ns 2.7 3.4 4.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [2] Parameters specified for 40 % of VDD(3V3) for rising edges and 60 % of VDD(3V3) for falling edges. [3] Tcy(clk) = 1/EMC_CLK (see LPC408x/7x User manual). [4] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1). [5] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE RD5 RD5 RD5 RD5 EMC_Dx 002aag216 Fig 21. External static memory burst read cycle Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit - - ns Common to read and write cycles clock cycle time [1] 12.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 …continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit Write cycle parameters td(QV) data output valid delay time [2] (CLKDLY + 1) (CLKDLY + 1) (CLKDLY + 1) ns 0.25 + 3.9 0.25 + 5.4 0.25 + 7.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 17. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 …continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit Write cycle parameters td(QV) data output valid delay time (CMDDLY + 1) 0.25 + 5.9 (CMDDLY + 1) 0.25 + 8.7 (CMDDLY + 1) 0.25 + 13.1 ns th(Q) data output hold time (CMDDLY + 1) 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 18. Dynamic characteristics: Dynamic external memory interface programmable clock delays CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V.Values guaranteed by design. Symbol Parameter Conditions Min Max Unit td delay time Programmable delay block 0 (CMDDLY or CLKOUTnDLY bit 0 = 1) [1] 0.1 0.2 ns Programmable delay block 1 (CMDDLY or CLKOUTnDLY bit 1 = 1) [1] 0.2 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.4 Internal oscillators Table 20. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V VDD(3V3) 3.6 V.[1] Typ[2] Max Unit internal RC oscillator frequency 11.88 12 12.12 MHz RTC input frequency 32.768 - kHz Symbol Parameter fosc(RC) fi(RTC) Min - [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller [2] Tamb = 40 C to 85 C; VDD(3V3) = 3.0 V to 3.6 V. [3] Tcy(clk) = 12 Tcy(PCLK). The maximum clock rate in slave mode is 1/12th of the PCLK rate. [4] Tamb = 25 C; VDD(3V3) = 3.3 V. Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI th(Q) DATA VALID DATA VALID tDH tDS MISO CPHA = 1 DATA VALID CPHA = 0 DATA VALID 002aae829 Fig 24.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO CPHA = 1 DATA VALID th(Q) DATA VALID CPHA = 0 DATA VALID 002aae830 Fig 25. SSP slave timing in SPI mode 11.7 I2C-bus Table 23. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 23. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter tHD;DAT data hold time data set-up time tSU;DAT [3][4][8] [9][10] Conditions Min Max Unit Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns [1] See the I2C-bus specification UM10204 for details.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 11.8 I2S-bus interface Table 24. Dynamic characteristics: I2S-bus interface pins CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit common to input and output tr rise time [1] - 6.7 ns tf fall time [1] - 8.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) tf tr I2S_RX_SCK tWH tWL I2S_RX_SDA tsu(D) th(D) I2S_RX_WS tsu(D) 002aag203 tsu(D) Fig 28. I2S-bus timing (receive) 11.9 LCD Remark: The LCD controller is available on parts LPC4088. Table 25. Dynamic characteristics: LCD CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 26. Dynamic characteristics: SD/MMC CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Tcy(clk) SPIFI_SCK tv(Q) th(Q) DATA VALID SPIFI data out DATA VALID tDS DATA VALID SPIFI data in tDH DATA VALID 002aah409 Fig 31. SPIFI timing (Mode 0) 12. Characteristics of the analog peripherals 12.1 ADC electrical characteristics Table 28. 12-bit ADC characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 28. 12-bit ADC characteristics …continued VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit - 1 - LSB EL(adj) integral non-linearity [2][5] EO offset error [2][6] - 1 - LSB EG gain error [2][7] - 1 - LSB ET absolute error [2][8] - - <1.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) offset error EO 1 LSB = VREFP - VSS 4096 002aaf436 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LPC408x/7x C3 Rcmp 90 Ω - 300 Ω 1.6 pF ADC COMPARATOR BLOCK Rsw 500 Ω - 2 kΩ C1 110 fF AD0[n] C2 80 fF Cia Rvsi VSS VEXT 002aah275 The values of resistor components Rcmp and Rsw vary with temperature and input voltage and are process-dependent. Fig 33. ADC interface to pins ADC0_IN[n] Table 29. ADC interface components Component Range Description Rcmp 90 to 300 Switch-on resistance for the comparator input switch.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 31. Comparator characteristics …continued VDDA= 3.0 V and Tamb = 25 C unless noted otherwise. Symbol Parameter Conditions DVO output voltage variation Voffset offset voltage Min Typ Max Unit 0 - VDDA V VIC = 0.1 V - 4 to +4.2 - VIC = 1.5 V - 2 VIC = 2.8 V - 2.5 - 4 - s mV - mV mV Dynamic characteristics tstartup start-up time nominal process tPD propagation delay HIGH to LOW; VDDA = 3.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 33. Comparator voltage ladder reference static characteristics VDDA = 3.3 V; Tamb = -40 C to + 85C. Symbol Parameter Conditions EV(O) output voltage error Internal VDDA supply EV(O) [1] output voltage error Min Typ Max[1] Unit decimal code = 00 0 0 0 % decimal code = 08 0.45 0.5 0.55 % decimal code = 16 0.99 1.1 1.21 % decimal code = 24 1.26 1.4 1.54 % decimal code = 30 1.35 1.5 1.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD(3V3) USB_UP_LED USB_CONNECT LPC40xx SoftConnect switch R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB_D- USB-B connector RS = 33 Ω VSS 002aah267 Fig 34. USB interface on a self-powered device VDD(3V3) R2 LPC40xx USB_UP_LED R1 1.5 kΩ VBUS USB_D+ RS = 33 Ω USB_D- RS = 33 Ω USB-B connector VSS 002aah268 Fig 35.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD R1 R2 R3 R4 RSTOUT RESET_N VBUS ADR/PSW ID OE_N/INT_N VDD SPEED SUSPEND R4 R5 ISP1302 DP 33 Ω DM 33 Ω R6 USB_SCL1 SCL USB_SDA1 SDA USB_INT1 Mini-AB connector VSSIO, VSSCORE INT_N USB_D+1 USB_D-1 VDD USB_UP_LED1 LPC408x/7x R7 5V VDD IN USB_PPWR2 ENA LM3526-L OUTA FLAGA USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω D+ USB_D-2 33 Ω D15 kΩ 15 kΩ USB-A connector VSSIO, VSSCORE VDD USB_UP_LED2 R8 0
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD RSTOUT RESET_N OE_N/INT_N USB_TX_E1 USB_TX_DP1 DAT_VP USB_TX_DM1 SE0_VM RCV USB_RCV1 USB_RX_DP1 USB_RX_DM1 VP VBUS VM ID VDD ISP1302 LPC408x/7x ADR/PSW SPEED DP 33 Ω DM 33 Ω USB MINI-AB connector VSSIO, VSSCORE SUSPEND USB_SCL1 SCL SDA USB_SDA1 INT_N USB_INT1 VDD USB_UP_LED1 002aah270 Fig 37.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D-1 33 Ω D15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA OUTA 5V IN LPC408x/7x USB_PPWR2 LM3526-L ENB VDD OUTB FLAGB USB_OVRCR2 VBUS USB_PWRD2 USB_D+2 33 Ω USB_D-2 33 Ω D+ USB-A connector D15 kΩ VSSIO, 15 kΩ VSSCORE VDD USB_UP_LED2 002aah271 Fig 38.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD USB_UP_LED1 VSSIO, VSSCORE USB_D+1 33 Ω D+ USB_D-1 33 Ω D15 kΩ USB-A connector 15 kΩ VDD VBUS USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA ENA 5V IN LM3526-L OUTA LPC408x/7x VDD USB_UP_LED2 VDD USB_CONNECT2 VSSIO, VSSCORE USB_D+2 33 Ω D+ USB_D-2 33 Ω D- VBUS USB-B connector VBUS 002aah272 Fig 39. USB device port configuration: port 1 host and port 2 device 13.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 40), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 41 and in Table 34 and Table 35.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 35. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF 20 pF < 100 39 pF, 39 pF 10 pF < 160 18 pF, 18 pF 20 pF < 80 39 pF, 39 pF 20 MHz to 25 MHz 13.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller VDD VDD open-drain enable pin configured as digital output driver strong pull-up output enable ESD data output PIN strong pull-down ESD VSS VDD weak pull-up pull-up enable pin configured as digital input weak pull-down repeater mode enable pull-down enable data input select analog input pin configured as analog input analog input 002aaf272 Fig 42. Standard I/O pin configuration with analog input 13.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller To eliminate the loss of time counts in the RTC due to voltage swing or ramp rate of the RESET signal, connect an RC filter between the RESET pin and the external reset input. 10 kΩ RESET pin 0.1 μF External RESET input 002aag552 Fig 44. Reset input with RC filter LPC408X_7X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 1 September 2014 © NXP Semiconductors N.V. 2014.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 14. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 105 156 157 104 ZE e E HE (A 3) A A2 A1 wM θ Lp bp L detail X pin 1 index 208 53 1 52 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller TFBGA180: thin fine-pitch ball grid array package; 180 balls SOT570-3 A B D ball A1 index area E A2 A A1 detail X e1 e 1/2 e ∅v ∅w b M M C C A B C y y1 C P N M L K J H G F E D C B A ball A1 index area e e2 1/2 e 1 2 3 4 5 6 7 8 9 10 11 12 13 X 14 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A A1 A2 b D E e e1 e2 v w y y1 1.20 1.06 0.95 0.40 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 73 72 108 109 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.9 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M θ bp Lp pin 1 index L 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 80 21 detail X 20 1 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 12.1 11.9 0.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller TFBGA80: plastic thin fine-pitch ball grid array package; 80 balls A B D SOT1328-1 ball A1 index area A A2 E A1 detail X e1 C e 1/2 e C A B C Øv Øw b y y1 C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 A2 b max 1.15 0.35 0.80 0.45 nom 1.00 0.30 0.70 0.40 min 0.90 0.25 0.65 0.35 D E 7.1 7.0 6.9 7.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 15. Soldering Footprint information for reflow soldering of LQFP208 package SOT459-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 31.300 31.300 28.300 28.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 28.500 28.500 31.550 31.550 sot459-1_fr Fig 52.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Footprint information for reflow soldering of TFBGA180 package SOT570-3 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 0.80 0.400 0.400 0.550 Hx Hy 12.575 12.575 sot570-3_fr Fig 53.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 23.300 23.300 20.300 20.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 20.500 20.500 23.550 23.550 sot486-1_fr Fig 54.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Footprint information for reflow soldering of LQFP100 package SOT407-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 17.300 17.300 14.300 14.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 14.500 14.500 17.550 17.550 sot407-1 Fig 55.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Footprint information for reflow soldering of LQFP80 package SOT315-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 15.300 15.300 12.300 12.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 12.500 12.500 15.550 15.550 sot315-1_fr Fig 56.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 16. Abbreviations Table 36.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 17. References LPC408X_7X Product data sheet [1] LPC408x/7x User manual UM10562: http://www.nxp.com/documents/user_manual/UM10562.pdf [2] LPC407x/8x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC407X_8X.pdf [3] Technical note ADC design guidelines: http://www.nxp.com/documents/technical_note/TN00009.pdf All information provided in this document is subject to legal disclaimers. Rev. 3.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 18. Revision history Table 37. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC408X_7X v.3.1 20140901 Product data sheet CIN 201404014I LPC408X_7X v.3 Modifications: LPC408X_7X v.3 Modifications: • • • SPIFI timing diagram corrected and specified for mode 0. See Table 27. • • • ADC conversion rate in burst mode added to Table 28 “12-bit ADC characteristics”.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Table 37. Revision history …continued Document ID Release date • • Data sheet status Change notice Supersedes Added LQFP100 and TFBGA80. Table 3: – Removed overbar from NMI. – Added minimum reset pulse width of 50 ns to RESET pin. – Updated Table note 14 for RTCX pins (32 kHz crystal must be used to operate RTC). – Added boundary scan information to description for RESET pin.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 8 6.1 Pinning . . .
LPC408x/7x NXP Semiconductors 32-bit ARM Cortex-M4 microcontroller 7.37.4 7.37.5 7.37.6 7.37.7 7.38 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 12 12.1 12.2 12.3 13 13.1 13.2 13.3 13.4 13.5 13.6 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 79 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 79 External interrupt inputs . . . . . . . . . . . . . . . . . 79 Memory mapping control . . . . . . . .