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Freescale Semiconductor

Technical Data

Document Number: MC56F8006

Rev. 4, 06/2011

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

MC56F8006/MC56F8002

48-pin LQFP

Case: 932-03

7 x 7 mm

28-pin SOIC

Case: 751F-05

7.5 x 18 mm

32-pin LQFP

Case: 873A-03

7 x 7 mm

32-pin PSDIP

Case: 1376-02

9 x 28.5 mm

This document applies to parts marked with 2M53M.

The 56F8006/56F8002 is a member of the 56800E core-based

family of digital signal controllers (DSCs). It combines, on a

single chip, the processing power of a DSP and the

functionality of a microcontroller with a flexible set of

peripherals to create a cost-effective solution. Because of its

low cost, configuration flexibility, and compact program

code, the 56F8006/56F8002 is well-suited for many

applications. It includes many peripherals that are especially

useful for cost-sensitive applications, including:

• Industrial control

• Home appliances

• Smart sensors

• Fire and security systems

• Switched-mode power supply and power management

•Power metering

• Motor control (ACIM, BLDC, PMSM, SR, and stepper)

• Handheld power tools

• Arc detection

• Medical device/equipment

• Instrumentation

• Lighting ballast

The 56800E core is based on a dual Harvard-style architecture

consisting of three execution units operating in parallel, allowing

as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow

straightforward generation of efficient, compact DSP and control

code. The instruction set is also highly efficient for C compilers

to enable rapid development of optimized control applications.

The 56F8006/56F8002 supports program execution from internal

memories. Two data operands can be accessed from the on-chip

data RAM per instruction cycle. The 56F8006/56F8002 also

offers up to 40 general-purpose input/output (GPIO) lines,

depending on peripheral configuration.

The 56F8006/56F8002 digital signal controller includes up to

16 KB of program flash and 2 KB of unified data/program

RAM. Program flash memory can be independently bulk

erased or erased in small pages of 512 bytes (256 words).

On-chip features include:

• Up to 32 MIPS at 32 MHz core frequency

• DSP and MCU functionality in a unified, C-efficient

architecture

• On-chip memory

– 56F8006: 16 KB (8K x 16) flash memory

– 56F8002: 12 KB (6K x 16) flash memory

– 2 KB (1K x 16) unified data/program RAM

• One 6-channel PWM module

• Two 28-channel, 12-bit analog-to-digital converters

(ADCs)

• Two programmable gain amplifiers (PGA) with gain up to

32x

• Three analog comparators

• One programmable interval timer (PIT)

• One high-speed serial communication interface (SCI) with

LIN slave functionality

• One serial peripheral interface (SPI)

• One 16-bit dual timer (2 x 16 bit timers)

• One programmable delay block (PDB)

• One SMBus compatible inter-integrated circuit (I

C) port

• One real time counter (RTC)

• Computer operating properly (COP)/watchdog

• Two on-chip relaxation oscillators — 1 kHz and 8 MHz

(400 kHz at standby mode)

• Crystal oscillator

• Integrated power-on reset (POR) and low-voltage interrupt

(LVI) module

• JTAG/enhanced on-chip emulation (OnCE™) for

unobtrusive, real-time debugging

• Up to 40 GPIO lines

• 28-pin SOIC, 32-pin LQFP, 32-pin PSDIP, and 48-pin

LQFP packages

MC56F8006/MC56F8002

Digital Signal Controller

Summary of content (106 pages)

PAGE 1
Freescale Semiconductor Technical Data Document Number: MC56F8006 Rev. 4, 06/2011 MC56F8006/MC56F8002 48-pin LQFP Case: 932-03 7 x 7 mm2 MC56F8006/MC56F8002 Digital Signal Controller This document applies to parts marked with 2M53M. The 56F8006/56F8002 is a member of the 56800E core-based family of digital signal controllers (DSCs).
PAGE 2
Table of Contents 1 2 3 4 5 6 7 8 MC56F8006/MC56F8002 Family Configuration . . . . . . . . . . . .3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.1 56F8006/56F8002 Features . . . . . . . . . . . . . . . . . . . . . .4 3.2 Award-Winning Development Environment. . . . . . . . . . .8 3.3 Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . .9 3.
PAGE 3
MC56F8006/MC56F8002 Family Configuration 1 MC56F8006/MC56F8002 Family Configuration MC56F8006/MC56F8002 device comparison in Table 1. Table 1.
PAGE 4
Block Diagram 2 Block Diagram Figure 1 shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this family are described later in this document. Italics indicate a 56F8002 device parameter. RESET 4 PWM 6 JTAG/EOnCE Port or GPIOD PWM Outputs Program Controller and Hardware Looping Unit programmable delay block 24 Total VSS 3 Digital Reg ADCA PGA/ADC R/W Control 2 Note: All pins are muxed with other peripheral pins.
PAGE 5
Overview • • • • • • • • • 3.1.2 • • • 3.1.3 • • • • 3.1.4 • • • • • • 3.1.
PAGE 6
Overview — — — — — — — • • • • • Four programmable fault inputs with programmable digital filter Double-buffered PWM registers Separate deadtime insertions for rising and falling edges Separate top and bottom pulse-width correction by means of software Asymmetric PWM output within both Center Aligned and Edge Aligned operation Separate top and bottom polarity control Each complementary PWM signal pair allows selection of a PWM supply source from: – PWM generator – Internal timers – Analog comparator
PAGE 7
Overview • • • • • • • — 1/16 bit-time noise detection One serial peripheral interface (SPI) — Full-duplex operation — Master and slave modes — Programmable length transactions (2 to 16 bits) — Programmable transmit and receive shift order (MSB as first or last bit transmitted) — Maximum slave module frequency = module clock frequency/2 One inter-integrated Circuit (I2C) port — Operates up to 400 kbps — Supports master and slave operation — Supports 10-bit address mode and broadcasting mode — Suppor
PAGE 8
Overview • • • • 3.1.6 • • • • • 3.
PAGE 9
Overview 3.3 Architecture Block Diagram The 56F8006/56F8002’s architecture is shown in Figure 2 and Figure 3. Figure 2 illustrates how the 56800E system buses communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core. Figure 3 shows the peripherals and control blocks connected to the IPBus bridge.
PAGE 10
Overview IPBus Bridge Port A Port B OCCS GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2 GPIOB1 GPIOB0 Port C Crystal COSC ROSC GPIOC7 GPIOC6 GPIOC5 GPIOC4 GPIOC3 GPIOC2 GPIOC1 GPIOC0 Port D COP Second Clcok source System Clock GPIOA7 GPIOA6 GPIOA5 GPIOA4 GPIOA3 GPIOA2 GPIOA1 GPIOA0 GPIOD3 GPIOD2 GPIOD1 GPIOD0 Port E RTC GPIOE7 GPIOE6 GPIOE5 GPIOE4 GPIOE3 GPIOE2 GPIOE1 GPIOE0 RESTE SIM PMC 1KHz INTC SPI SCI Dual Timer (TMR) PWM PWM Synch PWM Input Mux CMP0 GPIO MUX I2C CMP1 CMP2 PDB Trigge
PAGE 11
Signal/Connection Descriptions 3.4 Product Documentation The documents listed in Table 2 are required for a complete description and proper design with the 56F8006/56F8002. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table 2.
PAGE 12
Signal/Connection Descriptions In Table 4, peripheral pins in bold identify reset state. Table 4.
PAGE 13
Signal/Connection Descriptions Table 4.
PAGE 14
Signal/Connection Descriptions ANB6 & PGA1– & CMP0_P4/GPIOC5 1 28 ANB8 & PGA1+ & CMP0_M2/GPIOC4 ANB4 & CMP1_P1/GPIOC6/PWM2 2 27 GPIOB1/SS/SDA/ANA12 & CMP2_P3 VDDA 3 26 GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN VSSA 4 25 TDO/GPIOD1/ANB10/T0/CMP2_OUT ANA9 & PGA0– & CMP2_P4/GPIOC2 5 24 TMS/GPIOD3/ANB11/T1/CMP1_OUT ANA7 & PGA0+ & CMP2_M2/GPIOC1 6 23 TDI/GPIOD0/ANB12/SS/TIN2/CMP0_OUT ANA5 and CMP1_M1/GPIOC0/FAULT0 7 22 GPIOA0/PWM0 VSS 8 21 GPIOA1/PWM1 TCK/GPIOD2/ANA4 & CMP1_P2/CMP2_OU
PAGE 15
GPIOA0/PWM0 GPIOA1/PWM1 VSS VDD GPIOF0/XTAL 28 27 26 25 GPIOB5/T1/FAULT3/SCLK 29 3 TDI/GPIOD0/ANB12/SS/TIN2/CMP0_OUT GPIOB7/TXD/SCL/ANA11 & CMP2_M3 30 2 TMS/GPIOD3/ANB11/T1/CMP1_OUT GPIOB1/SS/SDA/ANA12 & CMP2_P3 31 1 TDO/GPIOD1/ANB10/T0/CMP2_OUT GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN 32 Signal/Connection Descriptions 24 GPIOA3/PWM3/TXD/EXTAL 23 GPIOA2/PWM2 22 GPIOA4/PWM4/SDA/FAULT1/TIN2 4 21 GPIOB0/SCLK/SCL/ANB13/PWM3/T1 ANB8 and PGA1+ & CMP0_M2/GPIOC4 5 20 GPIOA5/PWM5/FAULT
PAGE 16
Signal/Connection Descriptions !." AND 0'! #-0 ?- '0)/# '0)/" 4 &!5,4 3#,+ !." AND 0'! n #-0 ?0 '0)/# '0)/" 48$ 3#, !.! #-0 ?- !." #-0 ?0 '0)/# 07- '0)/" 33 3$! !.! #-0 ?0 6$$! '0)/" 28$ 3$! !.! #-0 ?0 #,+). 633! 4$/ '0)/$ !." 4 #-0 ?/54 !.! 0'! n #-0 ?0 '0)/# 4-3 '0)/$ !." 4 #-0 ?/54 !.! 0'! #-0 ?- '0)/# 4$) '0)/$ !." 33 4). #-0 ?/54 !.
PAGE 17
GPIOF1/CMP1_P3 VSS VDD GPIOF0/XTAL 40 39 38 37 GPIOF3/CMP0_P3 GPIOF2/CMP0_M3 41 43 42 GPIOA0/PWM0 GPIOA1/PWM1 44 GPIOC3/EXT_TRIGGER TDI/GPIOD0/ANB12/SS/TIN2/CMP0_OUT 45 TMS/GPIOD3/ANB11/T1/CMP1_OUT 47 46 TDO/GPIOD1/ANB10/T0/CMP2_OUT 48 Signal/Connection Descriptions GPIOB6/RXD/SDA/ANA13 & CMP0_P2/CLKIN 1 36 GPIOA3/PWM3/TXD/EXTAL GPIOB1/SS/SDA/ANA12 & CMP2_P3 2 35 GPIOA2/PWM2 GPIOB7/TXD/SCL/ANA11 & CMP2_M3 3 34 GPIOE7/CMP1_M3 GPIOB5/T1/FAULT3/SCLK 4 33 GPIOA4/PWM4/SDA/FAUL
PAGE 18
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information Signal Name 32 28 32 48 PSDI SOIC LQFP LQFP P VDD 21 VDD 31 Type State During Reset Signal Description Supply Supply I/O Power — This pin supplies 3.3 V power to the chip I/O interface. Supply Supply I/O Ground — These pins provide ground for chip I/O interface. VDD 19 26 22 38 VSS 8 13 9 20 VSS 20 27 23 39 VDDA 3 8 4 12 Supply Supply Analog Power — This pin supplies 3.
PAGE 19
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name GPIOA3 32 28 32 48 PSDI SOIC LQFP LQFP P 17 24 20 36 Type Input/ Output State During Reset Signal Description Input, Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled PWM3 — The PWM channel 3. (PWM3) Output (TXD) Output TXD — The SCI transmit data output or transmit/receive in single wire operation.
PAGE 20
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name GPIOA6 32 28 32 48 PSDI SOIC LQFP LQFP P 12 18 14 26 Type Input/ Output (FAULT0) Input (ANA1 & ANB1) Analog Input (SCL) Input/Opendrain Output (TXD) Output (CLKO_1) Output State During Reset Signal Description Input, Port A GPIO — This GPIO pin can be individually programmed as internal an input or output pin.
PAGE 21
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name GPIOB1 32 28 32 48 PSDI SOIC LQFP LQFP P 27 2 30 2 Type Input/ Output (SS) Input/ Output (SDA) Input/Opendrain Output (ANA12 and CMP2_P3) Analog input State During Reset Signal Description Input, Port B GPIO — This GPIO pin can be individually programmed as internal an input or output pin.
PAGE 22
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name GPIOB3 32 28 32 48 PSDI SOIC LQFP LQFP P 11 16 12 24 Type Input/ Output (MOSI) Input/ Output (TIN3) Input/ Output (ANA3 and ANB3) Input (PWM5) Output (CMP1_ OUT Output State During Reset Signal Description Input, Port B GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled MOSI — Master out/slave in.
PAGE 23
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name 32 28 32 48 PSDI SOIC LQFP LQFP P 4 GPIOB5 32 4 Type Input/ Output State During Reset Signal Description Input, Port B GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled T1 — Dual timer module channel 1 input/output.
PAGE 24
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name ANA5 and CMP1_M1 32 28 32 48 PSDI SOIC LQFP LQFP P 7 12 8 19 Type State During Reset Analog Input Analog Input Signal Description ANA5 and CMP1_M1— Analog input to channel 5 of ADCA and negative input 1 of analog comparator 1. (GPIOC0) Analog Input Port C GPIO — This GPIO pin can be individually programmed as an input or output pin.
PAGE 25
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name ANB8 and PGA1+ and CMP0_M2 32 28 32 48 PSDI SOIC LQFP LQFP P 28 5 1 7 (GPIOC4) Type State During Reset Analog Input Analog Input Input/ Output Signal Description ANB8 and PGA1+ and CMP0_M2 — Analog input to channel 8 of ADCB and PGA1 positive input and negative input 2 of analog comparator 0. Port C GPIO — This GPIO pin can be individually programmed as an input or output pin.
PAGE 26
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name TDI 32 28 32 48 PSDI SOIC LQFP LQFP P 23 30 26 45 Type Input State During Reset Signal Description Input, Test Data Input — This input pin provides a serial input data stream internal to the JTAG/EOnCE port. It is sampled on the rising edge of TCK pullup and has an on-chip pullup resistor. enabled Port D GPIO — This GPIO pin can be individually programmed as an input or output pin.
PAGE 27
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name TMS 32 28 32 48 PSDI SOIC LQFP LQFP P 24 31 27 47 Type Input State During Reset Signal Description Input, Test Mode Select Input — This input pin is used to sequence the internal JTAG TAP controller’s state machine. It is sampled on the rising pullup edge of TCK and has an on-chip pullup resistor. enabled Port D GPIO — This GPIO pin can be individually programmed as an input or output pin.
PAGE 28
Signal/Connection Descriptions Table 5. 56F8006/56F8002 Signal and Package Information (continued) Signal Name 32 28 32 48 PSDI SOIC LQFP LQFP P GPIOE5 16 (ANA8 and CMP2_P1) Type Input/ Output Analog Input State During Reset Signal Description Input, Port E GPIO — This GPIO pin can be individually programmed as internal an input or output pin. pullup enabled ANA8 and CMP2_P1— Analog input to channel 8 of ADCA and positive input 1 of analog comparator 2. After reset, the default state is GPIOE5.
PAGE 29
Memory Maps 5 Memory Maps 5.1 Introduction The 56F8006/56F8002 device is based on the 56800E core. It uses a dual Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM is shared by both data and program spaces and flash memory is used only in program space.
PAGE 30
Memory Maps Table 8. Program Memory Map1 for 56F8002 at Reset (continued) Begin/End Address 1 2 5.3 Memory Allocation P: 0x1F FFFF P: 0x00 8800 RESERVED P: 0x00 83FF P: 0x00 8000 On-Chip RAM2: 2 KB P: 0x00 7FFF P: 0x00 2000 RESERVED P: 0x00 1FFF P: 0x00 0800 • • • • P: 0x00 07FF P: 0x00 0000 RESERVED Internal program flash: 12 KB Interrupt vector table locates from 0x00 0800 to 0x00 0865 COP reset address = 0x00 0802 Boot location = 0x00 0800 All addresses are 16-bit word addresses.
PAGE 31
Memory Maps On-chip RAM is also mapped into program space starting at P: 0x00 8000. This makes for easier online reprogramming of on-chip flash. Program Data EOnCE Reserved 0xFF FF00 Reserved 0x00 8400 0x01 0000 RAM 0x00 8000 Peripherals Reserved 0x00 F000 Dual Port RAM Reserved 0x00 2000 0x00 0400 Flash RAM 0x00 0000 0x00 0000 Figure 8.
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Memory Maps Table 43 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. 5.5 Peripheral Memory-Mapped Registers The locations of on-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read or written using word accesses only.
PAGE 33
Memory Maps 5.6 EOnCE Memory Map Control registers of the EOnCE are located at the top of data memory space. These locations are fixed by the 56F800E core. These registers can also be accessed through JTAG port if flash security is not set. Table 11 lists all EOnCE registers necessary to access or control the EOnCE. Table 11.
PAGE 34
General System Control Information 6 General System Control Information 6.1 Overview This section discusses power pins, reset sources, interrupt sources, clock sources, the system integration module (SIM), ADC synchronization, and JTAG/EOnCE interfaces. 6.2 Power Pins VDD, VSS and VDDA, VSSA are the primary power supply pins for the devices. This voltage source supplies power to all on-chip peripherals, I/O buffer circuitry and to internal voltage regulators.
PAGE 35
General System Control Information • • • Provides a 3X system clock that operates at three times the system clock to PWM, timer, and SCI modules Safety shutdown feature is available if the PLL reference clock is lost Can be driven from an external clock source The clock generation module provides the programming interface for the PLL, internal relaxation oscillator, and crystal oscillator.
PAGE 36
General System Control Information 56F8002/56F8006 XTAL EXTAL Crystal Frequency = 32–38.4 kHz Figure 10. Typical Crystal Oscillator Circuit: Low-Range, Low-Power Mode 56F8002/56F8006 XTAL EXTAL Crystal Frequency = 1–16 MHz RF C2 C1 Figure 11. Typical Crystal or Ceramic Resonator Circuit: High-Range, Low-Power Mode 56F8002/56F8006 XTAL Low Range: Crystal Frequency = 32–38.4 kHz or High Range: Crystal Frequency = 1–16 MHz EXTAL RS RF C1 C2 Figure 12.
PAGE 37
General System Control Information 56F8006/56F8002 CLK_MOD = 1 XTAL EXTAL External Clock (<50 MHz) GND or GPIO Figure 13. Connecting an External Clock Signal Using XTAL 6.4.4 Alternate External Clock Input The recommended method of connecting an external clock is illustrated in Figure 14.
PAGE 38
General System Control Information • • • • • • • • • • • • • 6.
PAGE 39
Security Features Each ADC contains a temperature sensor. Outputs of temperature sensors, PGAs, on-chip regulators and VDDA are internally routed to ADC inputs. • • • • • • • • • • • • • 6.
PAGE 40
Security Features application software could communicate over a serial port, for example, to validate the authenticity of the requested access, then grant it until the next device reset. The inclusion of such a back door technique is at the discretion of the system designer. 7.
PAGE 41
Specifications 7.2.4 7.2.4.1 Flash Lockout Recovery without Mass Erase Without Presenting Back Door Access Keys to the Flash Unit A user can un-secure a secured device by programming the word 0x0000 into program flash location 0x00 1FF7. After completing the programming, the JTAG TAP controller and the device must be reset to return to normal unsecured operation.
PAGE 42
Specifications 8.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified Table 12 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section.
PAGE 43
Specifications A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 13.
PAGE 44
Specifications Table 15. 28SOIC Package Thermal Characteristics (continued) Characteristic Comments Symbol Value (LQFP) Unit Junction to ambient (@200 ft/min) Four layer board (2s2p) RJMA 42 °C/W Junction to board RJB 23 °C/W Junction to case RJC 26 °C/W JT 9 °C/W Junction to package top Natural Convection Table 16.
PAGE 45
Specifications Table 18.
PAGE 46
Specifications Table 19. Recommended Operating Conditions (VREFL x= 0 V, VSSA = 0 V, VSS = 0 V) 1 Characteristic Symbol Supply voltage Notes Min Typ Max Unit VDD, VDDA 3 3.3 3.6 V Voltage difference VDD to VDDA VDD –0.1 0 0.1 V Voltage difference VSS to VSSA VSS –0.1 0 0.1 V Device Clock Frequency Using relaxation oscillator Using external clock source FSYSCLK 1 0 32 32 MHz Input Voltage High (digital inputs) VIH Pin Groups 1, 2 2.
PAGE 47
Specifications Table 21. DC Characteristics Characteristic Symbol Condition Min Typ 1 1.
PAGE 48
Specifications Table 21. DC Characteristics (continued) Characteristic Low-voltage detection threshold — high range7 Low-voltage warning threshold Max Ambient temperature Unit operating range Symbol Condition Min Typ VLVDH8 VDD falling 2.31 2.34 2.36 2.16 2.3 2.48 —40 C ~ +125 C 2.38 2.44 2.47 –40 C ~ 105 C 2.23 2.39 2.49 —40 C ~ +125 C 1.8 1.84 1.87 N/A N/A N/A —40 C ~ +125 C VDD rising 1.88 1.93 1.96 –40 C ~ 105 C VDD falling 2.58 2.62 2.71 2.5 2.
PAGE 49
Specifications 8 Runs at 32 MHz bus frequency. Both Low Voltage Warning (LVW) and Out Of Regulation (OOR) sample the same input source. The OOR flag is a stick bit which is in the PMC_SCR register. 10 Factory trimmed at VDD = 3.3 V, Temp = 25 C. PULLDOWN RESISTANCE (kW) PULLUP RESISTOR (kW) 9 PULLUP RESISTOR TYPICALS 85C 25C –40C 40 35 30 25 20 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) 3.2 3.4 3.6 PULLDOWN RESISTOR TYPICALS 85C 25C –40C 40 35 30 25 20 1.8 2.3 2.8 VDD (V) 3.3 3.6 Figure 16.
PAGE 50
Specifications TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 85C 25C –40C 1 TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.25 VDD – VOH (V) VDD – VOH (V) 1.2 0.8 85C, IOH = 2 mA 25C, IOH = 2 mA –40C, IOH = 2 mA 0.2 0.15 0.6 0.4 0.1 0.05 0.2 0 0 0 –5 –10 IOH (mA)) –15 –20 1 2 3 VDD (V) 4 Figure 19. Typical High-Side (Source) Characteristics — Low Drive (GPIO_x_DRIVEn = 0) TYPICAL VDD – VOH VS VDD AT SPEC IOH TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 85C 25C –40C 0.8 0.6 0.4 0.
PAGE 51
Specifications 8.6 Supply Current Characteristics Table 22. Supply Current Consumption Mode Conditions Typical @ 3.3 V, 25 °C Maximum @ 3.6 V, 105 °C Maximum @ 3.6 V, 125 °C IDD1 IDDA IDD1 IDDA IDD1 IDDA 41.52 mA 1.71 mA 53 mA 2.7 mA 53 mA 2.9 mA LSrun 2 200 kHz device clock; 340.75 A 1.70 mA relaxation oscillator (ROSC) in standby mode; PLL disabled All peripheral modules disabled and clock gated off; simple loop with fetches from program flash; 480 A 2.5 mA 495 A 2.
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Specifications Table 22. Supply Current Consumption (continued) Mode Conditions Typical @ 3.3 V, 25 °C IDD1 LPwait 3 Stop 32.768 kHz device clock; Clocked by a 32.
PAGE 53
Specifications 8.7 Flash Memory Characteristics Table 23. Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 tprog 20 — 40 s terase 20 — — ms tme 100 — — ms Erase time 2 Mass erase time 1 There is additional overhead that is part of the programming sequence. See the MC56F8006 Peripheral Reference Manual for detail. 2 Specifies page erase time. There are 512 bytes per page in the program flash memory. 8.8 External Clock Operation Timing Table 24.
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Specifications 8.9 Phase Locked Loop Timing Table 25. Phase Locked Loop Timing Characteristic Symbol Min Typ Max Unit PLL input reference frequency1 fref 4 8 — MHz fop 120 192 — MHz tplls — 40 100 µs Accumulated jitter using an 8 MHz external crystal as the PLL source5 JA — — 0.
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MHz Specifications Degrees C (Junction) Figure 22. Relaxation Oscillator Temperature Variation (Typical) After Trim for devices with temperature operating range from –40 C to 105 C Figure 23. Relaxation Oscillator Temperature Variation (Typical) After Trim for devices with temperature operating range from –40 C to 125 C MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Specifications 8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing NOTE All address and data buses described here are internal. Table 27.
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Specifications Table 28. Crystal Oscillator Characteristics Characteristic Symbol Min Typ1 Max Unit flo fhi fhi 32 1 1 — — — 38.
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Specifications • • • Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH Data1 Valid Data2 Valid Data1 Data3 Valid Data2 Data3 Data Three-stated Data Invalid State Data Active Data Active Figure 26. Signal States 8.13.1 Serial Peripheral Interface (SPI) Timing Table 29.
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Specifications Table 29. SPI Timing1 (continued) 1 Characteristic Symbol Data valid for outputs Master Slave (after enable edge) tDV Data invalid Master Slave tDI Rise time Master Slave tR Fall time Master Slave tF Min Max Unit See Figure — — 4.5 20.4 ns ns Figure 27, Figure 28, Figure 29, Figure 30 0 0 — — ns ns Figure 27, Figure 28, Figure 29, Figure 30 — — 11.5 10.0 ns ns Figure 27, Figure 28, Figure 29, Figure 30 — — 9.7 9.
PAGE 60
Specifications SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in tDH Bits 14–1 tDI tDV(ref) MOSI (Output) LSB in tDV Master MSB out tDI(ref) Bits 14– 1 Master LSB out tF tR Figure 28.
PAGE 61
Specifications SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) Slave MSB out Bits 14–1 tDS Slave LSB out tDV tDI tDH MOSI (Input) tD tF MSB in Bits 14–1 LSB in Figure 30. SPI Slave Timing (CPHA = 1) 8.13.2 Serial Communication Interface (SCI) Timing Table 30. SCI Timing1 Characteristic Symbol Min Max Unit See Figure Baud rate2 BR — (fMAX/16) Mbps — RXD pulse width RXDPW 0.965/BR 1.
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Specifications RXD SCI receive data pin (Input) RXDPW Figure 31. RXD Pulse Width TXD SCI receive data pin (Input) TXDPW Figure 32. TXD Pulse Width 8.13.3 Inter-Integrated Circuit Interface (I2C) Timing Table 31. I2C Timing Standard Mode Characteristic Symbol Unit Minimum Maximum SCL Clock Frequency fSCL 0 100 MHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4.0 — s LOW period of the SCL clock tLOW 4.
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Specifications SDA tSU; DAT tf tf tr tLOW tHD; STA tr tSP tBUF SCL S tHD; STA tHD; DAT tSU; STA tHIGH tSU; STO SR P S 2 Figure 33. Timing Definition for Standard Mode Devices on the I C Bus 8.13.4 JTAG Timing Table 32.
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Specifications TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) Figure 35. Test Access Port Timing Diagram 8.13.5 Dual Timer Timing Table 33.
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Specifications 8.14 COP Specifications Table 34. COP Specifications Parameter Symbol Min Typ Max Unit Oscillator output frequency LPFosc 500 1000 1500 Hz Oscillator current consumption in partial power down mode IDD 8.15 TBD nA PGA Specifications Table 35.
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Specifications 8.16 ADC Specifications Table 36. ADC Operating Conditions Symb Min Typ1 Max Unit Input voltage VADIN VREFL2 — VREFH3 V Input capacitance CADIN — 4.5 5.5 pF Input resistance RADIN — 5 7 k — — — — 2 5 10-bit mode fADCK > 4 MHz fADCK < 4 MHz — — — — 5 10 8-bit mode (all valid fADCK) — — 10 0.4 — 8.0 0.4 — 4.
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Specifications Table 37. ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Symb Min Typ1 Max Unit Supply current ADLPC=1 ADLSMP=1 ADCO=1 IDDAD — 120 — A Supply current ADLPC=1 ADLSMP=0 ADCO=1 IDDAD — 202 — A Supply current ADLPC=0 ADLSMP=1 ADCO=1 IDDAD — 288 — A Supply current ADLPC=0 ADLSMP=0 ADCO=1 IDDAD — 0.532 1 mA fADACK 2 3.3 5 MHz 1.25 2 3.3 — 20 — — 40 — — 3.5 — — 23.5 — — 1.75 — — 0.5 1.0 — 0.3 0.5 — 1.5 — 10-bit mode — 0.
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Specifications 1 Typical values assume VDDA = 3.0 V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (VREFH – VREFL)/2N 3 Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals. 8.17 HSCMP Specifications Table 38. HSCMP Specifications Parameter Symbol Min Typ Max Unit Supply voltage VPWR 1.8 3.
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Specifications Power consumption is given by the following equation: Eqn. 1 Total power = A: internal [static component] +B: internal [state-dependent component] +C: internal [dynamic component] +D: external [dynamic component] +E: external [static component] A, the internal [static] component, is comprised of the DC bias currents for the oscillator, leakage currents, PLL, and voltage references. These sources operate independently of processor state or operating frequency.
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Design Considerations 9 Design Considerations 9.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJ x PD) Eqn. 3 where: TA = Ambient temperature for the package (oC) = Junction-to-ambient thermal resistance (oC/W) RJ = PD Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
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Design Considerations junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink.
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Design Considerations 9.3 Ordering Information Table 40 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order devices. Table 40.
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Package Mechanical Outline Drawings 10 Package Mechanical Outline Drawings 10.1 28-pin SOIC Package MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Package Mechanical Outline Drawings Figure 38. 56F8006/56F8002 28-Pin SOIC Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Package Mechanical Outline Drawings 10.2 32-pin LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Package Mechanical Outline Drawings Figure 39. 56F8006/56F8002 32-Pin LQFP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Package Mechanical Outline Drawings 10.3 48-pin LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Package Mechanical Outline Drawings Figure 40. 56F8006/56F8002 48-Pin LQFP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Package Mechanical Outline Drawings 10.4 32-Pin PSDIP MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Package Mechanical Outline Drawings Figure 41. 56F8006/56F8002 32-Pin PSDIP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Revision History 11 Revision History Table 41 lists major changes between versions of the MC56F8006 document. Table 41. Changes Between Revisions 2 and 3 Location Description Introduction on page 1 Added part marking for devices covered by this document Section 6.
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Interrupt Vector Table Table 43.
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Interrupt Vector Table Table 43.
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Freescale Semiconductor Appendix B Peripheral Register Memory Map and Reset Value NOTE In Table 44, ADC0 stands for ADCA, ADC1 stands for ADCB, and GPIOn is the same as GPIO_n (for example, GPIOA_PUR is the same as GPIO_A_PUR). Table 44.
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Register Bit 15 14 13 12 11 10 9 8 7 6 0A 0000 TMR0 TMR0_ CSCTRL DBG_EN ALT_LOAD 0 0 0 0 TCF2EN TCF1EN 0B 0000 TMR0 TMR0_ FILT 0 0 0 0 0C–0E — TMR0 Reserved 0F 000F TMR0 TMR_ ENBL 10 0000 TMR1 TMR1_ COMP1 COMPARISON_1 11 0000 TMR1 TMR1_ COMP2 COMPARISON_2 12 0000 TMR1 TMR1_ CAPT CAPTURE 13 0000 TMR1 TMR1_ LOAD LOAD 14 0000 TMR1 TMR1_ HOLD HOLD 15 0000 TMR1 TMR1_ CNTR COUNTER 16 0000 TMR1 TMR1_ CTRL 17 0000 TMR1 TMR1_ SCTRL 18 0000
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Register Bit 15 14 13 12 11 10 9 8 7 6 1A 0000 TMR1 TMR1_ CSCTRL DBG_EN FAULT ALT_LOAD 0 0 0 0 TCF2EN TCF1EN 1B 0000 TMR1 TMR1_ FILT 0 0 0 0 1C–1F — TMR1 Reserved 20 0000 PWM PWM_ CTRL 21 0000 PWM PWM_ FCTRL 22 0000 PWM 23 0000 24 0 5 4 3 TCF2 TCF1 FILT_CNT 2 Bit 0 1 CL2 CL1 FILT_PER Freescale Semiconductor 0 CR 25 0000 PWM PWM_ CMOD 0 PWMCM 26 0000 PWM PWM_ VAL0 PMVAL 27 0000 PWM PWM_ VAL1 PMVAL 28 0000 PWM PWM_ VAL2 PMVAL
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PWM PWM_ VAL3 PMVAL 2A 0000 PWM PWM_ VAL4 PMVAL 2B 0000 PWM PWM_ VAL5 PMVAL 2C 0FFF PWM PWM_ DTIM0 0 0 0 0 PWMDT0 2D 0FFF PWM PWM_ DTIM1 0 0 0 0 PWMDT1 2E FFFF PWM PWM_ DMAP1 2F 00FF PWM PWM_ DMAP2 0 0 0 0 0 0 0 0 30 0000 PWM PWM_ CNFG 0 EDG 0 TOPNEG23 31 0000 PWM PWM_ CCTRL nBX 32 00-U1 PWM PWM_ PORT 0 0 0 0 0 0 0 33 0000 PWM PWM_ ICCTRL 0 0 0 0 0 0 0 0 0 34 0000 PWM PWM_ SCTRL 0 0 CINV0 0 3 2 1 Bit 0 INDEP01 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 1 Bit 0 BKPT 0000 PWM PWM_ SYNC 36 0000 PWM PWM_ FFILT0 37 0000 PWM PWM_ FFILT1 38 0000 PWM PWM_ FFILT2 39 0000 PWM PWM_ FFILT3 3B–3F — PWM Reserved 40 0000 INTC INTC_ ICSR INT 41 0000 INTC INTC_ VBA 0 0 42 0000 INTC INTC_ IAR0 0 0 USER2 0 0 USER1 43 0000 INTC INTC_ IAR1 0 0 USER4 0 0 USER3 44 0000 INTC INTC_ IAR2 0 0 USER6 0 0 USER5 45–5F — INTC Reserved 60 001F ADC0 ADC0_ ADCSC1A SYN
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Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 61 0000 ADC0 ADC0_ ADCSC2 0 0 0 0 0 0 0 0 ADACT ADTRG 0 0 0 ECC 62–65 — ADC0 Reserved 66 0000 ADC0 ADC0_ ADCCFG 67–69 — ADC0 Reserved 6A 001F ADC0 ADC0_ ADCSC1B 0 6B 0000 ADC0 ADC0_ ADCRA 0 6C 0000 ADC0 ADC0_ ADCRB 0 6D–6F — ADC0 Reserved 80 001F ADC1 ADC1_ ADCSC1A 0 0 0 0 0 0 0 0 81 0000 ADC1 ADC1_ ADCSC2 0 0 0 0 0 0 0 0 82–85 — ADC1 Reserved 86 0000 ADC1 ADC1_ ADCCF
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0 0 0 0 0 0 0 0 TM A1 0002 PGA0 PGA0_ CNTL1 0 0 0 0 0 0 0 0 PPDIS PARMODE 0 A2 000E PGA0 PGA0_ CNTL2 0 0 0 0 0 0 0 0 0 0 SWTRIG NUM_CLK_GS A3 0000 PGA0 PGA0_STS 0 0 0 0 0 0 0 0 0 0 0 0 A4–BF — PGA0 Reserved C0 0000 PGA1 PGA1_ CNTL0 0 0 0 0 0 0 0 0 TM C1 0002 PGA1 PGA1_ CNTL1 0 0 0 0 0 0 0 0 PPDIS PARMODE 0 C2 000E PGA1 PGA1_ CNTL2 0 0 0 0 0 0 0 0 0 0 SWTRIG ADR0 PGA0_ CNTL0 0 0 ADR0 PGA0 ADR1 0000
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14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E1 0000 SCI SCI_ CTRL1 E2 0000 SCI SCI_ CTRL2 E3 C000 SCI E4 0000 E5–FF SBR FRAC_SBR POL PE PT TEIE TIIE 0 0 0 0 0 0 0 OR NF FE PF 0 0 0 0 0 0 0 M 0 0 0 0 93 SWAI 0 0 SCI_STAT SCI SCI_DATA 0 — SCI Reserved 00 6141 SPI SPI_ SCTRL 01 000F SPI SPI_ DSCTRL WOM 0 02 0000 SPI SPI_DRCV R15 03 0000 SPI SPI_DXMIT T15 04–1F — SPI Reserved 20 0000 I2C I
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Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 22 0000 I2C I2C_CR1 0 0 0 0 0 0 0 0 IICEN IICIE MST TX 23 0080 I2C I2C_SR 0 0 0 0 0 0 0 0 TCF IAAS BUSY ARBL 24 0000 I2C I2C_DATA 0 0 0 0 0 0 0 0 25 0000 I2C I2C_CR2 0 0 0 0 0 0 0 0 26 0000 I2C I2C_SMB_ CSR 0 0 0 0 0 0 0 0 27 0000 I2C I2C_ ADDR2 0 0 0 0 0 0 0 0 28 0000 I2C I2C_SLT1 0 0 0 0 0 0 0 0 29 0000 I2C I2C_SLT2 0 0 0 0 0 0 0 0 30–3F — I2C R
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2000 OCCS OCCS_ DIVBY 62 0015 OCCS OCCS_ STAT LOLI1 64 1611 OCCS OCCS_ OCTRL 65 0000 OCCS OCCS_ CLKCHKR 66 0000 OCCS OCCS_ CLKCHKT 0 0 0 0 0 0 0 0 0 67 0000 OCCS OCCS_ PROT 0 0 0 0 0 0 0 0 0 68–7F — OCCS Reserved 80 00FF GPIOA GPIOA_ PUR 81 0000 GPIOA GPIOA_DR 82 0000 GPIOA 83 0080 84 — PLLIE0 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 PRECS 61 PLLIE1 11 0 0 0 0 0 0 0 COSC_RDY OCCS_ CTRL 12 PLLPD OCCS 13 PLLPDN 0011 14 LCKON
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Offset Addr. (Hex) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor Reset Value Periph.
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Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Offset Addr.
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Offset Addr. (Hex) Reset Value Periph. (Hex) Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 MC56F8006/MC56F8002 Digital Signal Controller, Rev.
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Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Offset Addr.
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Offset Addr. (Hex) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Reset Value Periph.
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14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 41 0001 SIM SIM_ RSTAT 0 0 0 0 0 0 0 0 0 SWR 42 01F2 SIM SIM_ MSHID SIM_MSH_ID 43 601D SIM SIM_ LSHID SIM_LSH_ID 45 2020 SIM SIM_ CLKOUT 46 0000 SIM SIM_PCR 47 0000 SIM SIM_PCE 48 0000 SIM SIM_SDR 49 F000 SIM SIM_ISAL 4A 0000 SIM SIM_PROT 0 0 0 0 0 0 0 4B 0000 SIM SIM_GPSA 0 0 0 0 0 0 0 4C 0000 SIM SIM_ GPSB0 GPS_B5 4D 0000 SIM SIM_ GPSB1 0 0 0 CMP1 CMP1 0 0 0 0 0 0 0 0 0
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13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0000 SIM SIM_GPSC 0 0 0 0 0 0 0 0 4F 0000 SIM SIM_GPSD 0 0 0 0 0 0 0 GPS_D3 50 0000 SIM SIM_IPS0 0 0 0 0 51 0000 SIM SIM_IPS1 0 52–5F — SIM Reserved 60 0208 PMC PMC_SCR 61 00--2 PMC PMC_CR2 7F — PMC Reserved 80 0000 CMP0 CMP0_ CR0 0 0 0 0 0 0 0 0 0 81 0000 CMP0 CMP0_ CR1 0 0 0 0 0 0 0 0 SE 82 0000 CMP0 CMP0_ FPR 0 0 0 0 0 0 0 0 83 0000 CMP0 CMP0_ SCR 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 SE WE 0 PMODE INV COS OPE EN CFR CFF A1 0000 CMP1 CMP1_ CR1 0 0 0 0 0 0 0 0 A2 0000 CMP1 CMP1_ FPR 0 0 0 0 0 0 0 0 A3 0000 CMP1 CMP1_ SCR 0 0 0 0 0 0 0 0 A4–BF — CMP1 Reserved C0 0000 CMP2 CMP2_ CR0 0 0 0 0 0 0 0 0 0 C1 0000 CMP2 CMP2_ CR1 0 0 0 0 0 0 0 0 SE C2 0000 CMP2 CMP2_ FPR 0 0 0 0 0 0 0 0 C3 0000 CMP2 CMP2_ SCR 0 0 0 0 0 0 0 0 C4–DF — CMP
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Register 02 0000 PDB PDB_ DELAYB DELAYB 03 FFFF PDB PDB_MOD MOD 04 FFFF PDB PDB_ COUNT COUNT 05–1F — PDB Reserved RESERVED 20 0000 RTC RTC_SC 0 0 0 0 0 0 0 0 21 0000 RTC RTC_CNT 0 0 0 0 0 0 0 0 RTCCNT 22 0000 RTC RTC_MOD 0 0 0 0 0 0 0 0 RTCMOD 23–FF — RTC Reserved 00 0000 HFM FM_ CLKDIV 0 0 0 0 0 0 0 0 01 0000 HFM FM_CNFG 0 0 0 0 0 LOCK 0 AEIE 03 -0003 HFM FM_SECHI SECSTAT 0 0 0 0 0 0 04 0000 HFM FM_ SECLO
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Freescale Semiconductor Table 44. Detailed Peripheral Memory Map (continued) Offset Addr.
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