Freescale Semiconductor Technical Data Document Number: MC56F825X Rev. 3, 04/2011 MC56F825x/MC56F824x 44-pin LQFP Case: 10 x 10 mm2 MC56F825x/MC56F824x Digital Signal Controller The MC56F825x/MC56F824x is a member of the 56800E core-based family of digital signal controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create a cost-effective solution.
Table of Contents 1 2 3 4 5 6 7 MC56F825x/MC56F824x Family Configuration . . . . . . . . . . . .3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 MC56F825x/MC56F824x Features. . . . . . . . . . . . . . . . .4 2.2 Award-Winning Development Environment. . . . . . . . . . .8 2.3 Architecture Block Diagram. . . . . . . . . . . . . . . . . . . . . . .8 2.4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . .
MC56F825x/MC56F824x Family Configuration 1 MC56F825x/MC56F824x Family Configuration Table 1 compares the MC56F825x/MC56F824x devices. Table 1. MC56F825x/MC56F824x Device Comparison Feature 56F8245 56F8246 56F8247 56F8255 56F8256 56F8257 Operation Frequency (MHz) 60 High Speed Peripheral Clock (MHz) 120 Flash memory size (KB) with 1024 words per page 48 48 48 64 64 64 RAM size (KB) 6 6 8 8 8 8 Enhanced High resolution NanoEdge PWM (520 ps res.
Overview 2 Overview 2.1 MC56F825x/MC56F824x Features 2.1.1 • • • • • • • • • • • • • • 2.1.2 • • • 2.1.3 • • • • • • 2.1.
Overview • • • • — Lowest-priority software interrupt: level LP Nested interrupts: higher priority level interrupt request can interrupt lower priority interrupt subroutine Two programmable fast interrupts that can be assigned to any interrupt source Notification to system integration module (SIM) to restart clock out of wait and stop states Ability to relocate interrupt vector table The masking of interrupt priority level is managed by the 56800E core. 2.1.
Overview • • • • • • — Maximum ADC clock frequency: up to 10 MHz – Single conversion time of 8.5 ADC clock cycles (8.
Overview • • • • • • • — Maximum slave module frequency = module clock frequency/2 — 13-bit baud rate divider for low speed communication Two inter-integrated circuit (I2C) ports — Operation at up to 100 kbps — Support for master and slave operation — Support for 10-bit address mode and broadcasting mode — Support for SMBus, Version 2 One Freescale Scalable Controller Area Network (MSCAN) module — Fully compliant with CAN protocol Version 2.
Overview • • 2.1.6 • • • • 2.
Overview DSP56800E Core Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) Instruction Decoder Interrupt Unit ALU1 ALU2 R0 R1 R2 R3 R4 R5 N SP M01 N3 Looping Unit Program Memory XAB1 XAB2 PAB PDB Data/ Program RAM CDBW CDBR XDB2 A2 B2 C2 D2 BitManipulation Unit Enhanced OnCE™ JTAG TAP Y A1 B1 C1 D1 Y1 Y0 X0 MAC and ALU A0 B0 C0 D0 IP Bus Interface Data Arithmetic Logic Unit (ALU) Multi-Bit Shifter Figure 1.
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Signal/Connection Descriptions 2.4 Product Documentation The documents listed in Table 2 are required for a complete description and proper design with the MC56F825x/MC56F824x. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table 2.
Signal/Connection Descriptions 1 2 Pins may be shared with other peripherals. See Table 4. Exclude MC56F824x. Table 4 summarizes all device pins. Each table row describes the signal or signals present on a pin, sorted by pin number. Peripheral pins in bold identify reset state. Table 4. MC56F825x/MC56F824x Pins Pin Number Peripherals 48 64 44 LQFP LQFP LQFP Pin Name GPIO I2C SCI SPI MS CAN1 ADC Cross Bar COMP Quad Timer eFlex PWM Power JTAG Misc.
Signal/Connection Descriptions Table 4. MC56F825x/MC56F824x Pins (continued) Pin Number 48 64 44 LQFP LQFP LQFP Peripherals Pin Name GPIO I2C SCI SPI MS CAN1 ADC Cross Bar ANB3& VREFLB GPIOB3 COMP Quad Timer eFlex PWM Power JTAG Misc.
Signal/Connection Descriptions Table 4. MC56F825x/MC56F824x Pins (continued) Pin Number 48 64 44 LQFP LQFP LQFP 1 Peripherals Pin Name GPIO 41 45 61 VSS I2C SCI SPI MS CAN1 ADC Cross Bar COMP Quad Timer eFlex PWM Power JTAG Misc. VSS 42 46 62 TDO/GPIOD1 GPIOD1 TDO 43 47 63 TMS/GPIOD3 GIPOD3 TMS 44 48 64 TDI/GPIOD0 GPIOD0 TDI The MSCAN module is not available on the MC56F824x devices. MC56F825x/MC56F824x Digital Signal Controller, Rev.
Signal/Connection Descriptions 3.2 Pin Assignment Figure 3 shows the pin assignments of the 56F8245 and 56F8255’s 44-pin low-profile quad flat pack (44LQFP). Figure 4 shows the pin assignments of the 56F8246 and 56F8256’s 48-pin low-profile quad flat pack (48LQFP). Figure 5 shows the pin assignments of the 56F8247 and 56F8257’s 64-pin low-profile quad flat pack (64LQFP).
13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 GPIOE3/PWM1A GPIOE2/PWM1B GPIOE1/PWM0A GPIOE0/PWM0B VDD VSS GPIOC12/CANRX0/SDA1/RXD1 GPIOC11/CANTX0/SCL1/TXD1 GPIOF0/XB_IN6 GPIOC10/MOSI/XB_IN5/MISO GPIOC9/SCLK/XB_IN4 GPIOC8/MISO/RXD0 GPIOC5/DACO/XB_IN7 GPIOB4/ANB4/CMPC_M1 VDDA VSSA GPIOB0/ANB0/CMPB_P2 GPIOB1/ANB1/CMPB_M0 VCAP GPIOB2/ANB2/VREFHB/CMPC_P2 GPIOB3/ANB3/VREFLB/CMPC_M0 VSS GPIOC6/TA2/XB_IN3/CMP_REF GPIOC7/SS/TXD0 GPIOD2/TCK GPIOD4/RESET GPIOC0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GPIOE3/PWM1A GPIOE2/PWM1B GPIOE1/PWM0A GPIOE0/PWM0B VDD VSS GPIOF5/RXD1/XB_OUT5 GPIOF4/TXD1/XB_OUT4 GPIOF3/SDA1/XB_OUT3 GPIOF2/SCL1/XB_OUT2 GPIOC12/CANRX/SDA1/RXD1 GPIOC11/CANTX/SCL1/TXD1 GPIOF0/XB_IN6 GPIOC10/MOSI/XB_IN5/MISO GPIOC9/SCLK/XB_IN4 GPIOC8/MISO/RXD0 GPIOB7/ANB7/CMPB_M2 GPIOC5/DACO/XB_IN7 GPIOB6/ANB6/CMPB_M1 GPIOB5/ANB5/CMPC_M2 GPIOB4/ANB4/CMPC_M1 VDDA VSSA GPIOB0/ANB0/CMPB_P2 GPIOB1/ANB1/CMPB_M0 VCAP GPIOB
Signal/Connection Descriptions 3.3 MC56F825x/MC56F824x Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternative functionality, shown in parentheses and as italic, must be programmed via the GPIO module’s peripheral enable registers (GPIO_x_PER) and the SIM module’s GPIO peripheral select (GPSx) registers. Table 5.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name TMS 44 48 64 LQFP LQFP LQFP 43 47 63 (GPIOD3) Type input State During Reset Input, internal pullup enabled Input/ Output Signal Description Test Mode Select Input — This input pin is used to sequence the JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pullup resistor.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name GPIOA2 44 48 64 LQFP LQFP LQFP 10 11 15 (ANA2& VREFHA& CMPA_M1) Type Input/ Output Input State During Reset Input, internal pullup enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. ANA2 and VREFHA and CMPA_M1 — Analog input to channel 2 of ADCA and analog references high of ADCA and negative input 1 of analog comparator A.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name GPIOB0 44 48 64 LQFP LQFP LQFP 15 17 24 (ANB0& CMPB_P2) Type Input/ Output Input State During Reset Input, internal pullup enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB0 and CMPB_P2 — Analog input to channel 0 of ADCB and positive input 2 of analog comparator B.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name 44 48 64 LQFP LQFP LQFP GPIOB4 14 21 (ANB4& CMPC_M1) Type Input/ Output Input State During Reset Input, internal pullup enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB4 and CMPC_M1 — Analog input to channel 4 of ADCB and negative input 1 of analog comparator C. After reset, the default state is GPIOB4.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name GPIOC2 44 48 64 LQFP LQFP LQFP 5 5 5 Type Input/ Output (TXD0) Output (TB0) Input/ Output (XB_IN2) Input (CLKO) Output State During Reset Input, internal pullup enabled Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. TXD0 — The SCI0 transmit data output or transmit/receive in single wire operation.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name GPIOC6 44 48 64 LQFP LQFP LQFP 21 23 31 Type Input/ Output (TA2) Input/ Output (XB_IN3) Input (CMP_REF) Analog Input State During Reset Input, internal pullup enabled Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name GPIOC10 44 48 64 LQFP LQFP LQFP 25 27 35 Type Input/ Output (MOSI) Input/ Output (XB_IN5) Input (MISO) Input/ Output State During Reset Input, internal pullup enabled Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. MOSI — Master out/slave in. In master mode, this pin serves as the data output.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name GPIOC14 44 48 64 LQFP LQFP LQFP 37 41 55 Type Input/ Output (SDA0) Input/ Open-drain Output (XB_OUT0) Input State During Reset Input, internal pullup enabled Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. SDA0 — I2C0 serial data line XB_OUT0 — Crossbar module output 0 After reset, the default state is GPIOC14.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name GPIOE4 44 48 64 LQFP LQFP LQFP 35 39 51 Type Input/ Output (PWM2B) Output (XB_IN2) Input State During Reset Input, internal pullup enabled Signal Description Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM2B — NanoEdge PWM submodule 2 output B XB_IN2 — Crossbar module input 2 After reset, the default state is GPIOE4.
Signal/Connection Descriptions Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name 44 48 64 LQFP LQFP LQFP GPIOF1 38 50 Type Input/ Output (CLKO) Output (XB_IN7) Input State During Reset Input, internal pullup enabled Signal Description Port F GPIO — This GPIO pin can be individually programmed as an input or output pin.
Memory Maps Table 5. MC56F825x/MC56F824x Signal and Package Information (continued) Signal Name 44 48 64 LQFP LQFP LQFP GPIOF6 58 Type Input/ Output (TB2) Input/ Output (PWM3X) Input/ Output State During Reset Input, internal pullup enabled Signal Description Port F GPIO — This GPIO pin can be individually programmed as an input or output pin. TB2 — Quad timer module B channel 2 input/output. PWM3X — Enhanced PWM submodule 3 output X or input capture X After reset, the default state is GPIOF6.
Memory Maps Table 6. Chip Memory Configurations 56F8245 56F8246 56F8247 56F8255 56F8256 56F8357 Program Flash (PFLASH) 24K x 16 or 48 KB 24K x 16 or 48 KB 32K x 16 or 64 KB Erase/program via flash interface unit and word writes to CDBW Unified RAM (RAM) 3K x 16 or 6 KB 4K x 16 or 8 KB 4K x 16 or 8 KB Usable by the program and data memory spaces On-Chip Memory 4.2 Use Restrictions Program Map The MC56F825x/MC56F824x series provide up to 64 KB on-chip flash memory.
Memory Maps 1 2 All addresses are 16-bit word addresses. This RAM is shared with data space starting at address X: 0x00 0000. See Figure 7. Table 9. Program Memory Map1 for 56F8245/46 at Reset Begin/End Address 1 2 4.
Memory Maps 2 This RAM is shared with program space starting at P: 0x00 8000. See Figure 6 and Figure 7. On-chip RAM is also mapped into program space starting at P: 0x00 8000. This mapping eases online reprogramming of on-chip flash. Program Data EOnCE 0xFF FF00 Reserved 0x01 0000 Reserved Peripherals 0x00 F000 Reserved 0x00 9000 0x00 9000 Dual Port RAM RAM RAM Alias 0x00 8000 0x00 8000 Reserved 0x00 1000 Flash RAM 0x00 0000 0x00 0000 Figure 6.
Memory Maps Table 11. 56F8245/56 Data Memory Map1 Begin/End Address 1 2 Memory Allocation X:0xFF FFFF X:0xFF FF00 EOnCE 256 locations allocated X:0xFF FEFF X:0x01 0000 RESERVED X:0x00 FFFF X:0x00 F000 On-Chip Peripherals 4096 locations allocated X:0x00 EFFF X:0x00 8C00 RESERVED X:0x00 8BFF X:0x00 8000 On-Chip Data RAM Alias X:0x00 7FFF X:0x00 0C00 RESERVED X:0x00 0BFF X:0x00 0000 On-Chip Data RAM 6 KB2 All addresses are 16-bit word addresses.
Memory Maps • The 56F824x’s startup address is located at 0x00 2000. The reset value of VBA is reset to a value of 0x0020 that corresponds to the address 0x00 2000. By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions.
Memory Maps Table 12. Data Memory Peripheral Base Address Map Summary (continued) Peripheral Prefix Base Address Cyclic Redundancy Check Generator CRC X:0x00 F230 Comparator Voltage Reference A REFA X:0x00 F240 Comparator Voltage Reference B REFB X:0x00 F250 Comparator Voltage Reference C REFB X:0x00 F260 eFlexPWM X:0x00 F300 FM X:0x00 F400 MSCAN X:0x00 F440 Enhanced Flex PWM Module Flash Memory Interface Freescale Controller Area Network 1 4.
General System Control Information Table 13. EOnCE Memory Map Address Register Abbreviation X:0xFF FF91–X:0xFF FF90 OBMSK (32 bits) X:0xFF FF8F Register Name Breakpoint Unit Mask Register 2 Reserved X:0xFF FF8E OBCNTR EOnCE Breakpoint Unit Counter X:0xFF FF8D Reserved X:0xFF FF8C Reserved X:0xFF FF8B Reserved X:0xFF FF8A OESCR X:0xFF FF89 –X:0xFF FF00 External Signal Control Register Reserved 5 General System Control Information 5.
General System Control Information • Software reset (SWR) Each of these sources has an associated bit in the reset status register (RSTAT) in the system integration module (SIM). The external pin reset function is shared with a GPIO port A7 on the RESET/GPIOA7 pin. The reset function is enabled following any reset of the device. Bit 7 of the GPIOA_PER register must be cleared to use this pin as a GPIO port pin. When the pin is enabled as the RESET pin, an internal pullup device is automatically enabled.
General System Control Information when selecting a crystal, because crystal parameters determine the component values required to provide maximum stability and reliable startup. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and startup stabilization time.
General System Control Information EXT_SEL & CLK_MODE = 1 MC56F825x/MC56F824x GPIOC_PER0 = 0 CLKIN GPS_C0 = 1 External Clock (≤ 120 MHz) Figure 11. Connecting an External Clock Signal Using GPIO 5.5 Interrupt Controller The MC56F825x/MC56F824x interrupt controller (INTC) module arbitrates the various interrupt requests (IRQs). When an interrupt of sufficient priority exists, the INTC signals to the 56800E core and provides the address to which to jump to service the interrupt.
General System Control Information • • • • • • • • • • • 5.
General System Control Information Figure 12. On-Chip Comparator Connections Table 14. Connections by Comparator Inputs Comparator Input Comparator A Comparator B Comparator B P0 (from internal) 5-bit VREFA_DAC 5-bit VREFB_DAC 5-bit VREFC_DAC P1 (from internal) 12-bit DAC 12-bit DAC 12-bit DAC P2 (from package pin) CMPA_P2 CMPB_P2 CMPC_P2 P3 (from package pin) CMP_REF CMP_REF CMP_REF MC56F825x/MC56F824x Digital Signal Controller, Rev.
General System Control Information Table 14. Connections by Comparator Inputs (continued) Comparator Input Comparator A Comparator B Comparator B M0 (from package pin) CMPA_M0 CMPB_M0 CMPC_M0 M1 (from package pin) CMPA_M1 CMPB_M1 CMPC_M1 M2 (from package pin) CMPA_M2 CMPB_M2 CMPC_M2 M3 (from internal) 12-bit DAC 12-bit DAC 12-bit DAC 5.7.
General System Control Information Enhanced Flex PWM Module EXT_CLK XBAR_OUT20 XBAR_IN2 FAULT0 XBAR_OUT21 FAULT1 XBAR_OUT22 XBAR_IN 3 XBAR_IN4 FAULT2 XBAR_OUT23 FAULT3 XBAR_OUT24 EXT_FORCE Submodule 3 XBAR_OUT0 EXTA XBAR_OUT15 EXT_SYNC XBAR_OUT19 XBAR_OUT2 OUT_TRIG0 XBAR_IN20 XBAR_OUT3 OUT_TRIG1 XBAR_IN21 OUT_TRIG0 XBAR_OUT1 XBAR_OUT4 XBAR_OUT5 XBAR_OUT14 XBAR_IN9 EXT_SYNC OUT_TRIG1 OR XBAR_IN18 EXT_SYNC XBAR_OUT17 Crossbar Switch XBAR_OUT9 Window/ Sample XBAR_IN10 C
General System Control Information Table 15.
General System Control Information Table 16.
Security Features • If the ADC conversion result in SAMPLE1 is less than the value programmed into the low limit register 1, PWM1_EXTB is driven high. State of PWM2_EXTB: • • 5.8 If the ADC conversion result in SAMPLE2 is greater than the value programmed into the high limit register 2, PWM2_EXTB is driven low. If the ADC conversion result in SAMPLE2 is less than the value programmed into the low limit register 2, PWM2_EXTB is driven high.
Security Features word ensures that the device remains secure after the next reset (caused, for example, by the device powering down). Refer to the flash memory section of the device’s reference manual for details. When flash security mode is enabled, the MC56F825x/MC56F824x disables the core’s EOnCE debug capabilities. Normal program execution is otherwise unaffected. 6.2 Flash Access Lock and Unlock Mechanisms Several methods effectively lock or unlock the on-chip flash. 6.2.
Specifications 6.2.4 6.2.4.1 Flash Lockout Recovery without Mass Erase Without Presenting Back Door Access Keys to the Flash Unit A user can unsecure a secured device by programming the word 0x0000 into program flash location 0x00 7FF7. After completing the programming, the JTAG TAP controller and the device must be reset to return to normal unsecured operation.
Specifications 7.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. CAUTION Stress beyond the limits specified in Table 17 may affect device reliability or cause permanent damage to the device. Unless otherwise stated, all specifications within this section apply over the ambient temperature range of –40 ºC to +105 ºC over the following supply ranges: VSS = VSSA = 0 V, VDD = VDDA = 3.0 V to 3.
Specifications 7.3 ESD Protection and Latch-up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, use normal handling precautions to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing conforms with AEC-Q100 Stress Test Qualification.
Specifications Table 20.
Specifications Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. See Section 8.1, “Thermal Design Considerations,” for more detail on thermal design considerations. 7.5 Recommended Operating Conditions This section contains information about recommended operating conditions. Table 22.
Specifications 1 Total chip source or sink current cannot exceed 75 mA Default Mode Pin Group 1: GPIO, TDI, TDO, TMS, TCK Pin Group 2: RESET, GPIOA7 Pin Group 3: ADC and Comparator Analog Inputs Pin Group 4: XTAL, EXTAL Pin Group 5: DAC analog output 7.6 DC Electrical Characteristics This section includes information about power supply requirements and I/O pin characteristics. MC56F825x/MC56F824x Digital Signal Controller, Rev.
Specifications Table 23. DC Electrical Characteristics at Recommended Operating Conditions Symbol Notes Min Typ Max Unit Test Conditions Output Voltage High VOH Pin Group 1 2.4 — — V IOH = IOHmax Output Voltage Low VOL Pin Groups 1, 2 — — 0.4 V IOL = IOLmax Digital Input Current High (a) pull-up enabled or disabled IIH Pin Groups 1, 2 — 0 +/- 2.5 μA VIN = 2.4 V to 5.
Specifications 7.7 Supply Current Characteristics The following table specifies supply current characteristics. Table 24. Current Consumption Mode 1 Conditions Typical @ 3.3 V 25°C (mA) Maximum @ 3.
Specifications 7.8 Power-On Reset, Low Voltage Detection Specification Table 25. Power-On Reset and Low-Voltage Detection Parameters Characteristic Symbol Min Typ Max Unit Low-Voltage Interrupt for 3.3 V supply1 VLVI27 2.6 2.7 2.8 V Low-Voltage Interrupt for 2.5 V supply2 VLVI21 — 2.18 — V Low-Voltage Interrupt Recovery Hysteresis VEIH — 50 — mV Power-On Reset Threshold3 POR 2.6 2.7 2.8 V Brown-Out Reset Threshold4 BOR — 1.8 1.
Specifications Figure 16 shows the definitions of the following signal states: • • • • Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH Data1 Valid Data2 Valid Data1 Data3 Valid Data2 Data3 Data Three-stated Data Invalid State Data Active Data Active Figure 16.
Specifications Table 29. External Clock Operation Timing Requirements1 (continued) Characteristic Symbol Min Typ Max Unit External clock input rise time4 trise — — 3 ns 5 tfall — — 3 ns Input high voltage overdrive by an external clock Vih 0.85VDD — — V Input high voltage overdrive by an external clock Vil — — 0.3VDD V External clock input fall time 1 Parameters listed are guaranteed by design.
Specifications 7.15 External Crystal or Resonator Requirement Table 31. Crystal or Resonator Requirement 7.16 Characteristic Symbol Min Typ Max Unit Frequency of operation fXOSC 4 8 16 MHz Relaxation Oscillator Timing Table 32. Relaxation Oscillator Timing Characteristic Symbol Minimum Relaxation oscillator output frequency1 Normal Mode Standby Mode fop — Relaxation oscillator stabilization time2 troscs — 1 3 ms Cycle-to-cycle jitter.
Specifications 7.17 Reset, Stop, Wait, Mode Select, and Interrupt Timing NOTE All address and data buses described here are internal. Table 33.
Specifications Table 34.
Specifications SS (Input) SS is held high on master tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) LSB in tDI(ref) tDV Master MSB out Bits 14–1 Master LSB out tR tF Figure 20.
Specifications SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14–1 tDS Slave LSB out tDV tDI tDH MOSI (Input) MSB in tD Bits 14–1 tDI LSB in Figure 22.
Specifications 7.19 Queued Serial Communication Interface (SCI) Timing Table 35. SCI Timing1 Characteristic Symbol Min Max Unit See Figure Baud rate2 BR — (fMAX/16) Mbps — RXD pulse width RXDPW 0.965/BR 1.04/BR ns Figure 24 TXD pulse width TXDPW 0.965/BR 1.
Specifications 7.20 Freescale’s Scalable Controller Area Network (MSCAN) Table 36. MSCAN Timing Characteristic Symbol Min Max Unit Baud Rate BRCAN — 1 Mbps Bus Wake-up detection TWAKEUP TIPBUS — μs MSCAN_RX CAN receive data pin (Input) TWAKEUP Figure 26. Bus Wake-up Detection 7.21 Inter-Integrated Circuit Interface (I2C) Timing Table 37. I2C Timing Standard Mode Characteristic Symbol Unit Minimum Maximum SCL Clock Frequency fSCL 0 100 kHz Hold time (repeated) START condition.
Specifications SDA tSU; DAT tf tf tr tLOW tHD; STA tr tSP tBUF SCL S tHD; STA tHD; DAT tSU; STA tHIGH tSU; STO SR P S 2 Figure 27. Timing Definition for Standard Mode Devices on the I C Bus 7.22 JTAG Timing Table 38.
Specifications TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) Figure 29. Test Access Port Timing Diagram 7.23 Quad Timer Timing Table 39.
Specifications 7.24 COP Specifications Table 40. COP Specifications Parameter Symbol Min Typ Max Unit Oscillator output frequency LPFosc 500 1000 1500 Hz Oscillator current consumption in partial power down mode IDD TBD nA 7.25 Analog-to-Digital Converter (ADC) Parameters Table 41. ADC Parameters1 Parameter Symbol Min Typ Max Unit Resolution RES 12 — 12 Bits ADC internal clock fADIC 0.
Specifications Table 41. ADC Parameters1 (continued) Parameter Input impedance Symbol Min Typ Max Unit XIN — See Figure 31 — Ohms AC Specifications9 (gain of 1x, 2x, 4x and fADC ≤ 10 MHz)4 Signal-to-noise ratio SNR — 59 dB Total Harmonic Distortion THD — 64 dB Spurious Free Dynamic Range SFDR — 65 dB Signal-to-noise plus distortion SINAD — 59 dB Effective Number Of Bits ENOB — 9.5 Bits 1 All measurements were made at VDD = 3.3V, VREFH = 3.
Specifications 2. 3. 4. 5. Parasitic capacitance due to the chip bond pad, ESD protection devices, and signal routing: 2.04 pF 8 pF noise damping capacitor Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only connected to it at sampling time: Cgain = 1.4 pF for x1 gain, 2.8 pF for x2 gain, and 5.6 pF for x4 gain. S1 and S2 switch phases are non-overlapping and operate at the ADC clock frequency. S1 S2 Figure 31.
Specifications 1 2 No guaranteed specification within 5% of VDDA or VSSA LSB = 0.806 mV 7.27 5-Bit Digital-to-Analog Converter (DAC) Parameters Table 43. 5-Bit DAC Specifications 7.28 Parameter Symbol Min Typ Max Unit Reference Inputs Vin VDDA — VDDA mV Setup Delay tPRGST TBD TBD TBD ns Step size VSTEP 3Vin/128 Vin/32 5Vin/128 V Output Range VDACOUT Vin/32 — Vin ns HSCMP Specifications Table 44.
Design Considerations B, the internal [state-dependent] component, reflects the supply current required by certain on-chip resources only when those resources are in use. These resources include RAM, flash memory, and the ADCs. C, the internal [dynamic] component, is classic C*V2*F CMOS power dissipation corresponding to the 56800E core and standard cell logic. D, the external [dynamic] component, reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip.
Design Considerations value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated.
Ordering Information Use the following list of considerations to assure correct operation of the MC56F825x/MC56F824x: • • • • • • • • • • • • • • • • 9 Provide a low-impedance path from the board power supply to each VDD pin on the MC56F825x/MC56F824x and from the board ground to each VSS (GND) pin. The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as near as possible to the package supply pins.
Ordering Information Table 46. MC56F825x/MC56F824x Ordering Information 1 Ambient Temperature Range Order Number1 60 –40° to + 105° C –40° to + 125° C MC56F8245VLD MC56F8245MLD 48 60 –40° to + 105° C –40° to + 125° C MC56F8246VLF MC56F8246MLF Low-Profile Quad Flat Pack (LQFP) 64 60 –40° to + 105° C –40° to + 125° C MC56F8247VLH MC56F8247MLH 3.0–3.6 V Low-Profile Quad Flat Pack (LQFP) 44 60 –40° to + 105° C –40° to + 125° C MC56F8255VLD MC56F8255MLD MC56F8256 3.0–3.
Package Mechanical Outline Drawings 10 Package Mechanical Outline Drawings To ensure you have the latest version of a package drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number (shown in the following sections for each package). 10.1 44-pin LQFP MC56F825x/MC56F824x Digital Signal Controller, Rev.
Package Mechanical Outline Drawings MC56F825x/MC56F824x Digital Signal Controller, Rev.
Package Mechanical Outline Drawings Figure 32. 56F8245 and 56F8255 44-Pin LQFP Mechanical Information MC56F825x/MC56F824x Digital Signal Controller, Rev.
Package Mechanical Outline Drawings 10.2 48-pin LQFP MC56F825x/MC56F824x Digital Signal Controller, Rev.
Package Mechanical Outline Drawings Figure 33. 56F8246 and 56F8256 48-Pin LQFP Mechanical Information MC56F825x/MC56F824x Digital Signal Controller, Rev.
Package Mechanical Outline Drawings 10.3 64-pin LQFP MC56F825x/MC56F824x Digital Signal Controller, Rev.
Package Mechanical Outline Drawings MC56F825x/MC56F824x Digital Signal Controller, Rev.
Package Mechanical Outline Drawings Figure 34. 56F8247 and 56F8257 64-Pin LQFP Mechanical Information MC56F825x/MC56F824x Digital Signal Controller, Rev.
Revision History 11 Revision History Table 47 summarizes changes to the document since the release of the previous version. Table 47. Revision History Revision Date Description Table 46 on page 75: Added “M” orderable part numbers Rev. 3 2011-04-22 Table 24 on page 55: Updated data for run, wait, and stop modes, and added data for standby and powerdown modes Table 23 on page 54: Added minimum and maximum values for Internal Pull-Up Resistance Renumbered sections: Section 9 (was 8.
Interrupt Vector Table Appendix A Interrupt Vector Table Table 48 provides the MC56F825x/MC56F824x’s reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced before level 2 and so on.
Interrupt Vector Table Table 48.
Interrupt Vector Table Table 48.
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