Freescale Semiconductor, Inc. Order this document by MC68332TS/D Rev. 2 MC68332 Technical Summary 32-Bit Modular Microcontroller 1 Introduction Freescale Semiconductor, Inc... The MC68332, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB).
Freescale Semiconductor, Inc. Table 1 Ordering Information Package Type TPU Type Temperature Frequency (MHz) 132-Pin PQFP Motion Control –40 to +85 °C 16 MHz 20 MHz –40 to +105 °C 16 MHz 20 MHz Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 1 Ordering Information (Continued) Package Type TPU Type Temperature Frequency (MHz) Package Order Quantity Order Number 144-Pin QFP Motion Control –40 to +85 °C 16 MHz 2 pc tray SPAKMC332GCFV16 20 MHz –40 to +105 °C 16 MHz 20 MHz Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. TABLE OF CONTENTS Section 1 Introduction 1.1 1.2 1.3 1.4 1.5 2 3 Freescale Semiconductor, Inc... 1 Features ......................................................................................................................................5 Block Diagram .............................................................................................................................6 Pin Assignments ...........................................................................
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 1.
Freescale Semiconductor, Inc. 1.
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144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 MC68332 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC VSS PE4/AS PE6/SIZ0 PE7/SIZ1 R/W PF0/MODCLK PF1/IRQ1 PF2/IRQ2 PF3/IRQ3 PF4/IRQ4 PF5/IRQ5 PF6/IRQ6 PF7/IRQ7 BERR HALT RESET VSS CLKOUT VDD
Freescale Semiconductor, Inc. 1.4 Address Map The following figure is a map of the MCU internal addresses. The RAM array is positioned by the base address registers in the associated RAM control block. Unimplemented blocks are mapped externally. $YFF000 $YFFA00 $YFFA80 $YFFB00 $YFFB40 SIM RESERVED TPURAM CONTROL RESERVED Freescale Semiconductor, Inc... $YFFC00 2-KBYTE TPURAM ARRAY QSM $YFFE00 TPU $YFFFFF 332 ADDRESS MAP Figure 4 MCU Address Map 1.
Freescale Semiconductor, Inc. 2 Signal Descriptions 2.1 Pin Characteristics The following table shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin function. Refer to the table, MCU Driver Types, for a description of output drivers. An entry in the discrete I/O column of the MCU Pin Characteristics table indicates that a pin has an alternate I/O function.
Freescale Semiconductor, Inc. Table 2 MCU Pin Characteristic (Continued) Pin Mnemonic Output Driver Input Synchronized Input Hysteresis Discrete I/O Port Designation T2CLK TPUCH[15:0] — Y Y — — A Y Y — — TSC — Y Y — — TXD Bo Y Y I/O PQS7 — — — Special — — — — Special — XFC2 2 XTAL Freescale Semiconductor, Inc... NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin. 2.
Freescale Semiconductor, Inc. 2.4 Signal Characteristics Table 5 MCU Signal Characteristics Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 5 MCU Signal Characteristics (Continued) Signal Name MCU Module Signal Type Active State TSC SIM Input — TXD QSM Output — XFC SIM Input — XTAL SIM Output — 2.5 Signal Function Table 6 MCU Signal Function Signal Name Address Bus Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. 3 System Integration Module The MCU system integration module (SIM) consists of five functional blocks that control system startup, initialization, configuration, and external bus. SYSTEM CONFIGURATION AND PROTECTION Freescale Semiconductor, Inc... CLOCK SYNTHESIZER CHIP SELECTS CLKOUT EXTAL MODCLK CHIP SELECTS EXTERNAL BUS EXTERNAL BUS INTERFACE RESET FACTORY TEST TSC FREEZE/QUOT S(C)IM BLOCK Figure 5 SIM Block Diagram 3.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. MODULE CONFIGURATION AND TEST Freescale Semiconductor, Inc... RESET STATUS HALT MONITOR RESET REQUEST BUS MONITOR BERR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG TIMER CLOCK RESET REQUEST 29 PRESCALER IRQ [7:1] PERIODIC INTERRUPT TIMER SYS PROTECT BLOCK Figure 6 System Configuration and Protection Block 3.2.1 System Configuration The SIM controls MCU configuration during normal operation and during internal testing.
Freescale Semiconductor, Inc. EXOFF — External Clock Off 0 = The CLKOUT pin is driven from an internal clock source. 1 = The CLKOUT pin is placed in a high-impedance state. FRZSW — Freeze Software Enable 0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run. 1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer counters are disabled, preventing interrupts during software debug. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 3.2.2 System Protection Control Register The system protection control register controls system monitor functions, software watchdog clock prescaling, and bus monitor timing. This register can be written only once following power-on or reset, but can be read at any time. SYPCR —System Protection Control Register $YFFA21 8 15 NOT USED 7 6 SWE SWP 1 MODCLK 5 4 SWT 3 2 HME BME 1 0 0 0 BMT RESET: 0 0 0 0 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 3.2.3 Bus Monitor The internal bus monitor checks for excessively long DSACK response times during normal bus cycles and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The monitor asserts BERR if response time is excessive. DSACK and AVEC response times are measured in clock cycles. The maximum allowable response time can be selected by setting the BMT field.
Freescale Semiconductor, Inc. 3.2.7 Periodic Interrupt Timer The periodic interrupt timer (PIT) generates interrupts of specified priorities at specified intervals. Timing for the PIT is provided by a programmable prescaler driven by the system clock. PICR — Periodic Interrupt Control Register 15 14 13 12 11 0 0 0 0 0 0 0 0 0 $YFFA22 10 8 7 0 PIRQL PIV RESET: 0 0 0 0 0 0 0 0 1 1 1 1 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 3.3 System Clock The system clock in the SIM provides timing signals for the IMB modules and for an external peripheral bus. Because MCU operation is fully static, register and memory contents are not affected when the clock rate changes. System hardware and software support changes in the clock rate during operation. The system clock signal can be generated in three ways.
Freescale Semiconductor, Inc. When an external system clock signal is applied (i.e., the PLL is not used), duty cycle of the input is critical, especially at near maximum operating frequencies. The relationship between clock signal duty cycle and clock signal period is expressed: Minimum external clock period = minimum external clock high/low time 50% — percentage variation of external clock input duty cycle 3.3.2 Clock Synthesizer Operation Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 3.3.3 Clock Control The clock control circuits determine system clock frequency and clock operation under special circumstances, such as following loss of synthesizer reference or during low-power operation. Clock source is determined by the logic state of the MODCLK pin during reset.
Freescale Semiconductor, Inc. 3.4 External Bus Interface The external bus interface (EBI) transfers information between the internal MCU bus and external devices. The external bus has 24 address lines and 16 data lines. The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0).
Freescale Semiconductor, Inc. Table 9 CPU32 Address Space Encoding FC2 FC1 FC0 Address Space 0 0 0 Reserved 0 0 1 User Data Space 0 1 0 User Program Space 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Supervisor Data Space 1 1 0 Supervisor Program Space 1 1 1 CPU Space Freescale Semiconductor, Inc... 3.4.3 Address Bus Address bus signals ADDR[23:0] define the address of the most significant byte to be transferred during a bus cycle.
Freescale Semiconductor, Inc. 3.4.8 Data Transfer Mechanism The MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge inputs (DSACK1 and DSACK0). 3.4.9 Dynamic Bus Sizing The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports.
Freescale Semiconductor, Inc. ADDR0 also affects the operation of the data multiplexer. During an operand transfer, ADDR[23:1] indicate the word base address of the portion of the operand to be accessed, and ADDR0 indicates the byte offset from the base. 3.4.11 Misaligned Operands CPU32 processor architecture uses a basic operand size of 16 bits. An operand is misaligned when it overlaps a word boundary. This is determined by the value of ADDR0.
Freescale Semiconductor, Inc. Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single DSACK generator is shared by all circuits. Multiple chip selects assigned to the same address and control must have the same number of wait states. Chip selects can also be synchronized with the ECLK signal available on ADDR23. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 3.5.1 Chip-Select Registers Pin assignment registers CSPAR0 and CSPAR1 determine functions of chip-select pins. These registers also determine port size (8- or 16-bit) for dynamic bus allocation. A pin data register (PORTC) latches discrete output data. Blocks of addresses are assigned to each chip-select function. Block sizes of 2 Kbytes to 1 Mbyte can be selected by writing values to the appropriate base address register (CSBAR).
Freescale Semiconductor, Inc. CSPAR1 —Chip Select Pin Assignment Register 1 15 14 13 12 11 10 9 8 0 0 0 0 0 0 CSPA1[4] 0 0 0 0 0 $YFFA46 7 6 5 CSPA1[3] 4 CSPA1[2] 3 2 1 CSPA1[1] 0 CSPA1[0] RESET: 0 DATA7 1 DATA [7:6] 1 DATA [7:5] 1 DATA [7:4] 1 DATA [7:3] 1 CSPAR1 contains five 2-bit fields that determine the functions of corresponding chip-select pins. CSPAR1[15:10] are not used. These bits always read zero; writes have no effect. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 3.5.3 Base Address Registers A base address is the starting address for the block enabled by a given chip select. Block size determines the extent of the block above the base address. Each chip select has an associated base register so that an efficient address map can be constructed for each application.
Freescale Semiconductor, Inc. CSORBT —Chip-Select Option Register Boot ROM 15 14 MODE 13 12 BYTE 11 R/W 10 $YFFA4A 9 6 STRB 5 DSACK 4 3 SPACE 1 IPL 0 AVEC RESET: 0 1 1 1 1 0 1 1 0 1 1 1 0 CSOR[10:0] —Chip-Select Option Registers 15 14 MODE 13 12 BYTE 11 R/W 10 0 0 0 $YFFA4E–$YFFA76 9 6 STRB 5 DSACK 4 3 SPACE 1 IPL 0 AVEC RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... DSACK — Data and Size Acknowledge This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus timing with internal DSACK generation by controlling the number of wait states that are inserted to optimize bus speed in a particular application. The following table shows the DSACK field encoding. The fast termination encoding (1110) is used for two-cycle access to external memory.
Freescale Semiconductor, Inc. AVEC — Autovector Enable 0 = External interrupt vector enabled 1 = Autovector enabled This field selects one of two methods of acquiring the interrupt vector during the interrupt acknowledge cycle. It is not usually used in conjunction with a chip-select pin. If the chip select is configured to trigger on an interrupt acknowledge cycle (SPACE = 00) and the AVEC field is set to one, the chip select automatically generates an AVEC in response to the interrupt cycle.
Freescale Semiconductor, Inc. PEPAR — Port E Pin Assignment Register 15 $YFFA17 8 NOT USED 7 6 5 4 3 2 1 0 PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0 RESET: DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 The bits in this register control the function of each port E pin. Any bit set to one configures the corresponding pin as a bus control signal, with the function shown in the following table.
Freescale Semiconductor, Inc. PFPAR — Port F Pin Assignment Register 15 $YFFA1F 8 NOT USED 7 6 5 4 3 2 1 0 PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0 RESET: DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 The bits in this register control the function of each port F pin. Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be an interrupt request signal or MODCLK. The MODCLK signal has no function after reset.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 3.7.3 Reset Timing The RESET input must be asserted for a specified minimum period in order for reset to occur. External RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is asserted, SIM pins are either in a disabled high-impedance state or are driven to their inactive states.
Freescale Semiconductor, Inc. When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. Once the output drivers change state, the MCU must be powered down and restarted before normal operation can resume. 3.8 Interrupts Interrupt recognition and servicing involve complex interaction between the central processing unit, the system integration module, and a device or module requesting interrupt service.
Freescale Semiconductor, Inc. mask lower-priority interrupts during exception processing, and it is decoded by modules that have requested interrupt service to determine whether the current interrupt acknowledge cycle pertains to them. Modules that have requested interrupt service decode the IP value placed on the address bus at the beginning of the interrupt acknowledge cycle, and if their requests are at the specified IP level, respond to the cycle.
Freescale Semiconductor, Inc. 1. The dominant interrupt source supplies a vector number and DSACK signals appropriate to the access. The CPU32 acquires the vector number. 2. The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source or the pin can be tied low), and the CPU32 generates an autovector number corresponding to interrupt priority. 3. The bus monitor asserts BERR and the CPU32 generates the spurious interrupt vector number. F.
Freescale Semiconductor, Inc. 4 Central Processor Unit Based on the powerful MC68020, the CPU32 processing module provides enhanced system performance and also uses the extensive software base for the Motorola M68000 family. 4.1 Overview Freescale Semiconductor, Inc... The CPU32 is fully object code compatible with the M68000 Family, which excels at processing calculation-intensive algorithms and supporting high-level languages.
Freescale Semiconductor, Inc. 31 16 15 8 7 0 D0 D1 D2 D3 Data Registers D4 D5 D6 D7 31 16 15 0 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 4.3 Status Register The status register contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The lower byte containing the condition codes is the only portion of the register available at the user privilege level; it is referenced as the condition code register (CCR) in user programs.
Freescale Semiconductor, Inc. 4.6 Instruction Set Summary Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 20 Instruction Set Summary(Continued) Instruction Syntax Operand Size MOVES1 Rn, , Rn 8, 16, 32 MULS/MULU , Dn , Dl , Dh : Dl 16 ∗ 16 ⇒ 32 32 ∗ 32 ⇒ 32 32 ∗ 32 ⇒ 64 NBCD Í 8 8 Source ∗ Destination ⇒ Destination (signed or unsigned) 0 − Destination10 − X ⇒ Destination NEG Í 8, 16, 32 0 − Destination ⇒ Destination NEGX Í 8, 16, 32 0 − Destination − X ⇒ Destination NOP NOT Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 20 Instruction Set Summary(Continued) Instruction Syntax Operand Size SWAP Dn 16 Operation MSW Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 4.7 Background Debugging Mode The background debugger on the CPU32 is implemented in CPU microcode. The background debugging commands are summarized below. Freescale Semiconductor, Inc... Table 21 Background Debuggung Mode Command Mnemonic Description Read D/A Register RDREG/RAREG Write D/A Register WDREG/WAREG The data operand is written to the specified address or data register.
Freescale Semiconductor, Inc. 5 Time Processor Unit The time processor unit (TPU) provides optimum performance in controlling time-related activity. The TPU contains a dedicated execution unit, a tri-level prioritized scheduler, data storage RAM, dual-time bases, and microcode ROM. The TPU controls 16 independent, orthogonal channels, each with an associated I/O pin, and is capable of performing any microcoded time function.
Freescale Semiconductor, Inc. 5.1.2 Input Capture/Input Transition Counter (ITC) Any channel of the TPU can capture the value of a specified TCR upon the occurrence of each transition or specified number of transitions, and then generate an interrupt request to notify the CPU. A channel can perform input captures continually, or a channel can detect a single transition or specified number of transitions, then cease channel activity until reinitialization.
Freescale Semiconductor, Inc. 5.1.7 Period Measurement with Missing Transition Detect (PMM) Period measurement with missing transition detect allows a special-purpose 23-bit period measurement. It detects the occurrence of a missing transition (caused by a missing tooth on the sensed wheel), indicated by a period measurement that is greater than a programmable ratio of the previous period measurement.
Freescale Semiconductor, Inc. lation parameter. From 1 to 255 period measurements can be made and summed with the previous measurement(s) before the TPU interrupts the CPU, allowing instantaneous or average frequency measurement, and the latest complete accumulation (over the programmed number of periods). The pulse width (high-time portion) of an input signal can be measured (up to 24 bits) and added to a previous measurement over a programmable number of periods (1 to 255).
Freescale Semiconductor, Inc. 5.2.3 Queued Output Match (QOM) QOM can generate single or multiple output match events from a table of offsets in parameter RAM. Loop modes allow complex pulse trains to be generated once, a specified number of times, or continuously. The function can be triggered by a link from another TPU channel. In addition, the reference time for the sequence of matches can be obtained from another channel.
Freescale Semiconductor, Inc. 5.2.9 Frequency Measurement (FQM) FQM counts the number of input pulses to a TPU channel during a user-defined window period. The function has single shot and continuous modes. No pulses are lost between sample windows in continuous mode. The user selects whether to detect pulses on the rising or falling edge. This function is intended for high speed measurement; measurement of slow pulses with noise rejection can be made with PTA. 5.2.
Freescale Semiconductor, Inc. 5.4 Parameter RAM Parameter RAM occupies 256 bytes at the top of the TPU module address map. Channel parameters are organized as 128 16-bit words. However, only 100 words are actually implemented. The parameter RAM address map shows how parameter words are organized in memory. Table 23 TPU Parameter RAM Address Map Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. TCR1P — Timer Count Register 1 Prescaler Control TCR1 is clocked from the output of a prescaler. The prescaler's input is the internal TPU system clock divided by either 4 or 32, depending on the value of the PSCK bit. The prescaler divides this input by 1, 2, 4, or 8. Channels using TCR1 have the capability to resolve down to the TPU system clock divided by 4. ÷4 DIV4 CLOCK SYSTEM CLOCK 1 – DIV4 0 – DIV32 ÷ 32 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. EMU — Emulation Control In emulation mode, the TPU executes microinstructions from MCU TPURAM exclusively. Access to the TPURAM module through the IMB by a host is blocked, and the TPURAM module is dedicated for use by the TPU. After reset, this bit can be written only once. 0 = TPU and TPURAM not in emulation mode 1 = TPU and TPURAM in emulation mode Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 5.5.2 Channel Control Registers CIER — Channel Interrupt Enable Register $YFFE0A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 CH 9 CH 8 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET: 0 CH[15:0] — Channel Interrupt Enable/Disable 0 = Channel interrupts disabled 1 = Channel interrupts enabled Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. HSQR0 — Host Sequence Register 0 14 15 13 12 CH 14 CH 15 11 10 $YFFE14 9 CH 13 8 CH 12 7 6 CH 11 5 4 3 CH 10 2 1 CH 9 0 CH 8 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSQR1 — Host Sequence Register 1 15 14 13 CH 7 12 11 CH 6 10 0 0 $YFFE16 9 CH 5 8 7 CH 4 6 5 CH 3 4 3 CH 2 2 1 CH 1 0 CH 0 RESET: Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. CHX[1:0] 00 01 10 11 Service Disabled Low Middle High Guaranteed Time Slots — 4 out of 7 2 out of 7 1 out of 7 5.5.3 Development Support and Test Registers Freescale Semiconductor, Inc... These registers are used for custom microcode development or for factory test. Describing the use of the registers is beyond the scope of this technical summary. Register names and addresses are given for reference only.
Freescale Semiconductor, Inc. 6 Queued Serial Module The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial communication interface (SCI). MISO/PQS0 MOSI/PQS1 SCK/PQS2 PCS0/SS/PQS3 PCS1/PQS4 PCS2/PQS5 PCS3/PQS6 QSPI Freescale Semiconductor, Inc... PORT QS IMB INTERFACE LOGIC TXD/PQS7 SCI RXD QSM BLOCK Figure 13 QSM Block Diagram 6.
Freescale Semiconductor, Inc. 6.2 Address Map The “Access” column in the QSM address map below indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the QSMCR. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 6.3 Pin Function The following table is a summary of the functions of the QSM pins when they are not configured for general-purpose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an input or output. Pin Mode MISO Master Serial Data Input to QSPI Slave Serial Data Output from QSPI QSPI Pins MOSI Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. The system software must stop each submodule before asserting STOP to avoid complications at restart and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and the operation should be verified for completion before asserting STOP. The QSPI submodule should be stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set.
Freescale Semiconductor, Inc. QIVR — QSM Interrupt Vector Register $YFFC05 8 15 7 0 INTV QILR RESET: 0 0 0 0 1 1 1 1 At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the exception table. This vector is selected until QIVR is written. A user-defined vector ($40–$FF) should be written to QIVR during QSM initialization. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Table 25 QSPAR Pin Assignments PQSPAR Field PQSPA0 PQSPA1 PQSPA2 PQSPA3 PQSPA4 Freescale Semiconductor, Inc... PQSPA5 PQSPA6 PQSPA7 PQSPAR Bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pin Function PQS0 MISO PQS1 MOSI PQS21 SCK PQS3 PCS0/SS PQS4 PCS1 PQS5 PCS2 PQS6 PCS3 PQS72 TXD NOTES: 1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE in SPCR1 set), in which case it becomes SPI serial clock SCK. 2.
Freescale Semiconductor, Inc. Table 26 Effect of DDRQS on QSM Pin Function QSM Pin Mode MISO Master DDRQS Bit DDQ0 Transmit DDQ7 Bit State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X Receive None NA Slave MOSI Master DDQ1 Slave SCK1 Master DDQ2 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 6.5 QSPI Submodule The QSPI submodule communicates with external devices through a synchronous serial bus. The QSPI is fully compatible with the serial peripheral interface (SPI) systems found on other Motorola products. A block diagram of the QSPI is shown below. QUEUE CONTROL BLOCK QUEUE POINTER Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. MSTR — Master/Slave Mode Select 0 = QSPI is a slave device and only responds to externally generated serial data. 1 = QSPI is system master and can initiate transmission to external SPI devices. MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and may only be written by the CPU. Freescale Semiconductor, Inc... WOMQ — Wired-OR Mode for QSPI Pins 0 = Outputs have normal MOS drivers.
Freescale Semiconductor, Inc. SCK baud rate: SCK Baud Rate = System Clock/(2SPBR) or SPBR = System Clock/(2SCK)(Baud Rate Desired) where SPBR equals {2, 3, 4,..., 255} Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its inactive state value. No serial transfers occur. At reset, baud rate is initialized to one eighth of the system clock frequency. SPCR1 — QSPI Control Register 1 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. SPCR2 — QSPI Control Register 2 15 14 13 12 SPIFIE WREN WRTO 0 0 0 0 $YFFC1C 11 8 ENDQP 7 6 5 4 0 0 0 0 0 0 0 0 3 0 NEWQP RESET: 0 0 0 0 0 0 0 0 0 SPCR2 contains QSPI configuration parameters. The CPU can read and write this register; the QSM has read access only. Writes to SPCR2 are buffered.
Freescale Semiconductor, Inc. HALT — Halt 0 = Halt not enabled 1 = Halt enabled When HALT is asserted, the QSPI stops on a queue boundary. It is in a defined state from which it can later be restarted. SPSR — QSPI Status Register 15 $YFFC1F 8 SPCR3 7 6 5 4 SPIF MODF HALTA 0 0 0 3 0 CPTQP RESET: 0 0 0 0 0 0 Freescale Semiconductor, Inc... SPSR contains QSPI status information. Only the QSPI can assert the bits in this register.
Freescale Semiconductor, Inc. D00 D20 RR0 RR1 RR2 D40 TR0 TR1 TR2 CR0 CR1 CR2 RECEIVE RAM TRANSMIT RAM COMMAND RAM RRD RRE RRF TRD TRE TRF CRD CRE CRF D1E D3E D4F WORD WORD BYTE Freescale Semiconductor, Inc... QSPI RAM MAP Figure 15 QSPI RAM Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the QSPI can operate independently of the CPU.
Freescale Semiconductor, Inc. Command RAM is used by the QSPI when in master mode. The CPU writes one byte of control information to this segment for each QSPI command to be executed. The QSPI cannot modify information in command RAM. Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer. The command control field provides transfer options. A maximum of 16 commands can be in the queue.
Freescale Semiconductor, Inc. 6.6 SCI Submodule The SCI submodule is used to communicate with external devices through an asynchronous serial bus. The SCI is fully compatible with the SCI systems found on other Motorola MCUs, such as the M68HC11 and M68HC05 Families. 6.6.1 SCI Pins There are two unidirectional pins associated with the SCI. The SCI controls the transmit data (TXD) pin when enabled, whereas the receive data (RXD) pin remains a dedicated input pin to the SCI.
Freescale Semiconductor, Inc. Writing a value of zero to SCBR disables the baud rate generator. The following table lists the SCBR settings for standard and maximum baud rates using 16.78-MHz and 20.97-MHz system clocks. Table 27 SCI Baud Rates Freescale Semiconductor, Inc... Nominal Baud Rate Actual Rate with 16.78-MHz Clock 64.0 110.0 299.9 599.9 1199.7 2405.0 4810.0 9532.5 19418.1 37449.1 74898.3 524288.
Freescale Semiconductor, Inc. PE — Parity Enable 0 = SCI parity disabled 1 = SCI parity enabled PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the received parity bit is not correct, the SCI sets the PF error flag in SCSR. When PE is set, the most significant bit (MSB) of the data field is used for the parity function, which results in either seven or eight bits of user data, depending on the condition of M bit.
Freescale Semiconductor, Inc. SBK — Send Break 0 = Normal operation 1 = Break frame(s) transmitted after completion of current frame SBK provides the ability to transmit a break code from the SCI. If the SCI is transmitting when SBK is set, it will transmit continuous frames of zeros after it completes the current frame, until SBK is cleared.
Freescale Semiconductor, Inc. IDLE — Idle-Line Detected Flag 0 = SCI receiver did not detect an idle-line condition. 1 = SCI receiver detected an idle-line condition. IDLE is disabled when RWU in SCCR1 is set. IDLE is set when the SCI receiver detects the idle-line condition specified by ILT in SCCR1. If cleared, IDLE will not set again until after RDRF is set. RDRF is set when a break is received, so that a subsequent idle line can be detected. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. 7 Standby RAM with TPU Emulation RAM The TPURAM module contains a 2-Kbyte array of fast (two bus cycle) static RAM, which is especially useful for system stacks and variable storage. Alternately, it can be used by the TPU as emulation RAM for new timer algorithms. 7.1 Overview Freescale Semiconductor, Inc... The TPURAM can be mapped to any 4-Kbyte boundary in the address map, but must not overlap the module control registers. (Overlap makes the registers inaccessible.
Freescale Semiconductor, Inc. RASP — RAM Array Space Field 0 = TPURAM array is placed in unrestricted space 1 = TPURAM array is placed in supervisor space TRAMTST — TPURAM Test Register TRAMTST is used for factory testing of the TPURAM module.
Freescale Semiconductor, Inc. 8 Summary of Changes Freescale Semiconductor, Inc... This is a partial revision. Most of the publication remains the same, but the following changes were made to improve it. Typographical errors that do not affect content are not annotated. This document has also been reformatted for use on the web. Pages 2-3 New Ordering Information included. Page 6 New block diagram drawn. Page 7 New 132-pin assignment diagram drawn. Page 8 New 144-pin assignment diagram drawn.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MC68332 MC68332TS/D For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.