MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet M68HC08 Microcontrollers MC68HC908QY4/D Rev. 6 03/2010 freescale.
MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST.
Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History (Sheet 1 of 3) Date Revision Level September, 2002 N/A December, 2002 January, 2003 0.1 0.2 Page Number(s) Description Initial release N/A 1.2 Features — Added 8-pin dual flat no lead (DFN) packages to features list. 19 Figure 1-2.
Revision History (Sheet 2 of 3) Date August, 2003 Revision Level 1.0 Description Reformatted to meet latest M68HC08 documentation standards N/A Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt module and TCLK pin designator. 20 Figure 1-2. MCU Pin Assignments — Added TCLK pin designator. 21 Table 1-2. Pin Functions — Added TCLK pin description. 22 Table 1-3. Function Priority in Shared Pins — Revised table for clarity and to add TCLK. 23 Figure 2-1.
Revision History Revision History (Sheet 3 of 3) Date Revision Level Page Number(s) Description Reformatted to meet current documentation standards November, 2004 July, 2005 March, 2010 4.0 5.0 6.0 Throughout 6.3.1 BUSCLKX4 — Clarified description of BUSCLKX4 58 Chapter 7 Central Processor Unit (CPU) — In 7.7 Instruction Set Summary: Reworked definitions for STOP instruction Added WAIT instruction 70 71 13.8.1 SIM Reset Status Register — Clarified SRSR flag setting 117 14.9.
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Chapters MC68HC908QY/QT Family Data Sheet, Rev.
Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 1.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . .
Table of Contents 3.6 3.7 3.7.1 3.7.2 3.7.3 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 7 Central Processor Unit (CPU) 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 9.7 9.7.1 9.7.2 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Chapter 10 Low-Voltage Inhibit (LVI) 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.5 10.
Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.2.2 Data Direction Register A.
Table of Contents 13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.8.1 SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.8.2 Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Chapter 14 Timer Interface Module (TIM) 14.1 Introduction . . . . . . . . . . .
.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents MC68HC908QY/QT Family Data Sheet, Rev.
Chapter 1 General Description 1.1 Introduction The MC68HC908QY4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is a Complex Instruction Set Computer (CISC) with a Von Neumann architecture. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 0.4 Table 1-1.
General Description • • • • • • • • • • • • • • • • On-chip in-application programmable FLASH memory (with internal program/erase voltage generation) – MC68HC908QY4 and MC68HC908QT4 — 4096 bytes – MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, and MC68HC908QT1 — 1536 bytes 128 bytes of on-chip random-access memory (RAM) 2-channel, 16-bit timer interface module (TIM) 4-channel, 8-bit analog-to-digital converter (ADC) on MC68HC908QY2, MC68HC908QY4, MC68HC908QT2, and MC68HC908QT4 5 or 13 bidirectional input/o
MCU Block Diagram Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers • Fast 8 × 8 multiply instruction • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.
General Description PTA0/AD0/TCH0/KBI0 CLOCK GENERATOR (OSCILLATOR) PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 DDRA PTA1/AD1/TCH1/KBI1 SYSTEM INTEGRATION MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU SINGLE INTERRUPT MODULE BREAK MODULE DDRB PTB PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 POWER-ON RESET MODULE MC68HC908QY4 AND MC68HC908QT4 4096 BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH 8-BIT ADC 128 BYTES RAM KEYBOARD INTERRUPT MODULE 16-BIT TIM
Pin Assignments VDD 1 8 VSS PTA0/TCH0/KBI0 PTA5/OSC1/AD3/KBI5 2 7 PTA0/AD0/TCH0/KBI0 6 PTA1/TCH1/KBI1 PTA4/OSC2/AD2/KBI4 3 6 PTA1/AD1/TCH1/KBI1 5 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 4 5 PTA2/IRQ/KBI2/TCLK VDD 1 8 VSS PTA5/OSC1/KBI5 2 7 PTA4/OSC2/KBI4 3 PTA3/RST/KBI3 4 8-PIN ASSIGNMENT MC68HC908QT1 PDIP/SOIC 8-PIN ASSIGNMENT MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC VDD 1 16 VSS PTB0 PTB7 2 15 PTB0 14 PTB1 PTB6 3 14 PTB1 4 13 PTA0/TCH0/KBI0 PTA5/OSC1/AD3/KBI5
General Description 1.5 Pin Functions Table 1-2 provides a description of the pin functions. Table 1-2.
Pin Function Priority 1.6 Pin Function Priority Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. NOTE Upon reset all pins come up as input ports regardless of the priority table. Table 1-3.
General Description MC68HC908QY/QT Family Data Sheet, Rev.
Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space.
Memory $0000 ↓ $003F I/O REGISTERS 64 BYTES $0040 ↓ $007F RESERVED(1) 64 BYTES $0080 ↓ $00FF RAM 128 BYTES $0100 ↓ $27FF UNIMPLEMENTED(1) 9984 BYTES $2800 ↓ $2DFF AUXILIARY ROM 1536 BYTES $2E00 ↓ $EDFF UNIMPLEMENTED(1) 49152 BYTES $EE00 ↓ $FDFF FLASH MEMORY MC68HC908QT4 AND MC68HC908QY4 4096 BYTES Note 1. Attempts to execute code from addresses in this range will generate an illegal address reset.
Input/Output (I/O) Section 2.4 Input/Output (I/O) Section Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Memory Addr. $0006 ↓ $000A $000B $000C Register Name Bit 7 Port A Input Pullup Enable Read: OSC2EN Register (PTAPUE) Write: See page 99. Reset: 0 Port B Input Pullup Enable Read: PTBPUE7 Register (PTBPUE) Write: See page 102. Reset: 0 Unimplemented Keyboard Status and Read: Control Register (KBSCR) Write: See page 83. Reset: 0 $001A Read: 0 $001C $001D Keyboard Interrupt Enable Register (KBIER) Write: See page 84.
Input/Output (I/O) Section Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 1 1 1 1 1 1 1 1 TIM Counter Modulo Register Low (TMODL) Write: See page 129. Reset: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 TIM Channel 0 Status and Read: Control Register (TSC0) Write: See page 130.
Memory Addr. Register Name Bit 7 $0039 ↓ $003B Unimplemented $003C ADC Status and Control Read: Register (ADSCR) Write: See page 45. Reset: $003D Unimplemented $003E $003F ADC Data Register Read: (ADR) Write: See page 47. Reset: ADC Input Clock Register Read: (ADICLK) Write: See page 47. Reset: Read: $FE00 Break Status Register (BSR) Write: See page 137.
Input/Output (I/O) Section Addr. Register Name Read: $FE08 $FE09 FLASH Control Register (FLCR) Write: See page 34. Reset: Break Address High Read: Register (BRKH) Write: See page 136. Reset: Read: $FE0A $FE0B Break Address low Register (BRKL) Write: See page 136. Reset: Break Status and Control Read: Register (BRKSCR) Write: See page 136. Reset: Read: $FE0C $FE0D ↓ $FE0F $FFBE $FFBF $FFC0 $FFC1 $FFFF LVI Status Register (LVISR) Write: See page 87.
Memory . Table 2-1.
FLASH Memory (FLASH) 2.6 FLASH Memory (FLASH) This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. The FLASH memory consists of an array of 4096 or 1536 bytes with an additional 48 bytes for user vectors.
Memory ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time.
FLASH Memory (FLASH) 2.6.3 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory to read as a 1: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS (minimum 10 μs). 5. Set the HVEN bit. 6. Wait for a time, tMErase (minimum 4 ms). 7. Clear the ERASE and MASS bits.
Memory 8. 9. 10. 11. 12. 13. Wait for time, tPROG (minimum 30 μs). Repeat step 7 and 8 until all desired bytes within the row are programmed. Clear the PGM bit(1). Wait for time, tNVH (minimum 5 μs). Clear the HVEN bit. After time, tRCV (typical 1 μs), the memory can be accessed in read mode again. NOTE The COP register at location $FFFF should not be written between steps 5–12, when the HVEN bit is set.
FLASH Memory (FLASH) Algorithm for Programming a Row (32 Bytes) of FLASH Memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, tNVS 5 SET HVEN BIT 6 WAIT FOR A TIME, tPGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, tPROG 9 COMPLETED PROGRAMMING THIS ROW? Y N 10 11 12 NOTES: The time between each FLASH address change (step 7 to step 7), or the time between the
Memory 2.6.6 FLASH Block Protect Register The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting address of the protected range within the FLASH memory. Address: Read: Write: $FFBE Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Reset: Unaffected by reset. Initial value from factory is 1.
FLASH Memory (FLASH) 2.6.7 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH, or the operation will discontinue and the FLASH will be on standby mode. 2.6.
Memory MC68HC908QY/QT Family Data Sheet, Rev.
Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 4-channel analog-todigital converter. The ADC module is only available on the MC68HC908QY2, MC68HC908QT2, MC68HC908QY4, and MC68HC908QT4. 3.
Analog-to-Digital Converter (ADC) PTA0/AD0/TCH0/KBI0 CLOCK GENERATOR (OSCILLATOR) PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 DDRA PTA1/AD1/TCH1/KBI1 SYSTEM INTEGRATION MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU SINGLE INTERRUPT MODULE BREAK MODULE DDRB PTB PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 POWER-ON RESET MODULE MC68HC908QY4 AND MC68HC908QT4 4096 BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH 8-BIT ADC 128 BYTES RAM KEYBOARD INTERRUPT MOD
Functional Description INTERNAL DATA BUS READ DDRA DISABLE WRITE DDRA DDRAx RESET WRITE PTA ADCx PTAx READ PTA DISABLE ADC CHANNEL x ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE COCO BUS CLOCK ADC ADC VOLTAGE IN ADCVIN CHANNEL SELECT (1 OF 4 CHANNELS) CH[4:0] ADC CLOCK CLOCK GENERATOR ADIV[2:0] Figure 3-2. ADC Block Diagram MC68HC908QY/QT Family Data Sheet, Rev.
Analog-to-Digital Converter (ADC) 3.3.2 Voltage Conversion When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS. NOTE Input voltage should not exceed the analog supply voltages. 3.3.
Input/Output Signals 3.5.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before using ADC data after exiting stop mode. 3.6 Input/Output Signals The ADC module has four channels that are shared with I/O port A. ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC channels to the ADC module. 3.
Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when ADR is read or ADSCR is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update ADR at the end of each conversion. Only one conversion is allowed when this bit is cleared.
Input/Output Registers 3.7.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Address: $003E Read: Bit 7 6 5 4 3 2 1 Bit 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: Reset: Indeterminate after reset = Unimplemented Figure 3-4. ADC Data Register (ADR) 3.7.3 ADC Input Clock Register This register selects the clock frequency for the ADC.
Analog-to-Digital Converter (ADC) MC68HC908QY/QT Family Data Sheet, Rev.
Chapter 4 Auto Wakeup Module (AWU) 4.1 Introduction This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. Figure 4-1 is a block diagram of the AWU. 4.
Auto Wakeup Module (AWU) COPRS (FROM CONFIG1) VDD AUTOWUGEN TO PTA READ, BIT 6 1 = DIV 29 SHORT 0 = DIV 214 OVERFLOW INT RC OSC EN D 32 kHz CLK E RST AWUL Q AWUIREQ R TO KBI INTERRUPT LOGIC (SEE Figure 9-2. Keyboard Interrupt Block Diagram) CLRLOGIC RESET CLEAR (CGMXCLK) BUSCLKX4 CLK ACKK RST RESET RESET ISTOP AWUIE Figure 4-1. Auto Wakeup Interrupt Request Generation Logic The auto wakeup RC oscillator is highly dependent on operating voltage and temperature.
Input/Output Registers 4.6 Input/Output Registers The AWU shares registers with the keyboard interrupt (KBI) module and the port A I/O module. The following I/O registers control and monitor operation of the AWU: • Port A data register (PTA) • Keyboard interrupt status and control register (KBSCR) • Keyboard interrupt enable register (KBIER) 4.6.1 Port A I/O Register The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in addition to the data latches for port A.
Auto Wakeup Module (AWU) Bits 7–4 — Not used These read-only bits always read as 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears the KEYF bit. 1 = Keyboard/auto wakeup interrupt pending 0 = No keyboard/auto wakeup interrupt pending ACKK — Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port A and auto wakeup logic. ACKK always reads as 0.Reset clears ACKK.
Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2).
Configuration Register (CONFIG) IRQPUD — IRQ Pin Pullup Control Bit 1 = Internal pullup is disconnected 0 = Internal pullup is connected between IRQ pin and VDD IRQEN — IRQ Pin Function Selection Bit 1 = Interrupt request function active in pin 0 = Interrupt request function inactive in pin OSCOPT1 and OSCOPT0 — Selection Bits for Oscillator Option (0, 0) Internal oscillator (0, 1) External oscillator (1, 0) External RC oscillator (1, 1) External XTAL oscillator RSTEN — RST Pin Function Selection 1 = Reset
Functional Description LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. 1 = LVI module power disabled 0 = LVI module power enabled LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module. The voltage mode selected for the LVI should match the operating VDD for the LVI’s voltage trip points for each of the modes. 1 = LVI operates in 5-V mode 0 = LVI operates in 3-V mode NOTE The LVI5OR3 bit is cleared by a power-on reset (POR) only.
Configuration Register (CONFIG) MC68HC908QY/QT Family Data Sheet, Rev.
Chapter 6 Computer Operating Properly (COP) 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the configuration 1 (CONFIG1) register. 6.
Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 262,128 BUSCLKX4 cycle overflow option, the internal 12.8-MHz oscillator gives a COP timeout period of 20.48 ms.
COP Control Register 6.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register (CONFIG). 6.4 COP Control Register The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Computer Operating Properly (COP) MC68HC908QY/QT Family Data Sheet, Rev.
Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.
Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6.
Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set.
Instruction Set Summary V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
Central Processor Unit (CPU) CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr Clear Interrupt Mask Clear Compare A with M Compare H:X with M Compare X with M DAA Decimal Adjust A Decrement DIV Divide INC opr INCA INCX INC opr,X INC ,X INC opr,SP Exclusive OR M with A Increment – – 0 – – – INH DIR INH INH 0 – – 0 1 – INH IX1 IX SP1 3F dd 4F 5F 8C 6F
Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP PC ← Jump Address DIR EXT – – – – – – IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff 2
Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
Opcode Map V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and keyboard interrupt (KBI), provides a maskable interrupt input 8.2 Features Features of the IRQ module include the following: • External interrupt pin, IRQ • IRQ interrupt control bits • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Selectable internal pullup resistor 8.
External Interrupt (IRQ) PTA0/AD0/TCH0/KBI0 CLOCK GENERATOR (OSCILLATOR) PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 DDRA PTA1/AD1/TCH1/KBI1 SYSTEM INTEGRATION MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU SINGLE INTERRUPT MODULE BREAK MODULE DDRB PTB PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 POWER-ON RESET MODULE 8-BIT ADC 128 BYTES RAM MC68HC908QY4 AND MC68HC908QT4 4096 BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH KEYBOARD INTERRUPT MODULE 16-B
Functional Description ACK INTERNAL ADDRESS BUS RESET TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD IRQPUD INTERNAL PULLUP DEVICE VDD IRQF D CLR Q CK IRQ SYNCHRONIZER IRQ INTERRUPT REQUEST HIGH VOLTAGE DETECT TO MODE SELECT LOGIC IRQ LATCH IMASK MODE Figure 8-2. IRQ Module Block Diagram 8.3.1 MODE = 1 If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive.
External Interrupt (IRQ) 8.4 Interrupts The following IRQ source can generate interrupt requests: • Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests. 8.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 8.5.1 Wait Mode The IRQ module remains active in wait mode.
Registers 8.7.1 IRQ Input Pins (IRQ) The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup device. 8.8 Registers The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. See Chapter 5 Configuration Register (CONFIG).
External Interrupt (IRQ) MC68HC908QY/QT Family Data Sheet, Rev.
Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides six independently maskable external interrupts, which are accessible via the PTA0–PTA5 pins. 9.
Keyboard Interrupt Module (KBI) PTA0/AD0/TCH0/KBI0 CLOCK GENERATOR (OSCILLATOR) PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 DDRA PTA1/AD1/TCH1/KBI1 SYSTEM INTEGRATION MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU SINGLE INTERRUPT MODULE BREAK MODULE DDRB PTB PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 POWER-ON RESET MODULE MC68HC908QY4 AND MC68HC908QT4 4096 BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH 8-BIT ADC 128 BYTES RAM KEYBOARD INTERRUPT MODUL
Functional Description INTERNAL BUS VECTOR FETCH DECODER ACKK KBI0 VDD KBIE0 TO PULLUP ENABLE . . . RESET D CLR KEYF Q SYNCHRONIZER CK KBI5 KEYBOARD INTERRUPT FF IMASKK KEYBOARD INTERRUPT REQUEST MODEK KBIE5 TO PULLUP ENABLE AWUIREQ(1) 1. For AWUGEN logic refer to Figure 4-1. Auto Wakeup Interrupt Request Generation Logic. Figure 9-2.
Keyboard Interrupt Module (KBI) To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and then read the data register. NOTE Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a 0 for software to read the pin. 9.3.
Input/Output Registers To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. 9.7 Input/Output Registers The following I/O registers control and monitor operation of the keyboard interrupt module: • Keyboard interrupt status and control register (KBSCR) • Keyboard interrupt enable register (KBIER) 9.7.
Keyboard Interrupt Module (KBI) 9.7.2 Keyboard Interrupt Enable Register The port A keyboard interrupt enable register (KBIER) enables or disables each port A pin or auto wakeup to operate as a keyboard interrupt input. Address: $001B Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 = Unimplemented Figure 9-4.
Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF. 10.2 Features Features of the LVI module include: • Programmable LVI reset • Programmable power consumption • Selectable LVI trip voltage • Programmable stop mode operation 10.3 Functional Description Figure 10-1 shows the structure of the LVI module.
Low-Voltage Inhibit (LVI) VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, VTRIPF, to be configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, VTRIPF, to be configured for 3-V operation. The actual trip thresholds are specified in 16.5 5-V DC Electrical Characteristics and 16.9 3-V DC Electrical Characteristics.
LVI Status Register 10.4 LVI Status Register The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level while LVI resets have been disabled. Address: $FE0C Read: Bit 7 6 5 4 3 2 1 Bit 0 LVIOUT 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 R = Reserved Write: Reset: = Unimplemented Figure 10-2.
Low-Voltage Inhibit (LVI) MC68HC908QY/QT Family Data Sheet, Rev.
Chapter 11 Oscillator Module (OSC) 11.1 Introduction The oscillator module is used to provide a stable clock source for the microcontroller system and bus. The oscillator module generates two output clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is used by the system integration module (SIM) and the computer operating properly module (COP). The BUSCLKX2 clock is divided by two in the SIM to be used as the bus clock for the microcontroller.
Oscillator Module (OSC) PTA0/AD0/TCH0/KBI0 CLOCK GENERATOR (OSCILLATOR) PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 DDRA PTA1/AD1/TCH1/KBI1 SYSTEM INTEGRATION MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU SINGLE INTERRUPT MODULE BREAK MODULE DDRB PTB PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 POWER-ON RESET MODULE MC68HC908QY4 AND MC68HC908QT4 4096 BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH 8-BIT ADC 128 BYTES RAM KEYBOARD INTERRUPT MODULE 16-BIT
Functional Description 11.3.1.1 Internal Oscillator Trimming The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and –128 steps. Increasing OSCTRIM value increases the clock period. Trimming allows the internal clock frequency to be set to 12.8 MHz ± 5%. All devices are factory programmed with trim values in reserved FLASH memory locations $FFC0 and $FFC1. The trim value is not automatically loaded into the OSCTRIM register.
Oscillator Module (OSC) 11.3.3 XTAL Oscillator The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. The OSC2EN bit in the port A pullup enable register has no effect when this clock mode is selected. In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown in Figure 11-2.
Oscillator Module Signals 11.3.4 RC Oscillator The RC oscillator circuit is designed for use with an external resistor (REXT) to provide a clock source with a tolerance within 25% of the expected frequency. See Figure 11-3. The capacitor (C) for the RC oscillator is internal to the MCU. The REXT value must have a tolerance of 1% or less to minimize its effect on the frequency. In this configuration, the OSC2 pin can be left in the reset state as PTA4.
Oscillator Module (OSC) 11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting amplifier output. For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function. The OSC2EN bit has no effect. For the internal oscillator or RC oscillator options, the OSC2 pin can assume other functions according to Table 1-3. Function Priority in Shared Pins, or the output of the oscillator clock (BUSCLKX4). Table 11-1.
Low Power Modes again in the SIM and results in the internal bus frequency being one fourth of either the XTALCLK, RCCLK, or INTCLK frequency. 11.5 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 11.5.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and BUSCLKX4 continue to drive to the SIM module. 11.5.2 Stop Mode The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK output, hence BUSCLKX2 and BUSCLKX4.
Oscillator Module (OSC) 11.8.1 Oscillator Status Register The oscillator status register (OSCSTAT) contains the bits for switching from internal to external clock sources. Address: $0036 Read: Write: Reset: Bit 7 6 5 4 3 2 1 R R R R R R ECGON 0 0 0 0 0 0 0 R = Reserved Bit 0 ECGST 0 = Unimplemented Figure 11-4.
Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction The MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 have five bidirectional input-output (I/O) pins and one input only pin. The MC68HC908QY1, MC68HC908QY2, and MC68HC908QY4 have thirteen bidirectional pins and one input only pin. All I/O pins are programmable as inputs or outputs. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS.
Input/Output Ports (PORTS) 12.2.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the six port A pins. Address: $0000 Bit 7 Read: 6 AWUL R Write: 5 4 3 PTA5 PTA4 PTA3 Reset: 2 PTA2 1 Bit 0 PTA1 PTA0 KBI1 KBI0 Unaffected by reset KBI5 Additional Functions: R KBI4 KBI3 = Reserved KBI2 = Unimplemented Figure 12-1. Port A Data Register (PTA) PTA[5:0] — Port A Data Bits These read/write bits are software programmable.
Port A Figure 12-3 shows the port A I/O logic. READ DDRA ($0004) PTAPUEx INTERNAL DATA BUS WRITE DDRA ($0004) DDRAx RESET WRITE PTA ($0000) 30 k PTAx PTAx READ PTA ($0000) TO KEYBOARD INTERRUPT CIRCUIT Figure 12-3. Port A I/O Circuit NOTE Figure 12-3 does not apply to PTA2 When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading address $0000 reads the voltage level on the pin.
Input/Output Ports (PORTS) PTAPUE[5:0] — Port A Input Pullup Enable Bits These read/write bits are software programmable to enable pullup devices on port A pins. 1 = Corresponding port A pin configured to have internal pull if its DDRA bit is set to 0 0 = Pullup device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit Table 12-1 summarizes the operation of the port A pins. Table 12-1.
Port B 12.3.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer. Address: $0005 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 12-6.
Input/Output Ports (PORTS) 12.3.3 Port B Input Pullup Enable Register The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRBx bit is configured as output.
Chapter 13 System Integration Module (SIM) 13.1 Introduction This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 13-1. The SIM is a system state controller that coordinates CPU and exception timing.
System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK BUSCLKX4 (FROM OSCILLATOR) BUSCLKX2 (FROM OSCILLATOR) ÷2 VDD INTERNAL PULL-UP RESET PIN LOGIC CLOCK CONTROL CLOCK GENERATORS POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER INTERNAL CLOCKS ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI
Reset and System Initialization FROM OSCILLATOR BUSCLKX4 FROM OSCILLATOR BUSCLKX2 SIM COUNTER BUS CLOCK GENERATORS ÷2 SIM Figure 13-2. SIM Clock Signals 13.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four. 13.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed.
System Integration Module (SIM) 13.4.1 External Pin Reset The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at least the minimum tRL time. Figure 13-3 shows the relative timing. The RST pin function is only available if the RSTEN bit is set in the CONFIG2 register. BUSCLKX2 RST ADDRESS BUS VECT H PC VECT L Figure 13-3. External Reset Timing 13.4.
Reset and System Initialization ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI INTERNAL RESET Figure 13-5. Sources of Internal Reset Table 13-2. Reset Recovery Timing Reset Recovery Type Actual Number of Cycles POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) 13.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles.
System Integration Module (SIM) 13.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12–5 of the SIM counter.
Exception Control 13.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32 BUSCLKX4 cycles.
System Integration Module (SIM) FROM RESET BREAK INTERRUPT? I BIT SET? YES NO YES I BIT SET? NO IRQ INTERRUPT? YES NO TIMER INTERRUPT? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR (AS MANY INTERRUPTS AS EXIST ON CHIP) FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 13-7. Interrupt Processing MC68HC908QY/QT Family Data Sheet, Rev.
Exception Control MODULE INTERRUPT I BIT ADDRESS BUS DUMMY DATA BUS SP DUMMY SP – 1 SP – 2 PC – 1[7:0] PC – 1[15:8] SP – 3 X SP – 4 A VECT H CCR VECT L V DATA H START ADDR V DATA L OPCODE R/W Figure 13-8. Interrupt Entry MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS SP – 3 CCR SP – 2 A SP – 1 X SP PC PC + 1 PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND R/W Figure 13-9. Interrupt Recovery 13.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction.
System Integration Module (SIM) CLI LDA #$FF INT1 BACKGROUND ROUTINE PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 13-10. Interrupt Recognition Example 13.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack.
Exception Control 13.6.2.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 IF5 IF4 IF3 0 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 13-11. Interrupt Status Register 1 (INT1) IF1 and IF3–IF5 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 13-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1, 3, and 7 — Always read 0 13.6.2.
System Integration Module (SIM) 13.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 13.6.4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output. (See Chapter 15 Development Support.) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
Low-Power Modes A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset (or break in emulation mode).
System Integration Module (SIM) The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 13-17 shows stop mode entry timing and Figure 13-18 shows the stop mode recovery time from interrupt or break. NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
SIM Registers 13.8.1 SIM Reset Status Register The SRSR register contains flags that show the source of the last reset. The status register will automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the register. All other reset sources set the individual flag bits but do not clear the register. More than one reset source can be flagged at any time depending on the conditions at the time of the internal or external reset.
System Integration Module (SIM) 13.8.2 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 13-20.
Chapter 14 Timer Interface Module (TIM) 14.1 Introduction This section describes the timer interface module (TIM). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 14-2 is a block diagram of the TIM. 14.
Timer Interface Module (TIM) PTA0/AD0/TCH0/KBI0 CLOCK GENERATOR (OSCILLATOR) PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 DDRA PTA1/AD1/TCH1/KBI1 SYSTEM INTEGRATION MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU SINGLE INTERRUPT MODULE BREAK MODULE DDRB PTB PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 POWER-ON RESET MODULE MC68HC908QY4 AND MC68HC908QT4 4096 BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH 8-BIT ADC 128 BYTES RAM KEYBOARD INTERRUPT MODULE 1
Functional Description 14.4 Functional Description Figure 14-2 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence.
Timer Interface Module (TIM) 14.4.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source. 14.4.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs.
Functional Description control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE In buffered output compare operation, do not write new output compare values to the currently active channel registers.
Timer Interface Module (TIM) 14.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 14.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods.
Interrupts 14.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3.
Timer Interface Module (TIM) 14.6 Wait Mode The WAIT instruction puts the MCU in low power-consumption standby mode. The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 14.
Input/Output Registers 14.9.1 TIM Status and Control Register The TIM status and control register (TSC) does the following: • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter clock Address: $0020 Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Unimplemented Figure 14-4.
Timer Interface Module (TIM) TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as a 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000.
Input/Output Registers 14.9.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Timer Interface Module (TIM) Address: $0025 Bit 7 TSC0 6 5 4 3 2 1 Bit 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 5 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 Read: CH0F Write: 0 Reset: 0 0 Address: $0028 TSC1 Bit 7 Read: CH1F Write: 0 Reset: 0 6 CH1IE 0 0 0 = Unimplemented Figure 14-7.
Input/Output Registers When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 14-3). Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). Table 14-3.
Timer Interface Module (TIM) CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at a 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 14-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
Chapter 15 Development Support 15.1 Introduction This section describes the break module, the monitor read-only memory (MON), and the monitor mode entry methods. 15.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
Development Support PTA0/AD0/TCH0/KBI0 CLOCK GENERATOR (OSCILLATOR) PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 DDRA PTA1/AD1/TCH1/KBI1 SYSTEM INTEGRATION MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB SINGLE INTERRUPT MODULE BREAK MODULE DDRB PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 POWER-ON RESET MODULE MC68HC908QY4 AND MC68HC908QT4 4096 BYTES MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, AND MC68HC908QT1: 1536 BYTES USER FLASH 8-BIT ADC 128 BYTES RAM KEYBOARD INTERRUPT MODULE 16-BIT TIM
Break Module (BRK) When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not executed
Development Support 15.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0B Read: Write: Reset: Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 15-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit.
Break Module (BRK) 15.2.2.3 Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU is in a state of break interrupt with monitor mode. Address: $FE02 Read: Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: Bit 0 BDCOP 0 = Unimplemented Figure 15-6. Break Auxiliary Register (BRKAR) BDCOP — Break Disable COP Bit This read/write bit disables the COP during a break interrupt.
Development Support 15.2.2.5 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 15-8. Break Flag Control Register (BFCR) BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state.
Monitor Module (MON) 15.3.1 Functional Description Figure 15-9 shows a simplified diagram of monitor mode entry. The monitor module receives and executes commands from a host computer. Figure 15-10, Figure 15-11, and Figure 15-12 show example circuits used to enter monitor mode and communicate with a host computer via a standard RS-232 interface.
Development Support VDD VDD 10 kΩ* VDD RST (PTA3) MAX232 1 1 μF + 3 4 1 μF + VDD 16 C1+ + 7 10 8 9 VDD 1 kΩ PTA1 9.1 V 10 kΩ + PTA4 74HC125 5 6 74HC125 3 2 10 kΩ* PTA0 4 VSS 1 5 10 kΩ* IRQ (PTA2) VDD V– 6 DB9 3 1 μF V+ 2 1 μF OSC1 (PTA5) VTST + C2+ 0.1 μF 1 μF 15 C1– 5 C2– 2 9.8304 MHz CLOCK * Value not critical Figure 15-10. Monitor Mode Circuit (External Clock, with High Voltage) VDD N.C. 1 1 μF 3 4 1 μF + C1+ C1– C2+ 5 C2– VDD 16 + 3 5 9.
Monitor Module (MON) VDD N.C. RST (PTA3) VDD 0.1 μF MAX232 1 1 μF + 3 4 1 μF + C1+ C1– C2+ 5 C2– VDD + 3 1 μF 15 + OSC1 (PTA5) IRQ (PTA2) 1 μF VDD V– 6 1 μF 7 10 8 9 10 kΩ 74HC125 5 6 + 74HC125 3 2 PTA1 N.C. PTA4 N.C. 10 kΩ* V+ 2 DB9 2 N.C. 16 PTA0 VSS 4 1 5 * Value not critical Figure 15-12. Monitor Mode Circuit (Internal Clock, No High Voltage) Simple monitor commands can access any memory address.
Development Support Table 15-1. Monitor Mode Signal Requirements and Options Mode Serial Mode CommuniSelection RST Reset IRQ cation (PTA2) (PTA3) Vector PTA0 PTA1 PTA4 Communication Speed COP External Bus Clock Frequency Comments Baud Rate VTST VDD X 1 1 0 Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VDD X $FFFF (blank) 1 X X Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VSS X $FFFF (blank) 1 X X Disabled X 3.
Monitor Module (MON) If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to IRQ. 15.3.1.2 Forced Monitor Mode If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit programming.
Development Support Table 15-2. Mode Difference Functions Modes Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD 15.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
Monitor Module (MON) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE Wait one bit time after each echo before sending the next byte.
Development Support Table 15-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE WRITE ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 15-5.
Monitor Module (MON) Table 15-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 15-8.
Development Support 15.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
Chapter 16 Electrical Specifications 16.1 Introduction This section contains electrical and timing specifications. 16.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 16.5 5-V DC Electrical Characteristics and 16.9 3-V DC Electrical Characteristics for guaranteed operating conditions.
Electrical Specifications 16.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit Temp. Code TA – 40 to +125 – 40 to +105 – 40 to +85 •C M V C VDD 2.7 to 5.5 V — 16.
5-V DC Electrical Characteristics 16.5 5-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.4 VDD –1.5 VDD –0.8 — — — — — — — — 50 — — — — — — 0.4 1.5 0.8 Unit Output high voltage ILoad = –2.0 mA, all I/O pins ILoad = –10.0 mA, all I/O pins ILoad = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 1.6 mA, all I/O pins ILoad = 10.0 mA, all I/O pins ILoad = 15.
Electrical Specifications 16.6 Typical 5-V Output Drive Characteristics 2.0 VDD-VOH (V 1.5 5V PTA 1.0 5V PTB 0.5 0.0 0 -5 -10 -15 -20 -25 -30 -35 IOH (mA) Figure 16-1. Typical 5-Volt Output High Voltage versus Output High Current (25•C) 2.0 VOL (V 1.5 5V PTA 5V PTB 1.0 0.5 0.0 0 5 10 15 20 25 30 35 IOL (mA) Figure 16-2. Typical 5-Volt Output Low Voltage versus Output Low Current (25•C) MC68HC908QY/QT Family Data Sheet, Rev.
5-V Control Timing 16.7 5-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBus) — 8 MHz Internal clock period (1/fOP) tcyc 125 — ns RST input pulse width low tRL 100 — ns IRQ interrupt pulse width low (edge-triggered) tILIH 100 — ns IRQ interrupt pulse period tILIL Note(2) — tcyc 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2.
Electrical Specifications 16.8 5-V Oscillator Characteristics Characteristic Symbol Min Typ Max Unit fINTCLK — 12.8 — MHz — — — ± 0.4 ±2 — — — ±5 fOSCXCLK 1 — 24 MHz fRCCLK 2 — 12 MHz fOSCXCLK dc — 32 MHz Crystal load capacitance(5) CL — 20 — pF Crystal fixed capacitance(3) C1 — 2 x CL — — Crystal tuning capacitance(3) C2 — 2 x CL — — Feedback bias resistor RB 0.5 1 10 MΩ Internal oscillator frequency(1) Deviation from trimmed Internal oscillator 12.
3-V DC Electrical Characteristics 16.9 3-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.3 VDD –1.0 VDD –0.8 — — — — — — — — 50 — — — — — — 0.3 1.0 0.8 Unit Output high voltage ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 0.5 mA, all I/O pins ILoad = 6.0 mA, all I/O pins ILoad = 10.
Electrical Specifications 16.10 Typical 3.0-V Output Drive Characteristics VDD-VOH (V 1.5 1.0 3V PTA 3V PTB 0.5 0.0 0 -5 -10 -15 -20 IOH (mA) Figure 16-5. Typical 3-Volt Output High Voltage versus Output High Current (25•C) 1.5 VOL (V 1.0 3V PTA 3V PTB 0.5 0.0 0 5 10 15 20 IOL (mA) Figure 16-6. Typical 3-Volt Output Low Voltage versus Output Low Current (25•C) MC68HC908QY/QT Family Data Sheet, Rev.
3-V Control Timing 16.11 3-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBus) — 4 MHz Internal clock period (1/fOP) tcyc 250 — ns RST input pulse width low tRL 200 — ns IRQ interrupt pulse width low (edge-triggered) tILIH 200 — ns — tcyc tILIL IRQ interrupt pulse period (2) Note 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2.
Electrical Specifications 16.12 3-V Oscillator Characteristics Characteristic Symbol Min Typ Max Unit fINTCLK — 12.8 — MHz — — — ± 0.4 ±2 — — — ±5 fOSCXCLK 1 — 16 MHz fRCCLK 2 — 10 MHz fOSCXCLK dc — 16 MHz Crystal load capacitance(5) CL — 20 — pF Crystal fixed capacitance(3) C1 — 2 x CL — — Crystal tuning capacitance(3) C2 — 2 x CL — — Feedback bias resistor RB 0.5 1 10 MΩ Internal oscillator frequency(1) Deviation from trimmed Internal oscillator 12.
Supply Current Characteristics 16.13 Supply Current Characteristics Voltage Bus Frequency (MHz) Symbol Typ(2) Max Unit Run Mode VDD supply current(3) 5.0 3.0 3.2 3.2 RIDD 6.0 2.5 7.0 3.2 mA Wait Mode VDD supply current(4) 5.0 3.0 3.2 3.2 WIDD 1.0 0.67 1.5 1.0 mA mA 0.04 — — 7 125 1.0 2.0 5.0 — — 0.02 — — 5 100 0.5 1.0 4.
Electrical Specifications 14 12 IDD (mA 10 Crystal w/o ADC 8 Crystal w/ ADC 6 4 Internal Osc w/o ADC 2 Internal Osc w/ ADC 0 0 1 2 3 4 5 6 7 Bus Frequency (MHz) Figure 16-9. Typical 5-Volt Run Current versus Bus Frequency (25•C) 4 IDD (mA 3 Crystal w/o ADC 2 Crystal w/ ADC Internal Osc w/o ADC 1 Internal Osc w/ ADC 0 0 1 2 3 4 5 Bus Frequency (MHz) Figure 16-10. Typical 3-Volt Run Current versus Bus Frequency (25•C) MC68HC908QY/QT Family Data Sheet, Rev.
Analog-to-Digital Converter Characteristics 16.14 Analog-to-Digital Converter Characteristics Characteristic Symbol Min Max Unit Comments Supply voltage VDDAD 2.7 (VDD min) 5.5 (VDD max) V — Input voltages VADIN VSS VDD V — Resolution (1 LSB) RES 10.5 21.5 mV — Absolute accuracy (Total unadjusted error) ETUE — ± 1.5 LSB Includes quantization ADC internal clock fADIC 0.5 1.
Electrical Specifications 16.15 Timer Interface Module Characteristics Characteristic Symbol Min Max Unit tTH, tTL 2 — tcyc tTLTL Note(1) — tcyc tTCL, tTCH tcyc + 5 — ns Timer input capture pulse width Timer input capture period Timer input clock pulse width 1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
Memory Characteristics 16.16 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz fRead(1) 0 — 8M Hz FLASH page erase time <1 k cycles >1 k cycles tErase 0.9 3.6 1 4 1.1 5.
Electrical Specifications MC68HC908QY/QT Family Data Sheet, Rev.
Chapter 17 Ordering Information and Mechanical Specifications 17.1 Introduction This section contains order numbers for the MC68HC908QY1, MC68HC908QY2, MC68HC908QY4, MC68HC908QT1, MC68HC908QT2, and MC69HC908QT4. Dimensions are given for: • 8-pin plastic dual in-line package (PDIP) • 8-pin small outline integrated circuit (SOIC) package • 8-pin dual flat no lead (DFN) package • 16-pin PDIP • 16-pin SOIC • 16-pin thin shrink small outline package (TSSOP) 17.2 MC Order Numbers Table 17-1.
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