MC68HC908AP64 MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 Data Sheet M68HC08 Microcontrollers MC68HC908AP64 Rev. 4 01/2007 freescale.
MC68HC908AP64 MC68HC908AP32 MC68HC908AP16 MC68HC908AP8 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History Date Revision Level Description Page Number(s) January 2007 4 15.7.2 ADC Clock Control Register — Changed “The ADC clock should be set to between 500kHz and 2MHz” to “The ADC clock should be set to between 500kHz and 1MHz” 254 Table 22-4 . DC Electrical Characteristics (5V) — Updated VOL values. 299 Table 22-6 . Oscillator Specifications (5V) and Table 22-10 . Oscillator Specifications (3V) — Corrected internal oscillator clock frequency, fICLK.
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR) . . . . . . . . . . . . . . . .49 Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Chapters MC68HC908AP Family Data Sheet, Rev.
Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . .
Table of Contents 4.3.2 4.3.3 4.3.4 4.3.5 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.8 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . .
6.3.9 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.6 6.7 6.7.1 6.7.2 6.7.3 6.8 6.8.1 6.8.2 6.8.3 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 7.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.4.
Table of Contents 11.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 13.12.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.13.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.13.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . .
.3 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.3.6 15.3.7 15.3.8 15.4 15.5 15.5.1 15.5.2 15.6 15.6.1 15.6.2 15.6.3 15.6.4 15.6.5 15.7 15.7.1 15.7.2 15.7.3 15.7.4 15.7.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 17.3 17.4 17.5 17.6 17.6.1 17.6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ1 and IRQ2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2 20.3 20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.4 20.5 20.6 20.6.1 20.6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low VDD Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low VREG Detector . . . . . . . . .
Table of Contents 22.13 22.14 22.15 22.16 22.17 MMIIC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V SPI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V SPI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 General Description 1.1 Introduction The MC68HC908AP64 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. Table 1-1.
General Description • • • • • • • • • • • • • • • Timebase module Serial communications interface module 1 (SCI) Serial communications interface module 2 (SCI) with infrared (IR) encoder/decoder Serial peripheral interface module (SPI) System management bus (SMBus), version 1.0/1.
MCU Block Diagram PORTA PTA7/ADC7 ‡ PTA6/ADC6 ‡ PTA5/ADC5 ‡ PTA4/ADC4 ‡ PTA3/ADC3 ‡ PTA2/ADC2 ‡ PTA1/ADC1 ‡ PTA0/ADC0 ‡ PORTB PTB7/T2CH1 PTB6/T2CH0 PTB5/T1CH1 PTB4/T1CH0 PTB3/RxD † PTB2/TxD † PTB1/SCL † PTB0/SDA † PORTC PTC7/SCRxD † PTC6/SCTxD † PTC5/SPSCK PTC4/SS PTC3/MOSI PTC2/MISO PTC1 # PTC0/IRQ2 **# PORTD INTERNAL BUS PTD7/KBI7 *** PTD6/KBI6 *** PTD5/KBI5 *** PTD4/KBI4 *** PTD3/KBI3 *** PTD2/KBI2 *** PTD1/KBI1 *** PTD0/KBI0 *** M68HC08 CPU ARITHMETIC/LOGIC UNIT (ALU) CONTROL AND STATUS REGIS
General Description PTD0/KBI0 PTD1/KBI1 PTD2/KBI2 VDDA VSSA PTD3/KBI3 PTD4/KBI4 PTD5/KBI5 PTD6/KBI6 46 45 44 43 42 41 40 39 38 37 PTD7/KBI7 PTB7/T2CH1 PTB6/T2CH0 1 47 48 CGMXFC 1.
PTD0/KBI0 PTD1/KBI1 PTD2/KBI2 VDDA VSSA PTD3/KBI3 PTD4/KBI4 PTD5/KBI5 42 41 40 39 38 37 36 35 34 PTD6/KBI6 PTB7/T2CH1 PTB6/T2CH0 1 43 44 CGMXFC Pin Assignment 33 PTD7/KBI7 28 PTA2/ADC2 VSS 7 27 PTA3/ADC3 PTB4/T1CH0 8 26 PTA4/ADC4 IRQ1 9 25 PTA5/ADC5 10 24 PTA6/ADC6 PTB2/TxD 12 RST 11 23 PTA7/ADC7 PTC0/IRQ2 22 PTB3/RxD 21 6 PTC1 OSC2 20 PTA1/ADC1 PTC2/MISO 29 19 5 PTC3/MOSI OSC1 18 PTA0/ADC0 PTC4/SS 30 17 4 PTC5/SPSCK VDD 16 VREFL PTC6/SCTxD
General Description PTD2/KBI2 1 42 VDDA PTD1/KBI1 2 41 VSSA PTD0/KBI0 3 40 PTD3/KBI3 PTB7/T2CH1 4 39 PTD4/KBI4 CGMXFC 5 38 PTD5/KBI5 PTB6/T2CH0 6 37 PTD6/KBI6 VREG 7 36 PTD7/KBI7 PTB5/T1CH1 8 35 VREFH VDD 9 34 VREFL OSC1 10 33 PTA0/ADC0 OSC2 11 32 PTA1/ADC1 VSS 12 31 PTA2/ADC2 PTB4/T1CH0 13 30 PTA3/ADC3 IRQ1 14 29 PTA4/ADC4 PTB3/RxD 15 28 PTA5/ADC5 RST 16 27 PTA6/ADC6 PTB2/TxD 17 26 PTA7/ADC7 PTB1/SCL 18 25 PTC2/MISO PTB0/SDA 19 24
Pin Functions 1.5 Pin Functions Description of the pin functions are provided in Table 1-2. Table 1-2. Pin Functions PIN NAME PIN DESCRIPTION IN/OUT VOLTAGE LEVEL In 4.5 to 5.5 or 2.7 to 3.3 Out 0V In VDD Out VSS VDD Power supply. VSS Power supply ground. VDDA Power supply for analog circuits. VSSA Power supply ground for analog circuits. VREFH ADC input reference high. In VDDA VREFL ADC input reference low. Out VSSA VREG Internal (2.5V) regulator output.
General Description Table 1-2. Pin Functions PIN DESCRIPTION IN/OUT VOLTAGE LEVEL 8-bit general purpose I/O port; PTB0–PTB3 are open drain when configured as output. PTB4–PTB7 have schmitt trigger inputs. In/Out VDD PTB0 as SDA of MMIIC. In/Out VDD PTB1 as SCL of MMIIC. In/Out VDD Out VDD In VDD PTB4 as T1CH0 of TIM1. In/Out VDD PTB5 as T1CH1 of TIM1. In/Out VDD PTB6 as T2CH0 of TIM2. In/Out VDD PTB7 as T2CH1 of TIM2.
Regulator Power Supply Configuration (VREG) VDDA and VSSA are the power supply and ground pins for the analog circuits of the MCU. These pins should be decoupled as per the digital power supply pins. MCU VDD VSS VDDA C1(a) 0.1 µF VSSA C1(b) 0.1 µF + + C2(a) C2(b) VDD VDD NOTE: Component values shown represent typical applications. Figure 1-5. Power Supply Bypassing 1.7 Regulator Power Supply Configuration (VREG) VREG is the output from the on-chip regulator.
General Description MC68HC908AP Family Data Sheet, Rev.
Chapter 2 Memory 2.1 Introduction The CPU08 can address 64k-bytes of memory space. The memory map, shown in Figure 2-1, includes: • 62,368 bytes of user FLASH — MC68HC908AP64 32,768 bytes of user FLASH — MC68HC908AP32 16,384 bytes of user FLASH — MC68HC908AP16 8,192 bytes of user FLASH — MC68HC908AP8 • 2,048 bytes of RAM — MC68HC908AP64 and MC68HC908AP32 1,024 bytes of RAM — MC68HC908AP16 and MC68HC908AP8 • 48 bytes of user-defined vectors • 959 bytes of monitor ROM 2.
Memory $0000 ↓ $005F $0060 ↓ $085F $0860 I/O Registers 96 Bytes MC68HC908AP32 RAM 2,048 Bytes (MC68HC908AP64) RAM 2,048 Bytes MC68HC908AP16 $0060 ↓ $085F $0860 RAM 1,024 Bytes Unimplemented 1,024 Bytes ↓ FLASH Memory 62,368 Bytes (MC68HC908AP64) ↓ $885F $8860 Unimplemented 29,600 Bytes RAM 1,024 Bytes Unimplemented 1,024 Bytes FLASH Memory 8,192 Bytes $0060 $045F $0860 $285F $2860 $485F $4860 ↓ Unimplemented 45,984 Bytes $FBFF $FC00 ↓ $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07
Monitor ROM Addr.
Memory Addr.
Monitor ROM Addr.
Memory Addr.
Monitor ROM Addr.
Memory Addr.
Monitor ROM Addr.
Memory Addr.
Monitor ROM Addr.
Memory Table 2-1.
Random-Access Memory (RAM) Table 2-1.
Memory NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables.
FLASH Memory 2.5.2 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operation. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 Figure 2-3. FLASH Control Register (FLCR) HVEN — High Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array.
Memory 6. 7. 8. 9. Clear the ERASE bit. Wait for a time, tnvh (5 µs). Clear the HVEN bit. After time, trcv (1 µs), the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.5.4 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory: 1.
FLASH Memory 10. Wait for time, tnvh (5 µs). 11. Clear the HVEN bit. 12. After time, trcv (1 µs), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed. NOTE The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 6 to step 9), must not exceed the maximum programming time, tprog max.
Memory 1 Set PGM bit Algorithm for programming a row (64 bytes) of FLASH memory 2 3 4 5 6 7 Write any data to any FLASH address within the row address range desired Wait for a time, tnvs Set HVEN bit Wait for a time, tpgs Write data to the FLASH address to be programmed Wait for a time, tprog Completed programming this row? Y N NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step 9) mus
FLASH Memory 2.5.7 FLASH Block Protect Register The FLASH block protect register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the FLASH memory. Address: $FE09 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 0 0 0 0 0 0 0 0 Reset: Figure 2-5.
Memory MC68HC908AP Family Data Sheet, Rev.
Chapter 3 Configuration & Mask Option Registers (CONFIG & MOR) 3.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option register, MOR.
Configuration & Mask Option Registers (CONFIG & MOR) 3.2 Functional Description The configuration registers and the mask option register are used in the initialization of various options. These two types of registers are configured differently: • Configuration registers — Write-once registers after reset • Mask option register — FLASH register (write by programming) The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset.
Configuration Register 1 (CONFIG1) LVIPWRD — VDD LVI Circuit Disable Bit LVIPWRD disables the VDD LVI circuit. (See Chapter 20 Low-Voltage Inhibit (LVI).) 1 = VDD LVI circuit disabled 0 = VDD LVI circuit enabled LVIREGD — VREG LVI Circuit Disable Bit LVIREGD disables the VREG LVI circuit. (See Chapter 20 Low-Voltage Inhibit (LVI).) 1 = VREG LVI circuit disabled 0 = VREG LVI circuit enabled NOTE If LVIPWRD=1 and LVIREGD=1, set LVIRSTD=1 before entering stop mode.
Configuration & Mask Option Registers (CONFIG & MOR) 3.4 Configuration Register 2 (CONFIG2) Address: $001D Bit 7 6 5 Write: STOP_ ICLKDIS STOP_ RCLKEN STOP_ XCLKEN Reset: 0 0 0 Read: 4 3 OSCCLK1 OSCCLK0 0 0 2 1 Bit 0 0 0 SCIBDSRC 0 0 0 Figure 3-3. Configuration Register 2 (CONFIG2) STOP_ICLKDIS — Internal Oscillator Stop Mode Disable STOP_ICLKDIS disables the internal oscillator during stop mode. Setting the STOP_ICLKDIS bit disables the oscillator during stop mode.
Mask Option Register (MOR) SCIBDSRC — SCI Baud Rate Clock Source SCIBDSRC selects the clock source used for the standard SCI module (non-infrared SCI). The setting of this bit affects the frequency at which the SCI operates. 1 = Internal data bus clock, fBUS, is used as clock source for SCI 0 = Oscillator clock, CGMXCLK, is used as clock source for SCI 3.5 Mask Option Register (MOR) The mask option register (MOR) is used for selecting one of the three clock options for the MCU.
Configuration & Mask Option Registers (CONFIG & MOR) MC68HC908AP Family Data Sheet, Rev.
Chapter 4 Central Processor Unit (CPU) 4.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 4.
Central Processor Unit (CPU) 4.3 CPU Registers Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR (A) 15 0 H X INDEX REGISTER (H:X) 0 15 STACK POINTER (SP) 0 15 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 4-1. CPU Registers 4.3.1 Accumulator The accumulator is a general-purpose 8-bit register.
CPU Registers Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 X X X X X X X X Read: Write: Reset: X = Indeterminate Figure 4-3. Index Register (H:X) 4.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte.
Central Processor Unit (CPU) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF Figure 4-5. Program Counter (PC) 4.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register.
Arithmetic/Logic Unit (ALU) After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI).
Central Processor Unit (CPU) 4.6 CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
Opcode Map V H I N Z C AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP A ← (A) & (M) Logical AND Arithmetic Shift Left (Same as LSL) ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP Arithmetic Shift Right BCC rel Branch if Carry Bit Clear C 0 b7 b0 C b7 b0 PC ← (PC) + 2 + rel ? (C) = 0 Mn ← 0 Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 4-1.
Central Processor Unit (CPU) V H I N Z C BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) BLO rel Branch if Lower (Same as BCS) BLS rel (A) & (M) IMM DIR EXT IX2 0 – – o o – IX1 IX SP1 SP2 PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V)=1 – – – – – – REL A5 B5 C5 D5 E5 F5 9EE5 9ED5 ii dd hh ll ee ff ff Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 4-1.
Opcode Map V H I N Z C BSR rel PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) + rel Branch to Subroutine CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel – – – – – – REL PC ← (PC) + 3 + rel ? (A) – (M) = $00 DIR PC ← (PC) + 3 + rel ? (A) – (M) = $00 IMM PC ← (PC) + 3 + rel ? (X) – (M) = $00 IMM – – – – – – PC ← (PC) + 3 + rel ? (A) – (M) = $00 IX1+ PC ← (PC) + 2 + rel ? (A) – (M) = $00 IX+ PC ← (PC) + 4 + r
Central Processor Unit (CPU) V H I N Z C DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP Decrement DIV Divide EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Exclusive OR M with A Increment Jump Jump to Subroutine LDA #opr LDA opr LDA opr
Opcode Map V H I N Z C LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP IMM DIR EXT IX2 0 – – o o – IX1 IX SP1 SP2 AE BE CE DE EE FE 9EEE 9EDE ii dd hh ll ee ff ff DIR INH INH o – – o o o IX1 IX SP1 38 48 58 68 78 9E68 dd DIR INH INH o – – 0 o o IX1 IX SP1 34 44 54 64 74 9E64 dd H:X ← (H:X) + 1 (IX+D, DIX+) DD DIX+ 0 – – o o – IMD IX+D 4E 5E 6E 7E X:A ← (X) × (A) – 0 – – – 0 IN
Central Processor Unit (CPU) V H I N Z C Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 4-1.
Opcode Map V H I N Z C STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP M ← (X) Store X in M A ← (A) – (M) Subtract Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 4-1.
Central Processor Unit (CPU) V H I N Z C A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed,
Freescale Semiconductor Table 4-2.
Central Processor Unit (CPU) MC68HC908AP Family Data Sheet, Rev.
Chapter 5 Oscillator (OSC) 5.1 Introduction The oscillator module consist of three types of oscillator circuits: • Internal oscillator • RC oscillator • 32.768kHz crystal (x-tal) oscillator The reference clock for the CGM and other MCU sub-systems is selected by programming the mask option register located at $FFCF. The reference clock for the timebase module (TBM) is selected by the two bits, OSCCLK1 and OSCCLK0, in the CONFIG2 register.
Oscillator (OSC) To CGM and others To CGM PLL CGMXCLK To TBM CGMRCLK OSCCLK MOR CONFIG2 OSCSEL1 OSCCLK1 MUX MUX OSCSEL0 OSCCLK0 X RC I X RC I To SIM (and COP) XCLK ICLK RCCLK X-TAL OSCILLATOR RC OSCILLATOR INTERNAL OSCILLATOR BUS CLOCK OSC1 From SIM OSC2 Figure 5-1. Oscillator Module Block Diagram 5.2.1 CGM Reference Clock Selection The clock generator module (CGM) reference clock (CGMXCLK) is the reference clock input to the MCU.
Clock Selection Table 5-1. CGMXCLK Clock Selection OSCSEL1 OSCSEL0 CGMXCLK OSC2 Pin Comments 0 0 — — 0 1 ICLK fBUS Internal oscillator generates the CGMXCLK. 1 0 RCCLK fBUS RC oscillator generates the CGMXCLK. Internal oscillator is available after each POR or reset. 1 1 XCLK Inverting output of X-TAL X-tal oscillator generates the CGMXCLK. Internal oscillator is available after each POR or reset.
Oscillator (OSC) 5.3 Internal Oscillator The internal oscillator clock (ICLK), with a frequency of fICLK, is a free running clock that requires no external components. It can be selected as the CGMXCLK for the CGM and MCU sub-systems; and the OSCCLK clock for the TBM. The ICLK is also the reference clock input to the computer operating properly (COP) module. Due to the simplicity of the internal oscillator, it does not have the accuracy and stability of the RC oscillator or the x-tal oscillator.
RC Oscillator 5.4 RC Oscillator The RC oscillator circuit is designed for use with an external resistor and a capacitor. In its typical configuration, the RC oscillator requires two external components, one R and one C. Component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance.
Oscillator (OSC) From SIM To Clock Selection MUX SIMOSCEN XCLK CONFIG2 STOP_XCLKEN MCU OSC1 OSC2 RB RS X1 See Chapter 22 for component value requirements. C1 32.768kHz C2 Figure 5-6. Crystal Oscillator The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information. 5.
Low Power Modes 5.6.4 CGM Oscillator Clock (CGMXCLK) The CGMXCLK clock is output from the x-tal oscillator, RC oscillator or the internal oscillator. This clock drives to CGM and other MCU sub-systems. 5.6.5 CGM Reference Clock (CGMRCLK) This is buffered signal of CGMXCLK, it is used by the CGM as the phase-locked-loop (PLL) reference clock. 5.6.6 Oscillator Clock to Time Base Module (OSCCLK) The OSCCLK is the reference clock that drives the timebase module. See Chapter 10 Timebase Module (TBM). 5.
Oscillator (OSC) MC68HC908AP Family Data Sheet, Rev.
Chapter 6 Clock Generator Module (CGM) 6.1 Introduction This section describes the clock generator module (CGM). The CGM generates the base clock signal, CGMOUT, which is based on either the oscillator clock divided by two or the divided phase-locked loop (PLL) clock, CGMPCLK, divided by two. CGMOUT is the clock from which the SIM derives the system clocks, including the bus clock, which is at a frequency of CGMOUT 2.
Clock Generator Module (CGM) OSC2 OSC1 OSCILLATOR (OSC) MODULE See Chapter 5 Oscillator (OSC).
Functional Description Addr.
Clock Generator Module (CGM) • • • Phase detector Loop filter Lock detector The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range.
Functional Description 6.3.5 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. Automatic mode is recommended for most users. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 6.5.
Clock Generator Module (CGM) 1. Choose the desired bus frequency, fBUSDES, or the desired VCO frequency, fVCLKDES; and then solve for the other. The relationship between fBUS and fVCLK is governed by the equation: P P f VCLK = 2 × f CGMPCLK = 2 × 4 × fBUS where P is the power of two multiplier, and can be 0, 1, 2, or 3 2. Choose a practical PLL reference frequency, fRCLK, and the reference clock divider, R. Typically, the reference is 32.768kHz and R = 1.
Functional Description 5. Select the VCO’s power-of-two range multiplier E, according to this table: Frequency Range E 0 < fVCLK < 9,830,400 0 9,830,400 ≤ fVCLK < 19,660,800 1 19,660,800 ≤ fVCLK < 39,321,600 2 NOTE: Do not program E to a value of 3. 6. Select a VCO linear range multiplier, L, where fNOM = 125kHz ⎛ f VCLK ⎞ L = round ⎜ -------------------------⎟ ⎝ 2E × f ⎠ NOM 7. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS.
Clock Generator Module (CGM) Table 6-1. Numeric Examples CGMVCLK CGMPCLK fBUS fRCLK R N P E L 8.0 MHz 8.0 MHz 2.0 MHz 32.768 kHz 1 F5 0 0 40 9.8304 MHz 9.8304 MHz 2.4576 MHz 32.768 kHz 1 12C 0 1 27 10.0 MHz 10.0 MHz 2.5 MHz 32.768 kHz 1 132 0 1 28 16 MHz 16 MHz 4.0 MHz 32.768 kHz 1 1E9 0 1 40 19.6608 MHz 19.6608 MHz 4.9152 MHz 32.768 kHz 1 258 0 2 27 20 MHz 20 MHz 5.0 MHz 32.768 kHz 1 263 0 2 28 29.4912 MHz 29.4912 MHz 7.3728 MHz 32.
I/O Signals 6.3.9 CGM External Connections In its typical configuration, the CGM requires up to four external components. Figure 6-3 shows the external components for the PLL: • Bypass capacitor, CBYP • Filter network Care should be taken with PCB routing in order to minimize signal cross talk and noise. (See 6.8 Acquisition/Lock Time Specifications for routing information, filter network and its effects on PLL performance.) MCU CGMXFC VSSA VDDA VDD 1 kΩ 10 nF CBYP 0.1 µF 0.
Clock Generator Module (CGM) 6.4.3 PLL Analog Ground Pin (VSSA) VSSA is a ground pin used by the analog portions of the PLL. Connect the VSSA pin to the same voltage potential as the VSS pin. NOTE Route VSSA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 6.4.4 Oscillator Output Frequency Signal (CGMXCLK) CGMXCLK is the oscillator output signal.
CGM Registers 6.5.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: $0036 Bit 7 Read: Write: Reset: PLLIE 0 6 PLLF 0 5 4 3 2 1 Bit 0 PLLON BCS PRE1 PRE0 VPR1 VPR0 1 0 0 0 0 0 = Unimplemented Figure 6-4.
Clock Generator Module (CGM) NOTE PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMPCLK requires two writes to the PLL control register. (See 6.3.8 Base Clock Selector Circuit.
CGM Registers 6.5.
Clock Generator Module (CGM) 6.5.3 PLL Multiplier Select Registers The PLL multiplier select registers (PMSH and PMSL) contain the programming information for the modulo feedback divider. Address: Read: $0038 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 MUL11 MUL10 MUL9 MUL8 0 0 0 0 = Unimplemented Figure 6-6.
Interrupts register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 6.3.8 Base Clock Selector Circuit and 6.3.7 Special Programming Exceptions.). Reset initializes the register to $40 for a default range multiply value of 64. NOTE The VCO range select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected as the source of the base clock (BCS = 1) if the VCO range select bits are all clear.
Clock Generator Module (CGM) VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations. NOTE Software can select the CGMPCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit. 6.
Acquisition/Lock Time Specifications 6.8 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 6.8.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input.
Clock Generator Module (CGM) Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL.
Chapter 7 System Integration Module (SIM) 7.1 Introduction This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 7-1. Figure 7-2 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing.
System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM, OSC) SIM COUNTER COP CLOCK ICLK (FROM OSC) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL VDD CLOCK GENERATORS INTERNAL CLOCKS INTERNAL PULLUP DEVICE RESET PIN LOGIC LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) SIM RESET STATUS REGISTER RESET INTERRUPT SOU
SIM Bus Clock Control and Generation $FE04 $FE05 $FE06 Read: Interrupt Status Register 1 Write: (INT1) Reset: IF6 IF5 IF4 IF3 IF2 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 R R R R R R R R Interrupt Status Register 2 Write: (INT2) Reset: Read: Interrupt Status Register 3 Write: (INT3) Reset: 0 0 0 0 0 0 0 0 0 IF21 IF20 IF19 IF18 IF17 IF16 IF15 R R R R R R R R 0 0 0 0 0 0 0 0 = Unimplemente
System Integration Module (SIM) 7.2.2 Clock Start-up from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 ICLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. 7.2.
Reset and System Initialization ICLK RST IAB VECT H VECT L PC Figure 7-4. External Reset Timing 7.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 7-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR (see Figure 7-6).
System Integration Module (SIM) At power-on, these events occur: • A POR pulse is generated. • The internal reset signal is asserted. • The SIM enables CGMOUT. • Internal clocks to the CPU and modules are held inactive for 4096 ICLK cycles to allow stabilization of the oscillator. • The pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.
SIM Counter If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 7.3.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU.
System Integration Module (SIM) 7.4.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See 7.6.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 7.3.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.) 7.
Exception Control FROM RESET BREAK I BIT SET? INTERRUPT? YES NO YES I-BIT SET? NO IRQ1 INTERRUPT? YES NO STACK CPU REGISTERS SET I-BIT LOAD PC WITH INTERRUPT VECTOR AS MANY INTERRUPTS AS EXIST ON CHIP FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 7-10. Interrupt Processing 7.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction.
System Integration Module (SIM) CLI BACKGROUND ROUTINE LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 7-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry.
Exception Control 7.5.2.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 7-12. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Table 7-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 and Bit 1 — Always read 0 7.5.2.
System Integration Module (SIM) Table 7-3.
Low-Power Modes 7.5.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 7.5.4 Break Interrupts The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (See Chapter 21 Break Module (BRK).) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 7.5.
System Integration Module (SIM) IAB WAIT ADDR IDB WAIT ADDR + 1 PREVIOUS DATA SAME NEXT OPCODE SAME SAME SAME R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 7-15. Wait Mode Entry Timing Figure 7-16 and Figure 7-17 show the timing for WAIT recovery. IAB $6E0B IDB $A6 $6E0C $A6 $A6 $01 $00FF $0B $00FE $00FD $00FC $6E EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt Figure 7-16.
SIM Registers A break interrupt during stop mode sets the SIM break stop/wait bit (SBSW) in the SIM break status register (SBSR). The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 7-18 shows stop mode entry timing. NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
System Integration Module (SIM) 7.7.1 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop mode or wait mode. Address: $FE00 Bit 7 6 5 4 3 2 R R R R R R Read: Write: 1 Bit 0 SBSW Reset: R Note 0 Note: Writing a logic 0 clears SBSW. R = Reserved Figure 7-20. SIM Break Status Register (SBSR) SBSW — Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode.
SIM Registers 7.7.2 SIM Reset Status Register This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register. Address: Read: $FE01 Bit 7 6 5 4 3 2 1 Bit 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 7-21.
System Integration Module (SIM) 7.7.3 SIM Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state. Address: Read: Write: Reset: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 R = Reserved Figure 7-22.
Chapter 8 Monitor ROM (MON) 8.1 Introduction This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
Monitor ROM (MON) RST 0.1 µF HC908AP VDD VDD VDDA 0.1 µF VREFH VREG VREFL VREG VSS VSSA 4.9152MHz/9.8304MHz (50% DUTY) OSC1 CGMXFC 0.01 µF 10k MUST BE USED IF SW2 IS AT POSITION C. CONNECT TO OSC1, WITH OSC2 UNCONNECTED. EXT OSC 0.033 µF 4.9152MHz OSC1 1M 6–30 pF MAX232 1 1 µF + 3 4 1 µF C1+ C1– C2+ VDD VCC GND V+ OSC2 16 + 6–30 pF 1 µF 15 + 1 µF 2 V– 6 1 µF 5 10 8 9 IRQ1 VDD 10k 74HC125 5 6 74HC125 3 2 (SEE NOTE 1) D 10 k DB9 7 SW2 1k 8.
Functional Description 8.3.1 Entering Monitor Mode Table 8-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. If $FFFE and $FFFF do not contain $FF (programmed state): – The external clock is 4.9152 MHz with PTB0 low or 9.8304 MHz with PTB0 high – IRQ1 = VTST 2.
IRQ1 RST Address $FFFE/ $FFFF PTA2 PTA1 X GND X X X VTST(3) MC68HC908AP Family Data Sheet, Rev. 4 VDD or VTST X 0 1 (1) PTB0 External Clock(2) Bus Frequency PLL COP Baud Rate X X X 0 X Disabled 0 No operation until reset goes high 9600 PTA1 and PTA2 voltages only required if IRQ1 = VTST; PTB0 determines frequency divider PTA0 1 0 4.9152 MHz 2.4576 MHz OFF Disabled Comment Freescale Semiconductor VTST(3) VDD or VTST X 0 1 1 1 9.8304 MHz 2.
Functional Description Enter monitor mode with pin configuration shown in Figure 8-1 by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes. (See 8.4 Security.) After the security bytes, the MCU sends a break signal (10 consecutive logic 0’s) to the host, indicating that it is ready to receive a command.
Monitor ROM (MON) 8.3.2 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 NEXT START BIT STOP BIT BIT 7 Figure 8-3. Monitor Data Format 8.3.3 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal.
Functional Description 8.3.5 Commands The monitor ROM firmware uses these commands: • READ (read memory) • WRITE (write memory) • IREAD (indexed read) • IWRITE (indexed write) • READSP (read stack pointer) • RUN (run user program) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command.
Monitor ROM (MON) Table 8-4. READ (Read Memory) Command Description Read byte from memory Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR ADDRESS HIGH READ READ ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA ECHO RETURN Table 8-5.
Functional Description Table 8-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence FROM HOST IREAD IREAD DATA DATA ECHO RETURN Table 8-7.
Monitor ROM (MON) Table 8-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order Opcode $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 8-9.
Security SP HIGH BYTE OF INDEX REGISTER SP + 1 CONDITION CODE REGISTER SP + 2 ACCUMULATOR SP + 3 LOW BYTE OF INDEX REGISTER SP + 4 HIGH BYTE OF PROGRAM COUNTER SP + 5 LOW BYTE OF PROGRAM COUNTER SP + 6 SP + 7 Figure 8-7. Stack Pointer at Monitor Mode Entry 8.4 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode.
Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command.
ROM-Resident Routines During the software execution, it does not consume any dedicated RAM location, the run-time heap will extend the system stack, all other RAM location will not be affected. R FILE_PTR $XXXX A M BUS SPEED (BUS_SPD) ADDRESS AS POINTER DATA SIZE (DATASIZE) START ADDRESS HIGH (ADDRH) START ADDRESS LOW (ADDRL) DATA 0 DATA 1 DATA BLOCK DATA ARRAY DATA N Figure 8-9. Data Block Format for ROM-Resident Routines The control and data bytes are described below.
Monitor ROM (MON) The start location of the FLASH to be programmed is specified by the address ADDRH:ADDRL and the number of bytes from this location is specified by DATASIZE. The maximum number of bytes that can be programmed in one routine call is 255 bytes (max. DATASIZE is 255). ADDRH:ADDRL do not need to be at a page boundary, the routine handles any boundary misalignment during programming.
ROM-Resident Routines 8.5.2 ERARNGE ERARNGE is used to erase a range of locations in FLASH. Table 8-12. ERARNGE Routine Routine Name Routine Description ERARNGE Erase a page or the entire array Calling Address $FCE4 Stack Used 9 bytes Data Block Format Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH) Starting address (ADDRL) There are two sizes of erase ranges: a page or the entire array.
Monitor ROM (MON) 8.5.3 LDRNGE LDRNGE is used to load the data array in RAM with data from a range of FLASH locations. Table 8-13.
ROM-Resident Routines 8.5.4 MON_PRGRNGE In monitor mode, MON_PRGRNGE is used to program a range of FLASH locations with data loaded into the data array. Table 8-14. MON_PRGRNGE Routine Routine Name Routine Description Calling Address Stack Used Data Block Format MON_PRGRNGE Program a range of locations, in monitor mode $FF24 17 bytes Bus speed Data size Starting address (high byte) Starting address (low byte) Data 1 : Data N The MON_PRGRNGE routine is designed to be used in monitor mode.
Monitor ROM (MON) 8.5.6 EE_WRITE EE_WRITE is used to write a set of data from the data array to FLASH. Table 8-16. EE_WRITE Routine Routine Name Routine Description Calling Address Stack Used Data Block Format EE_WRITE Emulated EEPROM write. Data size ranges from 7 to 15 bytes at a time. $FF36 30 bytes Bus speed (BUS_SPD) Data size (DATASIZE)(1) Starting address (ADDRH)(2) Starting address (ADDRL)(1) Data 1 : Data N 1. The minimum data size is 7 bytes. The maximum data size is 15 bytes. 2.
ROM-Resident Routines F L A S H PAGE BOUNDARY CONTROL: 9 BYTES DATA ARRAY DATA ARRAY DATA ARRAY ONE PAGE = 512 BYTES PAGE BOUNDARY Figure 8-10. EE_WRITE FLASH Memory Usage The coding example below uses the $EE00–$EFFF page for data storage. The data array size is 15 bytes, and the bus speed is 4.9152 MHz. The coding assumes the data block is already loaded in RAM, with the address pointer, FILE_PTR, pointing to the first byte of the data block.
Monitor ROM (MON) 8.5.7 EE_READ EE_READ is used to load the data array in RAM with a set of data from FLASH. Table 8-17. EE_READ Routine Routine Name Routine Description Calling Address Stack Used Data Block Format EE_READ Emulated EEPROM read. Data size ranges from 7 to 15 bytes at a time. $FD5B 18 bytes Bus speed (BUS_SPD) Data size (DATASIZE) Starting address (ADDRH)(1) Starting address (ADDRL)(1) Data 1 : Data N 1. The start address must be a page boundary start address.
Chapter 9 Timer Interface Module (TIM) 9.1 Introduction This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with Input capture, output compare, and pulse-width-modulation functions. Figure 9-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2. 9.
Timer Interface Module (TIM) 9.4 Functional Description Figure 9-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence.
Functional Description Addr.
Timer Interface Module (TIM) Addr.
Functional Description An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed.
Timer Interface Module (TIM) $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 9.9.1 TIM Status and Control Register. OVERFLOW OVERFLOW OVERFLOW PERIOD PULSE WIDTH TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 9-3. PWM Period and Pulse Width The value in the TIM channel registers determines the pulse width of the PWM output.
Functional Description 9.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin.
Timer Interface Module (TIM) Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect.
I/O Signals To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure.
Timer Interface Module (TIM) TOF — TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF.
I/O Registers 9.9.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
Timer Interface Module (TIM) 9.9.
I/O Registers Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode Select Bit A When ELSxB:ELSxA ≠ 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 9-3.
Timer Interface Module (TIM) NOTE Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx — Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit.
I/O Registers Address: T1CH0H, $0026 and T2CH0H, $0031 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Reset: Indeterminate after reset Figure 9-12. TIM Channel 0 Register High (TCH0H) Address: T1CH0L, $0027 and T2CH0L $0032 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Reset: Indeterminate after reset Figure 9-13.
Timer Interface Module (TIM) MC68HC908AP Family Data Sheet, Rev.
Chapter 10 Timebase Module (TBM) 10.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the selected OSCCLK clock from the oscillator module. This TBM version uses 18 divider stages, eight of which are user selectable. 10.2 Features Features of the TBM module include: • Software programmable 8s, 4s, 2s, 1s, 2ms, 1ms, 0.5ms, and 0.25ms periodic interrupt using 32.
Timebase Module (TBM) TBON ÷2 OSCCLK ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 From OSC module ÷8 (See Chapter 5 Oscillator (OSC).) ÷ 16 ÷ 32 ÷ 64 ÷ 2048 ÷2 ÷2 ÷ 32768 ÷2 ÷ 65536 ÷2 ÷ 131072 TACK ÷2 TBR0 ÷2 TBR1 ÷2 TBR2 TBMINT ÷ 262144 TBIF 000 TBIE R 001 010 011 100 SEL 101 110 111 Figure 10-1. Timebase Block Diagram 10.4 Timebase Register Description The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the rate.
Timebase Register Description TBR[2:0] — Timebase Rate Selection These read/write bits are used to select the rate of timebase interrupts as shown in Table 10-1. NOTE Do not change TBR[2:0] bits while the timebase is enabled (TBON = 1). Table 10-1. Timebase Rate Selection for OSCCLK = 32.768-kHz Timebase Interrupt Rate TBR2 TBR1 TBR0 Divider Hz ms 0 0 0 262144 0.125 8000 0 0 1 131072 0.25 4000 0 1 0 65536 0.
Timebase Module (TBM) 10.5 Interrupts The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR[2:0]. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. The interrupt vector is defined in Table 2-1 . Vector Addresses. Interrupts must be acknowledged by writing a logic 1 to the TACK bit. 10.
Chapter 11 Serial Communications Interface Module (SCI) 11.1 Introduction The MC68HC908AP64 has two SCI modules: • SCI1 is a standard SCI module, and • SCI2 is an infrared SCI module. This section describes SCI1, the serial communications interface (SCI) module, which allows high-speed asynchronous communications with peripheral devices and other MCUs. NOTE When the SCI is enabled, the TxD pin is an open-drain output and requires a pullup resistor to be connected for proper SCI operation. 11.
Serial Communications Interface Module (SCI) 11.3 Pin Name Conventions The generic names of the SCI I/O pins are: • RxD (receive data) • TxD (transmit data) SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 11-1 shows the full names and the generic names of the SCI I/O pins. The generic pin names appear in the text of this section. Table 11-1.
Functional Description 11.4 Functional Description Figure 11-2 shows the structure of the SCI module. The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
Serial Communications Interface Module (SCI) 11.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 11-3. 8-BIT DATA FORMAT BIT M IN SCC1 CLEAR START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 PARITY BIT BIT 6 STOP BIT BIT 7 9-BIT DATA FORMAT BIT M IN SCC1 SET START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 NEXT START BIT PARITY BIT BIT 6 BIT 7 BIT 8 STOP BIT NEXT START BIT Figure 11-3. SCI Data Formats 11.4.
Functional Description 11.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). 11.4.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the TxD pin.
Serial Communications Interface Module (SCI) 11.4.2.4 Idle Characters An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress.
Functional Description the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request.
Serial Communications Interface Module (SCI) 11.4.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
Functional Description Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 11-3 summarizes the results of the data bit samples. Table 11-3.
Serial Communications Interface Module (SCI) 11.4.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. 11.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate.
Functional Description The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 – 163 × 100 = 4.12% -------------------------170 Fast Data Tolerance Figure 11-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10.
Serial Communications Interface Module (SCI) Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: • Address mark — An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF.
Low-Power Modes 11.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 11.5.1 Wait Mode The SCI module remains active after the execution of a WAIT instruction. In wait mode, the SCI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode.
Serial Communications Interface Module (SCI) NOTE The PTB2/TxD pin is an open-drain pin when configured as an output. Therefore, when configured as a general purpose output pin (PTB2), a pullup resistor must be connected to this pin. 11.7.2 RxD (Receive Data) When the SCI is enabled (ENSCI=1), the PTB3/RxD pin becomes the serial data input, RxD, to the SCI receiver regardless of the state of the DDRB3 bit in data direction register B (DDRB).
I/O Registers 11.8.1 SCI Control Register 1 SCI control register 1: • Enables loop mode operation • Enables the SCI • Controls output polarity • Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type Address: Read: Write: Reset: $0013 Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 Figure 11-9.
Serial Communications Interface Module (SCI) WAKE — Wakeup Condition Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY — Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits.
I/O Registers 11.8.
Serial Communications Interface Module (SCI) TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted.
I/O Registers 11.8.3 SCI Control Register 3 SCI control register 3: • Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted • Enables these interrupts: – Receiver overrun interrupts – Noise error interrupts – Framing error interrupts • Parity error interrupts Address: $0015 Bit 7 Read: R8 Write: Reset: U 6 5 4 3 2 1 Bit 0 T8 DMARE DMATE ORIE NEIE FEIE PEIE U 0 0 0 0 0 0 = Unimplemented U = Unaffected Figure 11-11.
Serial Communications Interface Module (SCI) NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled FEIE — Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE.
I/O Registers TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit.
Serial Communications Interface Module (SCI) FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit.
I/O Registers 11.8.5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: • Break character detected • Incoming data Address: $0017 Bit 7 6 5 4 3 2 Read: 1 Bit 0 BKF RPF 0 0 Write: Reset: 0 0 0 0 0 0 = Unimplemented Figure 11-14. SCI Status Register 2 (SCS2) BKF — Break Flag Bit This clearable, read-only bit is set when the SCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set.
Serial Communications Interface Module (SCI) 11.8.7 SCI Baud Rate Register The baud rate register (SCBR) selects the baud rate for both the receiver and the transmitter. Address: Read: $0019 6 0 0 0 0 Write: Reset: 5 4 3 2 1 Bit 0 SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 R = Reserved = Unimplemented Figure 11-16. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 11-6.
I/O Registers Table 11-8 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when fBUS is selected as SCI clock source. Table 11-8. SCI Baud Rate Selection Examples SCP1 and SCP0 Prescaler Divisor (PD) SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) Baud Rate (fBUS = 4.
Serial Communications Interface Module (SCI) MC68HC908AP Family Data Sheet, Rev.
Chapter 12 Infrared Serial Communications Interface Module (IRSCI) 12.1 Introduction The MC68HC908AP64 has two SCI modules: • SCI1 is a standard SCI module, and • SCI2 is an infrared SCI module. This section describes SCI2, the infrared serial communications interface (IRSCI) module which allows high-speed asynchronous communications with peripheral devices and other MCUs.
Infrared Serial Communications Interface Module (IRSCI) 12.2 Pin Name Conventions The generic names of the IRSCI I/O pins are: • RxD (receive data) • TxD (transmit data) IRSCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an IRSCI input or output reflects the name of the shared port pin. Table 12-1 shows the full names and the generic names of the IRSCI I/O pins. The generic pin names appear in the text of this section. Table 12-1.
IRSCI Module Overview 12.3 IRSCI Module Overview The IRSCI consists of a serial communications interface (SCI) and a infrared interface sub-module as shown in Figure 12-2. INTERNAL BUS SCI_TxD CGMXCLK BUS CLOCK SERIAL COMMUNICATIONS INTERFACE MODULE (SCI) SCTxD SCI_R32XCLK SCI_R16XCLK INFRARED SUB-MODULE SCI_RxD SCRxD Figure 12-2. IRSCI Block Diagram The SCI module provides serial data transmission and reception, with a programmable baud rate clock based on the bus clock or the CGMXCLK.
Infrared Serial Communications Interface Module (IRSCI) TNP[1:0] TRANSMIT ENCODER SCI_TxD IREN IR_TxD MUX SCTxD SCI_R32XCLK SCI_R16XCLK IR_RxD SCI_RxD RECEIVE DECODER SCRxD MUX Figure 12-3. Infrared Sub-Module Diagram 12.4.1 Infrared Transmit Encoder The infrared transmit encoder converts the "0" bits in the serial data stream from the SCI module to narrow "low" pulses, to the TxD pin. The narrow pulse is sent with a duration of 1/32, 1/16, or 3/16 of a data bit width.
SCI Functional Description 12.5 SCI Functional Description Figure 12-5 shows the structure of the SCI.
Infrared Serial Communications Interface Module (IRSCI) The SCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. NOTE For SCI operations, the IR sub-module is transparent to the SCI module.
SCI Functional Description CKS SL = 0 => X = A SL = 1 => X = B PRESCALER BAUD DIVIDER ÷ 16 SCI DATA REGISTER SCP1 SCP0 11-BIT TRANSMIT SHIFT REGISTER SCR1 H SCR2 8 7 6 5 4 3 2 START A SL X B STOP CGMXCLK BUS CLOCK INTERNAL BUS 1 0 L SCI_TxD PARITY GENERATION T8 DMATE DMATE SCTIE SCTE DMATE SCTE SCTIE TC TCIE BREAK ALL 0s PTY PREAMBLE ALL 1s PEN LOAD FROM IRSCDR M SHIFT ENABLE MSB TRANSMITTER DMA SERVICE REQUEST TRANSMITTER CPU INTERRUPT REQUEST SCR0 TRANSMITTER CONTRO
Infrared Serial Communications Interface Module (IRSCI) The SCI transmitter empty bit, SCTE, in IRSCS1 becomes set when the IRSCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the IRSCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in IRSCC2 is also set, the SCTE bit generates a transmitter interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1.
SCI Functional Description • • SCI transmitter empty (SCTE) — The SCTE bit in IRSCS1 indicates that the IRSCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in IRSCC2 enables the SCTE bit to generate transmitter CPU interrupt requests.
Infrared Serial Communications Interface Module (IRSCI) INTERNAL BUS SCR1 SCP0 SCR0 PRESCALER SL = 0 => X = A SL = 1 => X = B BAUD DIVIDER ÷ 16 DATA RECOVERY SCI_RxD BKF CPU INTERRUPT REQUEST H 11-BIT RECEIVE SHIFT REGISTER 8 7 M WAKE ILTY PEN PTY 6 5 4 3 2 1 0 L ALL 0s RPF ERROR CPU INTERRUPT REQUEST DMA SERVICE REQUEST STOP A SL X B SCI DATA REGISTER START SCR2 ALL 1s CGMXCLK BUS CLOCK SCP1 MSB CKS SCRF WAKEUP LOGIC PARITY CHECKING IDLE ILIE DMARE SCRF SCRIE DMARE SCRF SC
SCI Functional Description 12.5.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data register (IRSCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the IRSCDR.
Infrared Serial Communications Interface Module (IRSCI) Table 12-2. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 12-3 summarizes the results of the data bit samples. Table 12-3.
SCI Functional Description Table 12-4. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 12.5.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in IRSCS1. The FE flag is set at the same time that the SCRF bit is set. A break character that has no stop bit also sets the FE bit. 12.5.3.
Infrared Serial Communications Interface Module (IRSCI) The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is 154 – 147 × 100 = 4.54% -------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
SCI Functional Description 170 – 176 × 100 = 3.53% -------------------------170 12.5.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in IRSCC2 puts the receiver into a standby state during which receiver interrupts are disabled.
Infrared Serial Communications Interface Module (IRSCI) • • Framing error (FE) — The FE bit in IRSCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in IRSCC3 enables FE to generate SCI error CPU interrupt requests. Parity error (PE) — The PE bit in IRSCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in IRSCC3 enables PE to generate SCI error CPU interrupt requests. 12.
I/O Registers 12.8.1 PTC6/SCTxD (Transmit Data) The PTC6/SCTxD pin is the serial data (standard or infrared) output from the SCI transmitter. The IRSCI shares the PTC6/SCTxD pin with port C. When the IRSCI is enabled, the PTC6/SCTxD pin is an output regardless of the state of the DDRC6 bit in data direction register C (DDRC). NOTE The PTC6/SCTxD pin is an open-drain pin when configured as an output.
Infrared Serial Communications Interface Module (IRSCI) • • • • • IRSCI status register 1 (IRSCS1) IRSCI status register 2 (IRSCS2) IRSCI data register (IRSCDR) IRSCI baud rate register (IRSCBR) IRSCI infrared control register (IRSCIRCR) 12.9.
I/O Registers M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 12-6.) The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit.
Infrared Serial Communications Interface Module (IRSCI) 12.9.
I/O Registers NOTE Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1.
Infrared Serial Communications Interface Module (IRSCI) R8 — Received Bit 8 When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the IRSCDR receives the other 8 bits. When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit.
I/O Registers 12.9.4 IRSCI Status Register 1 SCI status register 1 contains flags to signal these conditions: • Transfer of IRSCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to IRSCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: $0043 Bit 7 6 5 4 3 2 1 Bit 0 Read: SCTE TC SCRF IDLE OR NF FE PE 1 1 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 12-15.
Infrared Serial Communications Interface Module (IRSCI) it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit.
I/O Registers NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an SCI error CPU interrupt request if the NEIE bit in IRSCC3 is also set. Clear the NF bit by reading IRSCS1 and then reading the IRSCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit.
Infrared Serial Communications Interface Module (IRSCI) RPF — Reception in Progress Flag Bit This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress.
I/O Registers Table 12-7. SCI Baud Rate Prescaling SCP1 and SCP0 Prescaler Divisor (PD) 00 1 01 3 10 4 11 13 SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 12-8. Reset clears SCR2–SCR0. Table 12-8.
Infrared Serial Communications Interface Module (IRSCI) Table 12-9. IRSCI Baud Rate Selection Examples SCP1 and SCP0 Prescaler Divisor (PD) SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) Baud Rate (fBUS = 4.
I/O Registers 12.9.8 IRSCI Infrared Control Register The infrared control register contains the control bits for the infrared sub-module. • Enables the infrared sub-module • Selects the infrared transmitter narrow pulse width Address: $0047 Bit 7 Read: Write: Reset: R 0 6 5 4 0 0 0 0 0 0 = Unimplemented 3 2 1 Bit 0 R TNP1 TNP0 IREN 0 0 0 0 R = Reserved Figure 12-20.
Infrared Serial Communications Interface Module (IRSCI) MC68HC908AP Family Data Sheet, Rev.
Chapter 13 Serial Peripheral Interface Module (SPI) 13.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. 13.
Serial Peripheral Interface Module (SPI) = Addr.
Functional Description INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT ÷ 2 FROM SIM SHIFT REGISTER 7 6 5 4 3 2 1 MISO 0 ÷2 MOSI ÷8 CLOCK DIVIDER ÷ 32 RECEIVE DATA REGISTER PIN CONTROL LOGIC ÷ 128 SPMSTR CLOCK SELECT SPE SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR RESERVED CPOL MODFEN TRANSMITTER CPU INTERRUPT REQUEST RESERVED CPHA SPWOM ERRIE SPI CONTROL SPTIE SPRIE RECEIVER/ERROR CPU INTERRUPT REQUEST R SPE SPRF SPTE OVRF MODF Figure 13-2.
Serial Peripheral Interface Module (SPI) 13.4.2 Slave Mode The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0. SS must remain low until the transmission is complete. (See 13.7.2 Mode Fault Error.) In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module.
Transmission Formats 13.5.2 Transmission Format When CPHA = 0 Figure 13-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave.
Serial Peripheral Interface Module (SPI) 13.5.3 Transmission Format When CPHA = 1 Figure 13-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1.
Queuing Transmission Data WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 6 1 2 BIT 5 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 3 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST LATEST WRITE TO SPDR SPSCK = INTERNAL CLOCK ÷ 2; 2 POSSIBLE START POINTS BUS CLOCK EARLIEST WRITE TO SPDR SPSCK = INTERNAL CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 32; 32 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK ÷ 128; 128 POSSIB
Serial Peripheral Interface Module (SPI) WRITE TO SPDR 1 3 SPTE 2 8 5 10 SPSCK CPHA:CPOL = 1:0 MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 6 5 4 3 2 1 6 5 4 3 2 1 6 5 4 BYTE 1 BYTE 2 BYTE 3 MOSI 4 SPRF 9 6 READ SPSCR 11 7 READ SPDR 12 1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. 7 CPU READS SPDR, CLEARING SPRF BIT. 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
Error Conditions 13.7.1 Overflow Error The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs in the middle of SPSCK cycle 7. (See Figure 13-4 and Figure 13-6.
Serial Peripheral Interface Module (SPI) BYTE 1 SPI RECEIVE COMPLETE BYTE 2 5 1 BYTE 3 7 BYTE 4 11 SPRF OVRF READ SPSCR 2 READ SPDR 4 3 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 3 6 9 8 12 10 14 13 8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. 9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 4 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 11 BYTE 4 SETS SPRF BIT.
Interrupts NOTE To prevent bus contention with another master SPI after a mode fault error, clear all SPI bits of the data direction register of the shared I/O port before enabling the SPI. When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift of the eighth data bit.
Serial Peripheral Interface Module (SPI) Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1).
Low-Power Modes • • • The shift register is cleared. The SPI state counter is cleared, making it ready for a new complete transmission. All the SPI port logic is defaulted back to being general-purpose I/O.
Serial Peripheral Interface Module (SPI) Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect. 13.12 I/O Signals The SPI module has five I/O pins and shares four of them with a parallel I/O port.
I/O Signals 13.12.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. (See 13.5 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low between transmissions for the CPHA = 1 format.
Serial Peripheral Interface Module (SPI) 13.12.5 CGND (Clock Ground) CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It is internally connected to VSS as shown in Table 13-1. 13.13 I/O Registers Three registers control and monitor SPI operation: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) 13.13.
I/O Registers SPWOM — SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE — SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 13.9 Resetting the SPI.) Reset clears the SPE bit.
Serial Peripheral Interface Module (SPI) ERRIE — Error Interrupt Enable Bit This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF — Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register.
I/O Registers Table 13-4. SPI Master Baud Rate Selection SPR1 and SPR0 Baud Rate Divisor (BD) 00 2 01 8 10 32 11 128 Use this formula to calculate the SPI baud rate: CGMOUT Baud rate = -------------------------2 × BD where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor 13.13.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register.
Serial Peripheral Interface Module (SPI) MC68HC908AP Family Data Sheet, Rev.
Chapter 14 Multi-Master IIC Interface (MMIIC) 14.1 Introduction The multi-master IIC (MMIIC) interface is a two wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices. The interface is designed for internal serial communication between the MCU and other IIC devices. It has hardware generated START and STOP signals; and byte by byte interrupt driven software algorithm.
Multi-Master IIC Interface (MMIIC) 14.3 I/O Pins The MMIIC module uses two I/O pins, shared with standard port I/O pins. The full name of the MMIIC I/O pins are listed in Table 14-1. The generic pin name appear in the text that follows. The SDA and SDL pins are open-drain. When configured as general purpose output pins (PTB0 and PTB1), pullup resistors must be connected to these pins. Table 14-1.
Multi-Master IIC Bus Protocol 14.5 Multi-Master IIC Bus Protocol Normally a standard communication is composed of four parts: 1. START signal, 2. slave address transmission, 3. data transfer, and 4. STOP signal. These are described briefly in the following sections and illustrated in Figure 14-2.
Multi-Master IIC Interface (MMIIC) Only the slave with a matched address will respond by sending back an acknowledge bit by pulling SDA low on the 9th clock cycle. (See Figure 14-2.) 14.5.3 Data Transfer Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in the direction specified by the R/W-bit sent by the calling master. Each data byte is 8 bits. Data can be changed only when SCL is low and must be held stable when SCL is high as shown in Figure 14-2.
MMIIC I/O Registers in this device clock may not change the state of the SCL line if another device clock is still in its low period. Therefore the synchronized clock SCL will be held low by the device which last releases SCL to logic high. Devices with shorter low periods enter a high wait state during this time. When all devices concerned have counted off their low period, the synchronized SCL line will be released and go high, and all devices will start counting their high periods.
Multi-Master IIC Interface (MMIIC) 14.6.1 MMIIC Address Register (MMADR) Address: $0048 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD 1 0 1 0 0 0 0 0 Reset: Figure 14-4. MMIIC Address Register (MMADR) MMAD[7:1] — Multi-Master Address These seven bits represent the MMIIC interface’s own specific slave address when in slave mode, and the calling address when in master mode.
MMIIC I/O Registers 14.6.2 MMIIC Control Register 1 (MMCR1) Address: Read: Write: Reset: $0049 Bit 7 6 MMEN MMIEN 0 0 5 4 0 0 MMCLRBB 0 0 3 2 MMTXAK REPSEN 0 1 Bit 0 0 MMCRCBYTE 0 0 0 = Unimplemented Figure 14-5. MMIIC Control Register 1 (MMCR1) MMEN — MMIIC Enable This bit is set to enable the Multi-master IIC module. When MMEN = 0, module is disabled and all flags will restore to its power-on default states. Reset clears this bit.
Multi-Master IIC Interface (MMIIC) Under normal operation, the user software should clear MMTXAK bit before setting MMCRCBYTE bit to ensure that an acknowledge signal is sent when no CRC error is detected. The MMCRCBYTE bit should not be set in transmit mode. This bit is cleared by the next START signal. Reset also clears this bit. 1 = Next receiving byte is the packet error checking (PEC) data 0 = Next receiving byte is not PEC data 14.6.
MMIIC I/O Registers MMRW — MMIIC Master Read/Write This bit is transmitted out as bit 0 of the calling address when the module sets the MMAST bit to enter master mode. The MMRW bit determines the transfer direction of the data bytes that follows. When it is "1", the module is in master receive mode. When it is "0", the module is in master transmit mode. Reset clears this bit.
Multi-Master IIC Interface (MMIIC) MMSRW — MMIIC Slave Read/Write Select This bit indicates the data direction when the module is in slave mode. It is updated after the calling address is received from a master device. MMSRW = 1 when the calling master is reading data from the module (slave transmit mode). MMSRW = 0 when the master is writing data to the module (receive mode).
MMIIC I/O Registers When the MMIIC module is enabled, MMEN = 1, data written into this register depends on whether module is in master or slave mode.
Multi-Master IIC Interface (MMIIC) 14.6.7 MMIIC CRC Data Register (MMCRCDR) Address: $004E Bit 7 6 5 4 3 2 1 Bit 0 Read: MMCRCD7 MMCRCD6 MMCRCD5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCD0 Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented Figure 14-10. MMIIC CRC Data Register (MMCRCDR) When the MMIIC module is enabled, MMEN = 1, and the CRC buffer full flag is set (MMCRCBF = 1), data in this read-only register contains the generated CRC byte for the last byte of received or transmitted data.
Program Algorithm Table 14-2. MMIIC Baud Rate Selection MMIIC Baud Rates for Bus Clocks: MMBR2 MMBR1 MMBR0 Divider 8MHz 4MHz 2MHz 1MHz 0 0 0 20 400kHz 200kHz 100kHz 50kHz 0 0 1 40 200kHz 100kHz 50kHz 25kHz 0 1 0 80 100kHz 50kHz 25kHz 12.5kHz 0 1 1 160 50kHz 25kHz 12.5kHz 6.25kHz 1 0 0 320 25kHz 12.5kHz 6.25kHz 3.125kHz 1 0 1 640 12.5kHz 6.25kHz 3.125kHz 1.5625kHz 1 1 0 1280 6.25kHz 3.125kHz 1.5625kHz 0.78125kHz 1 1 1 2560 3.125kHz 1.
Multi-Master IIC Interface (MMIIC) 14.7.
SMBus Protocols with PEC and without PEC 14.8 SMBus Protocols with PEC and without PEC Following is a description of the various MMIIC bus protocols with and without a packet error code (PEC). 14.8.1 Quick Command 1 7 1 1 1 Slave Address RW ACK START Master to Slave STOP Start Condition Slave to Master Stop Condition Command Bit Acknowledge Figure 14-13. Quick Command 14.8.
Multi-Master IIC Interface (MMIIC) 14.8.
SMBus Protocols with PEC and without PEC 14.8.6 Process Call START Slave Address W ACK START Slave Address R START Slave Address W ACK START Slave Address R ACK Command Code ACK Data Byte Low ACK Data Byte Low ACK Data Byte High NAK Command Code ACK Data Byte Low ACK Data Byte Low ACK Data Byte High ACK Data Byte High ACK STOP (a) Process Call ACK Data Byte High ACK PEC STOP NAK STOP (b) Process Call with PEC Figure 14-18. Process Call 14.8.
Multi-Master IIC Interface (MMIIC) 14.9 SMBus Protocol Implementation Shaded data packets indicate transmissions by the MCU MASTER MODE START Address 0 ACK Command ACK START Address 1 ACK RX Data1 ACK RX DataN ACK NAK STOP OPERATION: Prepare for repeated START OPERATION: Get ready to receive data OPERATION: Read received data OPERATION: Generate STOP FLAGS: MMTXIF set MMRXAK clear FLAGS: MMTXIF set MMRXAK clear FLAGS: MMRXIF set FLAGS: MMRXIF set ACTION: 1. Set MMRW 2. Set REPSEN 3.
Chapter 15 Analog-to-Digital Converter (ADC) 15.1 Introduction This section describes the analog-to-digital converter (ADC). The ADC is a 8-channel 10-bit linear successive approximation ADC. 15.
Analog-to-Digital Converter (ADC) $005C $005D $005E Read: ADC Data Register Low 2 Write: (ADRL3) Reset: Read: ADC Data Register Low 3 Write: (ADRL3) Reset: ADC Auto-scan Control Read: Register Write: (ADASCR) Reset: AD9 R 0 AD9 R 0 0 0 AD8 R 0 AD8 R 0 0 AD7 R 0 AD7 R 0 0 0 0 = Unimplemented AD6 R 0 AD6 R 0 0 AD5 R 0 AD5 R 0 0 0 0 R AD4 R 0 AD4 R 0 AD3 R 0 AD3 R 0 AD2 R 0 AD2 R 0 AUTO1 AUTO0 ASCAN 0 = Reserved 0 0 Figure 15-1. ADC I/O Register Summary 15.
Functional Description INTERNAL DATA BUS READ DDRAx DISABLE WRITE DDRAx RESET WRITE PTAx DDRAx PTAx PTAx/ADCx READ PTAx ADC0–ADC7 (8 CHANNELS) ADC DATA REGISTERS DISABLE ADRH0 ADRL0 ADRL1 ADRL2 VREFH ADRL3 INTERRUPT LOGIC AIEN VREFL ADC VOLTAGE IN (VADIN) CONVERSION COMPLETE 10-BIT ADC CHANNEL SELECT ADCICLK COCO MUX CGMXCLK BUS CLOCK ASCAN CLOCK GENERATOR ADCH[4:0] ADIV[2:0] ADICLK 2-BIT UP-COUNTER AUTO[1:0] Figure 15-2. ADC Block Diagram 15.3.
Analog-to-Digital Converter (ADC) The ADC conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is either the bus clock or CGMXCLK and is selectable by the ADICLK bit located in the ADC clock register. The divide ratio is selected by the ADIV[2:0] bits.
Interrupts 15.3.6 Result Justification The conversion result may be formatted in four different ways. • Left justified • Right justified • Left justified sign data mode • 8-bit truncation All four of these modes are controlled using MODE0 and MODE1 bits located in the ADC clock control register (ADICLK). Left justification will place the eight most significant bits (MSB) in the corresponding ADC data register high (ADRH).
Analog-to-Digital Converter (ADC) 15.5.1 Wait Mode The ADC continues normal operation in wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits to logic 1’s before executing the WAIT instruction. 15.5.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted.
I/O Registers 15.7 I/O Registers These I/O registers control and monitor ADC operation: • ADC status and control register (ADSCR) — $0057 • ADC clock control register (ADICLK) — $0058 • ADC data register high:low 0 (ADRH0:ADRL0) — $0059:$005A • ADC data register low 1–3 (ADRL1–ADRL3) — $005B–$005D • ADC auto-scan control register (ADASCR) — $005E 15.7.1 ADC Status and Control Register Function of the ADC status and control register is described here.
Analog-to-Digital Converter (ADC) Table 15-1.
I/O Registers Table 15-2. ADC Clock Divide Ratio ADIV2 ADIV1 ADIV0 ADC Clock Rate 0 0 0 ADC input clock ÷ 1 0 0 1 ADC input clock ÷ 2 0 1 0 ADC input clock ÷ 4 0 1 1 ADC input clock ÷ 8 1 X X ADC input clock ÷ 16 X = don’t care ADICLK — ADC Input Clock Select Bit ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source.
Analog-to-Digital Converter (ADC) Addr. Register Name $0059 ADC Data Register High 0 (ADRH0) $005A ADC Data Register Low 0 (ADRL0) Read: Write: Reset: Read: Write: Reset: Bit 7 0 R 0 AD9 R 0 6 0 R 0 AD8 R 0 5 0 R 0 AD7 R 0 4 0 R 0 AD6 R 0 3 0 R 0 AD5 R 0 2 0 R 0 AD4 R 0 1 0 R 0 AD3 R 0 Bit 0 0 R 0 AD2 R 0 Figure 15-5. ADRH0 and ADRL0 in 8-Bit Truncated Mode In right justified mode the ADRH0 holds the two MSBs, and the ADRL0 holds the eight least significant bits (LSBs), of the 10-bit result.
I/O Registers Addr. Register Name $0059 ADC Data Register High 0 (ADRH0) $005A ADC Data Register Low 0 (ADRL0) Bit 7 AD9 R 0 AD1 R 0 Read: Write: Reset: Read: Write: Reset: 6 AD8 R 0 AD0 R 0 5 AD7 R 0 0 R 0 4 AD6 R 0 0 R 0 3 AD5 R 0 0 R 0 2 AD4 R 0 0 R 0 1 AD3 R 0 0 R 0 Bit 0 AD2 R 0 0 R 0 Figure 15-8 ADRH0 and ADRL0 in Left Justified Sign Data Mode 15.7.
Analog-to-Digital Converter (ADC) ASCAN — Auto-scan Mode Enable Bit This bit enable/disable the auto-scan mode. Reset clears this bit. 1 = Auto-scan mode is enabled 0 = Auto-scan mode is disabled Auto-scan mode should not be enabled when ADC continuous conversion is enabled; i.e. when ADCO=1. MC68HC908AP Family Data Sheet, Rev.
Chapter 16 Input/Output (I/O) Ports 16.1 Introduction Thirty-two (32) bidirectional input-output (I/O) pins form four parallel ports. All I/O pins are programmable as inputs or outputs. NOTE Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Addr.
Input/Output (I/O) Ports Table 16-1.
Port A 16.2 Port A Port A is an 8-bit special-function port that shares all of its pins with the analog-to-digital converter (ADC) module. Port A pins also have LED direct drive capability. 16.2.1 Port A Data Register (PTA) The port A data register contains a data latch for each of the eight port A pins.
Input/Output (I/O) Ports DDRA[7:0] — Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 16-4 shows the port A I/O logic.
Port B 16.2.3 Port-A LED Control Register (LEDA) The port-A LED control register (LEDA) controls the direct LED drive capability on PTA7–PTA0 pins. Each bit is individually configurable and requires that the data direction register, DDRA, bit be configured as an output. Address: Read: Write: $000C Bit 7 6 5 4 3 2 1 Bit 0 LEDA7 LEDA6 LEDA5 LEDA4 LEDA3 LEDA2 LEDA1 LEDA0 0 0 0 0 0 0 0 0 Reset: Figure 16-5.
Input/Output (I/O) Ports SDA and SCL — Multi-Master IIC Data and Clock The SDA and SCL pins are multi-master IIC data and clock pins. Setting the MMEN bit in the MMIIC control register 1 (MMCR1) configures the PTB0/SDA and PTB1/SCL pins for MMIIC function and overrides any control from the port I/O logic. TxD and RxD — SCI Transmit and Receive Data The TxD and RxD pins are SCI transmit and receive data pins.
Port C READ DDRB ($0005) INTERNAL DATA BUS WRITE DDRB ($0005) DDRBx RESET WRITE PTB ($0001) PTBx # PTBx READ PTB ($0001) # PTB3–PTB0 are open-drain pins when configured as outputs. PTB7–PTB4 have schmitt trigger inputs. Figure 16-8. Port B I/O Circuit When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
Input/Output (I/O) Ports PTC[7:0] — Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. IRQ2 — IRQ2 input pin The PTC0/IRQ2 pin is always available as input pin to the IRQ2 module. Care must be taken to available unwanted interrupts when this pin is used as general purpose I/O.
Port D READ DDRC ($0006) INTERNAL DATA BUS WRITE DDRC ($0006) DDRCx RESET WRITE PTC ($0002) PTCx # PTCx READ PTC ($0002) # PTC0 has schmitt trigger input. Figure 16-11. Port C I/O Circuit When DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 16-4 summarizes the operation of the port C pins. Table 16-4.
Input/Output (I/O) Ports PTD[7:0] — Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. KBI7–KBI0 — Keyboard Interrupt Inputs The keyboard interrupt enable bits, KBIE[7:0], in the keyboard interrupt enable register (KBIER), enable the port D pins as external interrupt pins. See Chapter 18 Keyboard Interrupt Module (KBI). 16.5.
Port D Table 16-5 summarizes the operation of the port D pins. Table 16-5. Port D Pin Functions Accesses to DDRD DDRD Bit PTD Bit 0 X(1) 1 X Accesses to PTD I/O Pin Mode Read/Write Read Write Input, Hi-Z(2) DDRD[7:0] Pin PTD[7:0](3) Output DDRD[7:0] PTD[7:0] PTD[7:0] 1. X = don’t care. 2. Hi-Z = high impedance. 3. Writing affects data register, but does not affect input. MC68HC908AP Family Data Sheet, Rev.
Input/Output (I/O) Ports MC68HC908AP Family Data Sheet, Rev.
Chapter 17 External Interrupt (IRQ) 17.1 Introduction The external interrupt (IRQ) module provides two maskable interrupt inputs: IRQ1 and IRQ2. 17.
External Interrupt (IRQ) • • Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (INTSCR). Writing a logic 1 to the ACK bit clears the IRQ latch. Reset — A reset automatically clears the interrupt latch. The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge or falling-edge and low-level-triggered.
IRQ1 and IRQ2 Pins RESET ACK2 INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQ2F PUC0ENB D CLR Q SYNCHRONIZER CK IRQ2 IRQ2 INTERRUPT REQUEST IMASK2 MODE2 Figure 17-3. IRQ2 Block Diagram 17.4 IRQ1 and IRQ2 Pins A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive.
External Interrupt (IRQ) NOTE When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. The IRQ1 pin has a permanent internal pullup device connected, while the IRQ2 pin has an optional pullup device that can be enabled or disabled by the PUC0ENB bit in the INTSCR2 register. 17.5 IRQ Module During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during the break state.
IRQ Registers IMASK1 — IRQ1 Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1. 1 = IRQ1 interrupt requests disabled 0 = IRQ1 interrupt requests enabled MODE1 — IRQ1 Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1. 1 = IRQ1 interrupt requests on falling edges and low levels 0 = IRQ1 interrupt requests on falling edges only 17.6.
External Interrupt (IRQ) MC68HC908AP Family Data Sheet, Rev.
Chapter 18 Keyboard Interrupt Module (KBI) 18.1 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTD0–PTD7. When a port pin is enabled for keyboard interrupt function, an internal 30kΩ pullup device is also enabled on the pin. 18.
Keyboard Interrupt Module (KBI) 18.4 Functional Description INTERNAL BUS KBI0 ACKK VDD VECTOR FETCH DECODER KEYF RESET . KBIE0 D CLR Q SYNCHRONIZER . CK TO PULLUP ENABLE . KEYBOARD INTERRUPT FF KBI7 Keyboard Interrupt Request IMASKK MODEK KBIE7 TO PULLUP ENABLE Figure 18-2. Keyboard Interrupt Block Diagram Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port D pin as a keyboard interrupt pin.
Keyboard Interrupt Registers If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists.
Keyboard Interrupt Module (KBI) Address: Read: $001A Bit 7 6 5 4 3 2 0 0 0 0 KEYF 0 Write: Reset: ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 18-3. Keyboard Status and Control Register (KBSCR) KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit.
Low-Power Modes 18.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 18.6.1 Wait Mode The keyboard interrupt module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 18.6.2 Stop Mode The keyboard interrupt module remains active in stop mode.
Keyboard Interrupt Module (KBI) MC68HC908AP Family Data Sheet, Rev.
Chapter 19 Computer Operating Properly (COP) 19.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the configuration register 1 (CONFIG1). 19.2 Functional Description Figure 19-1 shows the structure of the COP module.
Computer Operating Properly (COP) NOTE Service the COP immediately after reset and before entering or after exiting STOP Mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 ICLK cycles and sets the COP bit in the SIM reset status register (SRSR). In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held at VTST. During the break state, VTST on the RST pin disables the COP.
COP Control Register 19.3.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the CONFIG1 register. Address: Read: Write: Reset: $001F Bit 7 6 5 4 3 2 1 Bit 0 COPRS LVISTOP LVIRSTD LVIPWRD LVIREGD SSREC STOP COPD 0 0 0 0 0 0 0 0 Figure 19-2. Configuration Register 1 (CONFIG1) COPRS — COP Rate Select Bit COPRS selects the COP time out period. Reset clears COPRS.
Computer Operating Properly (COP) 19.7.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 19.7.2 Stop Mode Stop mode turns off the ICLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
Chapter 20 Low-Voltage Inhibit (LVI) 20.1 Introduction This section describes the low-voltage inhibit (LVI) module. The LVI module monitors the voltage on the VDD pin and VREG pin, and can force a reset when VDD voltage falls below VTRIPF1, or VREG voltage falls below VTRIPF2. NOTE The VREG pin is the output of the internal voltage regulator and is guaranteed to meet operating specification as long as VDD is within the MCU operating voltage.
Low-Voltage Inhibit (LVI) an LVI reset occurs, the MCU remains in reset until VDD rises above VTRIPR1 and VREG rises above VTRIPR2, which causes the MCU to exit reset. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
LVI Status Register 20.3.4 Forced Reset Operation In applications that require VDD to remain above the VTRIPF1 level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF1 level. In the CONFIG1 register, the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets. 20.3.
Low-Voltage Inhibit (LVI) 20.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 20.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 20.6.2 Stop Mode If enabled in stop mode (LVISTOP = 1), the LVI module remains active in stop mode.
Chapter 21 Break Module (BRK) 21.1 Introduction This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 21.2 Features Features of the break module include: • Accessible input/output (I/O) registers during the break interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts Addr.
Break Module (BRK) The following events can cause a break interrupt to occur: • A CPU-generated address (the address in the program counter) matches the contents of the break address registers. • Software writes a logic 1 to the BRKA bit in the break status and control register. When a CPU-generated address matches the contents of the break address registers, the break interrupt begins after the CPU completes its current instruction.
Break Module Registers 21.4.1 Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if SBSW is set. (see Chapter 7 System Integration Module (SIM)) Clear the BW bit by writing logic 0 to it. 21.4.2 Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. 21.
Break Module (BRK) 21.5.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: Read: Write: Reset: $FE0C Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Figure 21-4.
Break Module Registers ; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the break ; service routine software. HIBYTE EQU 5 LOBYTE EQU 6 ; If not SBSW, do RTI BRCLR SBSW,SBSR, RETURN ; See if wait mode or stop mode was exited by ; break. TST LOBYTE,SP ;If RETURNLO is not zero, BNE DOLO ;then just decrement low byte. DEC HIBYTE,SP ;Else deal with high byte, too.
Break Module (BRK) MC68HC908AP Family Data Sheet, Rev.
Chapter 22 Electrical Specifications 22.1 Introduction This section contains electrical and timing specifications. 22.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to DC Electrical Characteristics for guaranteed operating conditions. Table 22-1. Absolute Maximum Ratings Characteristic(1) Symbol Value Unit Supply voltage VDD –0.
Electrical Specifications 22.3 Functional Operating Range Table 22-2. Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit TA – 40 to +85 °C VDD 2.7 to 5.5 V 22.4 Thermal Characteristics Table 22-3.
5V DC Electrical Characteristics 22.5 5V DC Electrical Characteristics Table 22-4. DC Electrical Characteristics (5V) Characteristic(1) Symbol Min Typ(2) Max Unit Output high voltage (ILOAD = –12mA) PTA[0:7], PTB[4:7], PTC[0:5], PTD[0:7] (ILOAD = –15mA) PTA[0:7], PTB[4:7], PTC[0:5], PTD[0:7] VOH VOH VDD –0.8 VDD –1.
Electrical Specifications Table 22-4. DC Electrical Characteristics (5V) Characteristic(1) Symbol Min Typ(2) Max Unit RPU1 RPU2 21 21 27 27 39 39 kΩ kΩ Low-voltage inhibit, trip falling voltage1(10) VTRIPF1 2.25 2.45 2.65 V Low-voltage inhibit, trip rising voltage1(10) VTRIPR1 2.35 2.55 2.75 V Low-voltage inhibit, trip voltage2(10) VTRIPF2 2.25 2.45 2.65 V VREG 2.25 2.50 2.75 V Pullup resistors(9) PTD[0:7] RST, IRQ1, IRQ2 VREG(10), (11) 1. VDD = 4.5 to 5.
5V Oscillator Characteristics 22.7 5V Oscillator Characteristics Table 22-6. Oscillator Specifications (5V) Characteristic(1) Symbol Min Typ Max Unit Internal oscillator clock frequency fICLK 64k 88k(2) 104k Hz External reference clock to OSC1(3) fOSC dc 32M Hz Crystal reference frequency fXTALCLK 30 32.768 100 kHz Crystal load capacitance(4) CL — 12.
Electrical Specifications 22.8 5V ADC Electrical Characteristics Table 22-7. ADC Electrical Characteristics (5V) Characteristic(1) Symbol Min Max Unit Notes Supply voltage VDDA 4.5 5.5 V VDDA is an dedicated pin and should be tied to VDD on the PCB with proper decoupling. Input range VADIN 0 VDDA V VADIN ≤ VDDA Resolution BAD 10 10 bits Absolute accuracy AAD — ± 1.5 LSB ADC internal clock fADIC 500k 1.
3V DC Electrical Characteristics 22.9 3V DC Electrical Characteristics Table 22-8. DC Electrical Characteristics (3V) Characteristic(1) Symbol Min Typ(2) Max Unit VOH VDD –0.4 — — V VOL VOL VOLSCI VOLIIC — — — — — — — — 0.4 0.4 0.4 0.4 V V V V LED sink current (VOL = 2V) PTA[0:7] IOL 3 7 15 mA Input high voltage PTA[0:7], PTB[0:7], PTC[0:7], PTD[0:7], RST, IRQ1 OSC1 VIH 0.7 × VDD 0.
Electrical Specifications Table 22-8. DC Electrical Characteristics (3V) Characteristic(1) Symbol Min Typ(2) Max Unit RPU1 RPU2 21 21 27 27 39 39 kΩ kΩ Low-voltage inhibit, trip falling voltage1(11) VTRIPF1 2.25 2.45 2.65 V Low-voltage inhibit, trip rising voltage1(10) VTRIPR1 2.35 2.55 2.75 V Low-voltage inhibit, trip voltage2(10) VTRIPF2 2.25 2.45 2.65 V VREG 2.25 2.50 2.75 V Pullup resistors(10) PTD[0:7] RST, IRQ1, IRQ2 VREG(10), (12) 1. VDD = 2.7 to 3.
3V Oscillator Characteristics 22.11 3V Oscillator Characteristics Table 22-10. Oscillator Specifications (3V) Characteristic(1) Symbol Min Typ Max Unit Internal oscillator clock frequency fICLK 64k 88k(2) 104k Hz External reference clock to OSC1(3) fOSC dc 32M Hz Crystal reference frequency fXTALCLK 30 32.768 100 kHz Crystal load capacitance(4) CL — 12.
Electrical Specifications 22.12 3V ADC Electrical Characteristics Table 22-11. ADC Electrical Characteristics (3V) Characteristic(1) Symbol Min Max Unit Notes Supply voltage VDDA 2.7 3.3 V VDDA is an dedicated pin and should be tied to VDD on the PCB with proper decoupling. Input range VADIN 0 VDDA V VADIN ≤ VDDA Resolution BAD 10 10 bits Absolute accuracy AAD — ± 1.5 LSB ADC internal clock fADIC 500k 1.
MMIIC Electrical Characteristics 22.13 MMIIC Electrical Characteristics Table 22-12. MMIIC DC Electrical Characteristics Characteristic(1) Symbol Min Typ Max Unit Comments Input low VIL –0.5 — 0.8 V Data, clock input low. Input high VIH 2.1 — 5.5 V Data, clock input high. Output low VOL — — 0.
Electrical Specifications Table 22-13. MMIIC Interface Input/Output Signal Timing Characteristic Symbol Min Typ Max Unit Comments Operating frequency fSMB 10 — 100 kHz Bus free time tBUF 4.7 — — µs Bus free time between STOP and START condition Repeated start hold time. tHD.STA 4.0 — — µs Hold time after (repeated) START condition. After this period, the first clock is generated. Repeated start setup time. tSU.STA 4.7 — — µs Repeated START condition setup time.
CGM Electrical Specification 22.14 CGM Electrical Specification Table 22-14. CGM Electrical Specifications Characteristic Symbol Min Typ Max Unit Reference frequency fRDV 30 32.
Electrical Specifications 22.15 5V SPI Characteristics Table 22-15.
3V SPI Characteristics 22.16 3V SPI Characteristics Table 22-16.
Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT BITS 6–1 MSB IN 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
3V SPI Characteristics SS INPUT 3 1 SPSCK INPUT CPOL = 0 5 4 2 SPSCK INPUT CPOL = 1 5 4 9 8 MISO INPUT SLAVE MSB OUT 6 MOSI OUTPUT BITS 6–1 7 NOTE 11 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined but normally MSB of character just received a) SPI Slave Timing (CPHA = 0) SS INPUT 1 SPSCK INPUT CPOL = 0 5 4 2 3 SPSCK INPUT CPOL = 1 8 MISO OUTPUT MOSI INPUT 5 4 10 NOTE 9 SLAVE MSB OUT 6 7 BITS 6–1 11 10 MSB IN SLAVE LSB OUT BITS 6–1 LSB IN Note: Not defined
Electrical Specifications 22.17 Memory Characteristics Table 22-17. Memory Characteristics Characteristic Data retention voltage Symbol Min. Max. Unit VRDR 1.
Chapter 23 Mechanical Specifications 23.1 Introduction This section gives the dimensions for: • 48-pin plastic low-profile quad flat pack (case #932) • 44-pin plastic quad flat pack (case #824A) • 42-pin shrink dual in-line package (case #858) MC68HC908AP Family Data Sheet, Rev.
Mechanical Specifications 23.2 48-Pin Low-Profile Quad Flat Pack (LQFP) 4X 0.200 AB T–U Z DETAIL Y A P A1 48 37 1 36 T U B V AE B1 12 25 13 AE V1 24 DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA Z S1 T, U, Z S DETAIL Y 4X 0.200 AC T–U Z 0.080 AC G AB AD AC MILLIMETERS MAX MIN 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 1° 5° 12° REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.
44-Pin Quad Flat Pack (QFP) 23.3 44-Pin Quad Flat Pack (QFP) B L B 33 23 22 S D S V F BASE METAL 0.20 (0.008) DETAIL A DETAIL A M C A–B S S H A–B 0.20 (0.008) B L –B– M –A– D –A–, –B–, –D– 0.05 (0.002) A–B 34 J N D 44 0.20 (0.008) 12 1 11 M C A–B S D S SECTION B–B VIEW ROTATED 90° –D– A 0.20 (0.008) M H A–B S D S S D S 0.05 (0.002) A–B S 0.20 (0.008) M C A–B M DETAIL C C E –H– –C– DATUM PLANE 0.10 (0.004) H SEATING PLANE G NOTES: 1.
Mechanical Specifications 23.4 42-Pin Shrink Dual In-Line Package (SDIP) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010). –A– 42 22 –B– 1 21 DIM A B C D F G H J K L M N L H C –T– SEATING PLANE 0.25 (0.010) N G F D 42 PL K M T A S M J 42 PL 0.25 (0.010) M T B INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.
Chapter 24 Ordering Information 24.1 Introduction This section contains device ordering numbers. 24.2 MC Order Numbers Table 24-1.
Ordering Information MC68HC908AP Family Data Sheet, Rev.
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