MC68HC908GZ60 MC68HC908GZ48 MC68HC908GZ32 Data Sheet M68HC08 Microcontrollers MC68HC908GZ60 Rev. 6.0 04/2007 freescale.
MC68HC908GZ60 MC68HC908GZ48 MC68HC908GZ32 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005, 2006, 2007.
Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level April, 2004 N/A May, 2004 1.0 Page Number(s) Description Initial release N/A 9.7.3 Keyboard Interrupt Polarity Register — Corrected the bit description of the KBIP7–KBIP0 bits. 119 14.8.
Revision History (Continued) Date October, 2006 Revision Level 5.0 Description 12.2 Features — Corrected timer link connection from TIM2 channel 0 to TIM1 channel 0. 135 12.9 Timer Link — Corrected timer link connection from TIM2 channel 0 to TIM1 channel 0. 147 21.5 5.0-Vdc Electrical Characteristics and 21.6 3.3-Vdc Electrical Characteristics — Updated DC injection current specification. April, 2007 6.0 Page Number(s) 317 319 Figure 2-2.
Revision History MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Chapters MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Table of Contents Chapter 1 General Description 1.1 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7 1.5.8 1.5.9 1.5.10 1.5.11 1.5.12 1.5.13 1.5.14 1.5.15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Features . . . . . . . . . . . . . . . . .
Table of Contents 2.6.6 FLASH-1 Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 4 Clock Generator Module (CGM) 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.6 4.7 4.7.1 4.7.2 4.7.3 4.8 4.8.1 4.8.2 4.8.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents Chapter 6 Computer Operating Properly (COP) Module 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.4 6.5 6.6 6.7 6.7.1 6.7.2 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 9 Keyboard Interrupt Module (KBI) 9.1 9.2 9.3 9.4 9.5 9.5.1 9.5.2 9.6 9.7 9.7.1 9.7.2 9.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 10.10 Enhanced Serial Communications Interface Module (ESCI) . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.11 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8.1 MSCAN08 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8.2 MSCAN08 Soft Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 13.6 13.6.1 13.6.2 13.6.3 13.7 13.7.1 13.7.2 13.8 13.8.1 13.8.2 13.9 13.9.1 13.9.2 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.8.3 ESCI Control Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.4 ESCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.5 ESCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8.6 ESCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents Chapter 16 Serial Peripheral Interface (SPI) Module 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.
Chapter 18 Timer Interface Module (TIM1) 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3.1 TIM1 Counter Prescaler . . . . . . .
Table of Contents 19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.7.1 TIM2 Clock Pin (T2CH0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.7.2 TIM2 Channel I/O Pins (T2CH5:T2CH2 and T2CH1:T2CH0) . . . . . . . . . . . . . . . . . . . . . . 19.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.9 21.9.1 21.9.2 21.9.3 21.10 21.11 21.12 21.13 21.14 21.15 Clock Generation Module (CGM) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Component Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Acquisition/Lock Time Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Chapter 1 General Description 1.1 Introduction The MC68HC908GZ60, MC68HC908GZ48, and MC68HC908GZ32 are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
General Description • • • • • • • • • • • • • • • • • • • • • Standard low-power modes of operation: – Wait mode – Stop mode Master reset pin and power-on reset (POR) On-chip FLASH memory: – MC68HC908GZ60 — 60 Kbytes – MC68HC908GZ48 — 48 Kbytes – MC68HC908GZ32 — 32 Kbytes Random-access memory (RAM): – MC68HC908GZ60 — 2048 bytes – MC68HC908GZ48 — 1536 bytes – MC68HC908GZ32 — 1536 bytes Serial peripheral interface (SPI) module Enhanced serial communications interface (ESCI) module One 16-bit, 2-channe
MCU Block Diagram • • Specific features in 48-pin LQFP are: – Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules – Port B is 8 bits: PTB0–PTB7; shared with ADC module – Port C is only 7 bits: PTC0–PTC6; shared with MSCAN module – Port D is 8 bits: PTD0–PTD7; shared with SPI, TIM1, and TIM2 modules – Port E is only 6 bits: PTE0–PTE5; shared with ESCI module Specific features in 64-pin QFP are: – Port A is 8 bits: PTA0–PTA7; shared with ADC and KBI modules – Port B is 8 bits: PTB0–PTB7; shared wi
General Description INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE5–PTE2 PTE1/RxD PTE0/T
OSC2 CGMXFC VSSA VDDA PTC1/CANRX PTC0/CANTX PTA3/KBD3/AD1 30 29 28 27 26 25 32 OSC1 31 Pin Assignments RST 1 24 PTA2/KBD2/AD10 PTD1/MISO 6 19 PTB5/AD5 PTD2/MOSI 7 18 PTB4/AD4 PTD3/SPSCK 8 17 PTB3/AD3 16 VDDAD/VREFH PTB2/AD2 20 15 5 PTB1/AD1 PTD0/SS/MCLK 14 VSSAD/VREFL PTB0/AD0 21 13 4 PTD6/T2CH0 IRQ 12 PTA0/KBD0/AD8 PTD5/T1CH1 22 11 3 PTD4/T1CH0 PTE1/RxD 10 PTA1/KBD1/AD9 VDD 23 9 2 VSS PTE0/TxD CGMXFC VSSA VDDA PTC1/CANRX PTC0/CANTX PTA7/K
CGMXFC VSSA VDDA PTC1/CANRX PTC0/CANTX PTG7/AD23 PTG6/AD22 PTG5/AD21 PTG4/AD20 PTA7/KBD7/AD15 PTA6/KBD6/AD14 PTA5/KBD5/AD13 PTA4/KBD4/AD12 63 62 61 60 59 58 57 56 55 54 53 52 51 50 64 RST PTA3/KBD3/AD11 OSC2 OSC1 General Description 49 48 PTA2/KBD2/AD10 1 PTE0/TxD 2 47 PTA1/KBD1/AD9 PTE1/RxD 3 46 PTA0/KBD0/AD8 PTE2 4 45 PTC6 PTE3 5 44 PTC5 PTE4 6 43 PTG3/AD19 PTE5 7 42 PTG2/AD18 PTF0 8 41 PTG1/AD17 PTF1 9 40 PTG0/AD16 PTF2 10 39 VSSAD/VREF
Pin Functions MCU VSS VDD C1 0.1 μF + C2 VDD Note: Component values shown represent typical applications. Figure 1-5. Power Supply Bypassing 1.5.2 Oscillator Pins (OSC1 and OSC2) OSC1 and OSC2 are the connections for an external crystal, resonator, or clock circuit. See Chapter 4 Clock Generator Module (CGM). 1.5.3 External Reset Pin (RST) A low on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system.
General Description VREFL is the low reference supply for the ADC, and by default the VSSAD/VREFL pin should be connected to the same voltage potential as VSS. See Chapter 3 Analog-to-Digital Converter (ADC). 1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15–PTA0/KBD0/AD8) PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be programmed to serve as keyboard interrupt pins or used as analog-to-digital inputs.
Pin Functions 1.5.13 Port F I/O Pins (PTF7/T2CH5–PTF0) PTF7–PTF4 are special-function, bidirectional I/O port pins that can be individually programmed to be timer interface module (TIM2) pins. PTF3–PTF0 are general-purpose, bidirectional I/O port pins that contain higher current sink/source capability. PTF7–PTF0 are only available on the 64-pin QFP package. See Chapter 18 Timer Interface Module (TIM1), Chapter 19 Timer Interface Module (TIM2), and Chapter 13 Input/Output (I/O) Ports. 1.5.
General Description MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 62,078 bytes of user FLASH memory • 2048 bytes of random-access memory (RAM) • 52 bytes of user-defined vectors 2.2 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded. 2.
Memory • • $FF81; FLASH-2 block protect register, FL2BPR $FF88; FLASH-1 control register, FL1CR Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
Input/Output (I/O) Section Addr. $0000 $0001 $0002 Register Name Port A Data Register Read: (PTA) Write: See page 173. Reset: Port B Data Register Read: (PTB) Write: See page 176. Reset: Port C Data Register Read: (PTC) Write: See page 178. Reset: $0003 Port D Data Register Read: (PTD) Write: See page 180. Reset: $0004 Data Direction Register A Read: (DDRA) Write: See page 174. Reset: $0005 $0006 Data Direction Register B Read: (DDRB) Write: See page 176.
Memory Addr. $000C $000D $000E $000F $0010 $0011 $0012 Register Name Data Direction Register E Read: (DDRE) Write: See page 184. Reset: Port C Input Pullup Enable Read: Register (PTCPUE) Write: See page 180. Reset: SPI Control Register Read: (SPCR) Write: See page 255. Reset: SPI Status and Control Read: Register (SPSCR) Write: See page 256. Reset: SPI Data Register Read: (SPDR) Write: See page 258. Reset: $0014 ESCI Control Register 2 Read: (SCC2) Write: See page 206.
Input/Output (I/O) Section Addr. $0018 $0019 Register Name ESCI Data Register Read: (SCDR) Write: See page 212. Reset: ESCI Baud Rate Register Read: (SCBR) Write: See page 212. Reset: Keyboard Status and Control Read: $001A Register (INTKBSCR) Write: See page 120. Reset: $001B Keyboard Interrupt Enable Read: Register (INTKBIER) Write: See page 121. Reset: $001C Timebase Module Control Read: Register (TBCR) Write: See page 262.
Memory Addr. $0024 $0025 $0026 Register Name TIM1 Counter Modulo Read: Register Low (T1MODL) Write: See page 273. Reset: TIM1 Channel 0 Status and Read: Control Register (T1SC0) Write: See page 274. Reset: TIM1 Channel 0 Read: Register High (T1CH0H) Write: See page 277. Reset: $0027 TIM1 Channel 0 Read: Register Low (T1CH0L) Write: See page 277. Reset: $0028 TIM1 Channel 1 Status and Read: Control Register (T1SC1) Write: See page 274.
Input/Output (I/O) Section Addr. $0030 $0031 $0032 Register Name Bit 7 TIM2 Channel 0 Status and Read: Control Register (T2SC0) Write: See page 293. Reset: TIM2 Channel 0 Read: Register High (T2CH0H) Write: See page 297. Reset: TIM2 Channel 0 Read: Register Low (T2CH0L) Write: See page 297. Reset: $0033 TIM2 Channel 1 Status and Read: Control Register (T2SC1) Write: See page 293. Reset: $0034 TIM2 Channel 1 Read: Register High (T2CH1H) Write: See page 297.
Memory Addr. $003C $003D $003E Register Name 6 5 4 3 2 1 Bit 0 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 1 1 1 1 1 ADC Data High Register Read: (ADRH) Write: See page 70. Reset: 0 0 0 0 0 0 AD9 AD8 ADC Data Low Register Read: (ADRL) Write: See page 70. Reset: AD7 AD2 AD1 AD0 COCO $003F ADC Clock Register Read: (ADCLK) Write: See page 72. Reset: $0440 Port F Data Register Read: (PTF) Write: See page 185.
Input/Output (I/O) Section Addr. $0459 $045A $045B Register Name Bit 7 TIM2 Channel 3 Status and Read: Control Register (T2SC3) Write: See page 293. Reset: TIM2 Channel 3 Read: Register High (T2CH3H) Write: See page 297. Reset: TIM2 Channel 3 Read: Register Low (T2CH3L) Write: See page 297. Reset: $045C TIM2 Channel 4 Status and Read: Control Register (T2SC4) Write: See page 293. Reset: $045D TIM2 Channel 4 Read: Register High (T2CH4H) Write: See page 297.
Memory Addr. Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R 0 0 0 0 0 0 0 0 Interrupt Status Register 1 Read: (INT1) Write: See page 231. Reset: IF6 IF5 IF4 IF3 IF2 IF1 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Interrupt Status Register 2 Read: (INT2) Write: See page 233.
Input/Output (I/O) Section Addr. Register Name $FF80 FLASH-1 Block Protect Read: Register (FL1BPR)(1) Write: See page 47. Reset: $FF81 FLASH-2 Block Protect Read: Register (FL2BPR)(1) Write: See page 54. Reset: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 BPR2 BPR1 BPR0 HVEN MASS ERASE PGM 0 0 0 0 Unaffected by reset BPR7 BPR6 BPR5 BPR4 BPR3 Unaffected by reset 1.
Memory Table 2-1.
Random-Access Memory (RAM) 2.5 Random-Access Memory (RAM) The RAM locations are broken into two non-continuous memory blocks. The RAM addresses locations are $0040–$043F and $0580–$097F. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 192 bytes of RAM.
Memory Programming tools are available from Freescale. Contact your local Freescale representative for more information. NOTE A security feature prevents viewing of the FLASH contents.(1) 2.6.2 FLASH-1 Control and Block Protect Registers The FLASH-1 array has two registers that control its operation, the FLASH-1 control register (FL1CR) and the FLASH-1 block protect register (FL1BPR). 2.6.2.1 FLASH-1 Control Register The FLASH-1 control register (FL1CR) controls FLASH program and erase operations.
FLASH-1 Memory (FLASH-1) 2.6.2.2 FLASH-1 Block Protect Register The FLASH-1 block protect register (FL1BPR) is implemented as a byte within the FLASH-1 memory; therefore, it can only be written during a FLASH programming sequence. The value in this register determines the starting location of the protected range within the FLASH-1 memory. Address: $FF80 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Unaffected by reset Figure 2-4.
Memory 2.6.3 FLASH-1 Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by using the FLASH-1 block protection register (FL1BPR). FL1BPR determines the range of the FLASH-1 memory which is to be protected.
FLASH-1 Memory (FLASH-1) B. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. However, care must be taken to ensure that these operations do not access any address within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF. C. It is highly recommended that interrupts be disabled during program/erase operations. 2.6.
Memory During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail. Use this step-by-step procedure to program a row of FLASH-1 memory. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. NOTE Only bytes which are currently $FF may be programmed. Set the PGM bit in the FLASH-1 control register (FL1CR).
FLASH-1 Memory (FLASH-1) Algorithm for programming a row (64 bytes) of FLASH memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, tNVS 5 SET HVEN BIT 6 WAIT FOR A TIME, tPGS 7 8 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG COMPLETED PROGRAMMING THIS ROW? YES NO NOTES: The time between each FLASH address change (step 7 to step 7) or the time between the last FL
Memory 2.6.7 Low-Power Modes The WAIT and STOP instructions will place the MCU in low power-consumption standby modes. 2.6.7.1 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly; however, no memory activity will take place since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH.
FLASH-2 Memory (FLASH-2) Programming tools are available from Freescale. Contact your local Freescale representative for more information. NOTE A security feature prevents viewing of the FLASH contents.(1) 2.7.2 FLASH-2 Control and Block Protect Registers The FLASH-2 array has two registers that control its operation, the FLASH-2 control register (FL2CR) and the FLASH-2 block protect register (FL2BPR). 2.7.2.
Memory 2.7.2.2 FLASH-2 Block Protect Register The FLASH-2 block protect register (FL2BPR) is implemented as a byte within the FLASH-1 memory; therefore, can only be written during a FLASH-1 programming sequence. The value in this register determines the starting location of the protected range within the FLASH-2 memory. Address: Read: Write: $FF81 Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Reset: Unaffected by reset Figure 2-8.
FLASH-2 Memory (FLASH-2) Decreasing the value in FL2BPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means that locations $7F00–$7FFF are protected in FLASH-2. The FLASH memory does not exist at some locations. The block protection range configuration is unaffected if FLASH memory does not exist in that range.
Memory 8. Wait for a time, tNVHL (minimum 100 μs). 9. Clear the HVEN bit. 10. Wait for a time, tRCV, (typically 1 μs) after which the memory can be accessed in normal read mode. NOTES A. Programming and erasing of FLASH locations can not be performed by code being executed from the same FLASH array. B. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
FLASH-2 Memory (FLASH-2) 2.7.6 FLASH-2 Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes with address ranges as follows: • $XX00 to $XX3F • $XX40 to $XX7F • $XX80 to $XXBF • $XXC0 to $XXFF During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail.
Memory E. The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing the PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG maximum. F. Be cautious when programming the FLASH-2 array to ensure that non-FLASH locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. 2.7.
FLASH-2 Memory (FLASH-2) Algorithm for programming a row (64 bytes) of FLASH memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, tNVS 5 SET HVEN BIT 6 WAIT FOR A TIME, tPGS 7 8 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED WAIT FOR A TIME, tPROG COMPLETED PROGRAMMING THIS ROW? YES NO NOTES: The time between each FLASH address change (step 7 to step 7) or the time between the last FL
Memory MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 10-bit analog-to-digital converter (ADC). 3.2 Features Features of the ADC module include: • 24 channels with multiplexed input • Linear successive approximation with monotonicity • 10-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock • Left or right justified result • Left justified sign data mode 3.
Analog-to-Digital Converter (ADC) INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE5–PTE2 P
Functional Description INTERNAL DATA BUS READ DDRx WRITE DDRx DISABLE DDRx RESET WRITE PTx PTx PTx ADC CHANNEL x READ PTx DISABLE ADC DATA REGISTER INTERRUPT LOGIC AIEN CONVERSION COMPLETE ADC ADC VOLTAGE IN (VADIN) CHANNEL SELECT ADCH4–ADCH0 ADC CLOCK COCO CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV2–ADIV0 ADICLK Figure 3-2. ADC Block Diagram 3.3.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $3FF (full scale).
Analog-to-Digital Converter (ADC) 3.3.3 Conversion Time Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency. Conversion time = 16 to 17 ADC cycles ADC frequency Number of bus cycles = conversion time × bus frequency 3.3.4 Conversion In continuous conversion mode, the ADC data register will be filled with new data after each conversion.
Monotonicity Left justified sign data mode is similar to left justified mode with one exception. The MSB of the 10-bit result, AD9 located in ADRH, is complemented. This mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. Finally, 8-bit truncation mode will place the eight MSBs in the ADC data register low, ADRL. The two LSBs are dropped. This mode of operation is used when compatibility with 8-bit ADC designs are required.
Analog-to-Digital Converter (ADC) 3.6 Low-Power Modes The WAIT and STOP instruction can put the MCU in low power- consumption standby modes. 3.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4–ADCH0 bits in the ADC status and control register before executing the WAIT instruction. 3.6.
I/O Registers 3.7.3 ADC Voltage Reference High Pin (VREFH) The ADC analog portion uses VREFH as its upper voltage reference pin. By default, connect the VREFH pin to the same voltage potential as VDD. External filtering is often necessary to ensure a clean VREFH for good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values. NOTE For maximum noise immunity, route VREFH carefully and place bypass capacitors as close as possible to the package.
Analog-to-Digital Converter (ADC) 3.8.1 ADC Status and Control Register Function of the ADC status and control register (ADSCR) is described here. Address: $003C Read: COCO Write: R Reset: Bit 7 6 5 4 3 2 1 Bit 0 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 0 0 1 1 1 1 1 R = Reserved Figure 3-4. ADC Status and Control Register (ADSCR) COCO — Conversions Complete Bit In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion.
I/O Registers The voltage levels supplied from internal reference nodes, as specified in Table 3-1, are used to verify the operation of the ADC converter both in production test and for user applications. Table 3-1.
Analog-to-Digital Converter (ADC) 3.8.2 ADC Data Register High and Data Register Low 3.8.2.1 Left Justified Mode In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
I/O Registers 3.8.2.3 Left Justified Signed Data Mode In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read.
Analog-to-Digital Converter (ADC) 3.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: Read: Write: Reset: $003F Bit 7 6 5 4 3 2 1 ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 R 0 0 0 0 0 1 0 R = Reserved = Unimplemented Bit 0 0 0 Figure 3-9. ADC Clock Register (ADCLK) ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock.
Chapter 4 Clock Generator Module (CGM) 4.1 Introduction This section describes the clock generator module. The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two.
Clock Generator Module (CGM) OSCILLATOR (OSC) OSC2 CGMXCLK (TO: SIM, TBM, ADC, MSCAN) OSC1 SIMOSCEN (FROM SIM) OSCENINSTOP (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRCLK CLOCK SELECT CIRCUIT BCS VDDA CGMXFC ÷2 A CGMOUT B S* (TO SIM) SIMDIV2 (FROM SIM) *WHEN S = 1, VSSA CGMOUT = B VPR1–VPR0 VRS7–VRS0 PHASE DETECTOR VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER CGMVCLK PLL ANALOG LOCK DETECTOR LOCK AUTOMATIC MODE CONTROL AUTO ACQ CGMINT INTERRUPT CONTROL PLLIE (TO SIM) PLLF MUL11–MUL0
Functional Description 4.3.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCENINSTOP bit in the CONFIG register enable the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency.
Clock Generator Module (CGM) frequency, fRCLK. The circuit determines the mode of the PLL and the lock condition based on this comparison. 4.3.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency.
Functional Description The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 4.8 Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL).
Clock Generator Module (CGM) In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Chapter 21 Electrical Specifications. After choosing N, the actual bus frequency can be determined using equation in 2 above. 4. Select a VCO frequency multiplier, N.
Functional Description 11. Program the PLL registers accordingly: a. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. b. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. If using a 1–8 MHz reference, the PMSL register must be reprogrammed from the reset value before enabling the PLL. c. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
Clock Generator Module (CGM) 4.3.9 CGM External Connections In its typical configuration, the CGM requires external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 4-2. Figure 4-2 shows only the logical representation of the internal components and may not represent actual circuitry.
I/O Signals 4.4 I/O Signals The following paragraphs describe the CGM I/O signals. 4.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 4.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 4.4.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 4-2.
Clock Generator Module (CGM) 4.4.8 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 4-2 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors.
CGM Registers Addr. $0039 $003A Register Name PLL Multiplier Select Low Read: Register (PMSL) Write: See page 86. Reset: PLL VCO Select Range Read: Register (PMRS) Write: See page 87. Reset: Bit 7 6 5 4 3 2 1 Bit 0 MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0 0 1 0 0 0 0 0 0 VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 0 1 0 0 0 0 0 0 0 0 0 0 R R R R 0 0 0 0 0 0 0 1 R = Reserved Read: $003B Reserved Register Write: Reset: = Unimplemented NOTES: 1.
Clock Generator Module (CGM) NOTE Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 4.3.8 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
CGM Registers 4.5.
Clock Generator Module (CGM) 4.5.3 PLL Multiplier Select Register High The PLL multiplier select register high (PMSH) contains the programming information for the high byte of the modulo feedback divider. Address: Read: $0038 Bit 7 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 MUL11 MUL10 MUL9 MUL8 0 0 0 0 = Unimplemented Figure 4-6.
CGM Registers MUL7–MUL0 — Multiplier Select Bits These read/write bits control the low byte of the modulo feedback divider that selects the VCO frequency multiplier, N. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) MUL7–MUL0 cannot be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to $40 for a default multiply value of 64.
Clock Generator Module (CGM) 4.6 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as 0.
Acquisition/Lock Time Specifications 4.8 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 4.8.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input.
Clock Generator Module (CGM) External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 4.8.3 Choosing a Filter As described in 4.8.2 Parametric Influences on Reaction Time, the external filter network is critical to the stability and reaction time of the PLL.
Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2.
Configuration Register (CONFIG) Address: $001E Bit 7 Read: 0 Write: Reset: 6 5 4 MCLKSEL MCLK1 MCLK0 0 0 0 0 3 2 1 Bit 0 MSCANEN TMBCLKSEL OSCENINSTOP SCIBDSRC See note 0 0 1 Note: MSCANEN is only reset via POR (power-on reset). = Unimplemented Figure 5-1.
Functional Description OSCENINSTOP — Oscillator Enable In Stop Mode Bit OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See Chapter 4 Clock Generator Module (CGM). This function is used to keep the timebase running while the rest of the MCU stops. See Chapter 17 Timebase Module (TBM). When clear, the oscillator will cease to generate clocks while in stop mode. The default state for this option is clear, disabling the oscillator in stop mode.
Configuration Register (CONFIG) LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module (see Chapter 11 Low-Voltage Inhibit (LVI)). The voltage mode selected for the LVI should match the operating VDD (see Chapter 21 Electrical Specifications) for the LVI’s voltage trip points for each of the modes. 1 = LVI operates in 5-V mode 0 = LVI operates in 3-V mode NOTE The LVI5OR3 bit is cleared by a power-on reset (POR) only.
Chapter 6 Computer Operating Properly (COP) Module 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register. 6.2 Functional Description Figure 6-1 shows the structure of the COP module.
Computer Operating Properly (COP) Module The COP counter is a free-running 6-bit counter preceded by the 12-bit SIM counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 262,128 CGMXCLK cycle overflow option, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms.
COP Control Register 6.3.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Chapter 5 Configuration Register (CONFIG). 6.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See Chapter 5 Configuration Register (CONFIG). 6.4 COP Control Register The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector.
Computer Operating Properly (COP) Module To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when VTST is present on the RST pin.
Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.
Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6.
Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set.
Instruction Set Summary Effect on CCR V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Description Operand Operation Opcode Source Form Address Mode Table
Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X D
Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 8.2 Features Features of the IRQ module include: • A dedicated external interrupt pin (IRQ) • IRQ interrupt control bits • Hysteresis buffer • Programmable edge-only or edge and level interrupt sensitivity • Automatic interrupt acknowledge • Internal pullup resistor 8.
External Interrupt (IRQ) RESET ACK TO CPU FOR BIL/BIH INSTRUCTIONS INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D CLR Q IRQ INTERRUPT REQUEST SYNCHRONIZER CK IRQ IMASK MODE TO MODE SELECT LOGIC HIGH VOLTAGE DETECT Figure 8-1.
IRQ Pin 8.4 IRQ Pin A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch.
External Interrupt (IRQ) 8.6 IRQ Status and Control Register The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin Address: Read: $001D Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 Write: Reset: ACK 0 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 = Unimplemented Figure 8-3.
Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup/pulldown device is also enabled on the pin. 9.
Keyboard Interrupt Module (KBI) INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE5–PTE2 PTE
Functional Description The KBIP7–KBIP0 bits determine the polarity of the keyboard pin detection. These bits along with the MODEK bit determine whether a logic level (0 or 1) and/or a falling (or rising) edge is being detected. • If the keyboard interrupt is edge-sensitive only, a falling (or rising) edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already asserted.
Keyboard Interrupt Module (KBI) If the MODEK bit is set and depending on the KBIPx bit, the keyboard interrupt pins are both falling (or rising) edge and low (or high) level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request.
Low-Power Modes An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A. 2. Write 1s (or 0s) to the appropriate port A data register bits. 3.
Keyboard Interrupt Module (KBI) 9.7.1 Keyboard Status and Control Register The keyboard status and control register: • Flags keyboard interrupt requests • Acknowledges keyboard interrupt requests • Masks keyboard interrupt requests • Controls keyboard interrupt triggering sensitivity Address: $001A Read: Bit 7 6 5 4 3 2 0 0 0 0 KEYF 0 Write: Reset: ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 9-4.
I/O Registers 9.7.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin. Address: $001B Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 Figure 9-5.
Keyboard Interrupt Module (KBI) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Chapter 10 Low-Power Modes 10.1 Introduction The microcontroller (MCU) may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in the low-power modes. 10.1.1 Wait Mode The WAIT instruction puts the MCU in a low-power standby mode in which the central processor unit (CPU) clock is disabled but the bus clock continues to run.
Low-Power Modes 10.3 Break Module (BRK) 10.3.1 Wait Mode The break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set. 10.3.2 Stop Mode The break module is inactive in stop mode. The STOP instruction does not affect break module register states. 10.4 Central Processor Unit (CPU) 10.4.
Computer Operating Properly Module (COP) 10.6 Computer Operating Properly Module (COP) 10.6.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. 10.6.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the CONFIG1 register enables the STOP instruction.
Low-Power Modes 10.9 Low-Voltage Inhibit Module (LVI) 10.9.1 Wait Mode If enabled, the low-voltage inhibit (LVI) module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 10.9.2 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. 10.10 Enhanced Serial Communications Interface Module (ESCI) 10.10.
Timer Interface Module (TIM1 and TIM2) 10.12 Timer Interface Module (TIM1 and TIM2) 10.12.1 Wait Mode The timer interface modules (TIM) remain active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 10.12.2 Stop Mode The TIM is inactive in stop mode.
Low-Power Modes 10.15 Exiting Wait Mode These events restart the CPU clock and load the program counter with the reset vector or with an interrupt vector: • External reset — A low on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. • External interrupt — A high-to-low transition on an external interrupt pin (IRQ pin) loads the program counter with the contents of locations: $FFFA and $FFFB; IRQ pin.
Exiting Stop Mode • MSCAN module interrupt — A CPU interrupt request from the MSCAN08 loads the program counter with the contents of: – $FFD4 and $FFD5; MSCAN08 transmitter – $FFD6 and $FFD7; MSCAN08 receiver – $FFD8 and $FFD9; MSCAN08 error – $FFDA and $FFDB; MSCAN08 wakeup 10.
Low-Power Modes MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF. 11.2 Features Features of the LVI module include: • Programmable LVI reset • Selectable LVI trip voltage • Programmable stop mode operation 11.3 Functional Description Figure 11-1 shows the structure of the LVI module. The LVI is enabled out of reset.
Low-Voltage Inhibit (LVI) LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See Figure 5-2. Configuration Register 1 (CONFIG1) for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 15.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI.
LVI Status Register 11.3.3 Voltage Hysteresis Protection Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS. 11.3.
Low-Voltage Inhibit (LVI) 11.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 11.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 11.6.2 Stop Mode If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active in stop mode.
Chapter 12 MSCAN08 Controller (MSCAN08) 12.1 Introduction The MSCAN08 is the specific implementation of the scalable controller area network (MSCAN) concept targeted for the M68HC08 Microcontroller Family. The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification dated September, 1991.
MSCAN08 Controller (MSCAN08) INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE5–PTE2 PTE1/
External Pins 12.3 External Pins The MSCAN08 uses two external pins, one input (CANRX) and one output (CANTX). The CANTX output pin represents the logic level on the CAN: 0 is for a dominant state, and 1 is for a recessive state. A typical CAN system with MSCAN08 is shown in Figure 12-2. CAN STATION 1 CAN NODE 1 CAN NODE 2 CAN NODE N MCU CAN CONTROLLER (MSCAN08) CANTX CANRX TRANSCEIVER CAN_H CAN_L C A N BUS Figure 12-2.
MSCAN08 Controller (MSCAN08) completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message being sent and as such reduces the reactiveness requirements on the CPU.
Message Storage CPU08 I BUS MSCAN08 RxBG RxFG RXF Tx0 TXE PRIO Tx1 TXE PRIO Tx2 TXE PRIO Figure 12-3. User Model for Message Buffer Organization 12.4.3 Transmit Structures The MSCAN08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. The three buffers are arranged as shown in Figure 12-3. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see 12.
MSCAN08 Controller (MSCAN08) To transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (TXE) flag in the MSCAN08 transmitter flag register (CTFLG) (see 12.13.7 MSCAN08 Transmitter Flag Register). The CPU08 then stores the identifier, the control bits and the data content into one of the transmit buffers. Finally, the buffer has to be flagged ready for transmission by clearing the TXE flag.
Identifier Acceptance Filter 2. Two identifier acceptance filters, each to be applied to: a. The 14 most significant bits of the extended identifier plus the SRR and the IDE bits of CAN2.0B messages, or b. The 11 bits of the identifier plus the RTR and IDE bits of CAN 2.0A/B messages. Figure 12-5 shows how the 32-bit filter bank (CIDAR0–CIDAR3 and CIDMR0–CIDMR3) produces filter 0 and 1 hits. 3. Four identifier acceptance filters, each to be applied to the first eight bits of the identifier.
MSCAN08 Controller (MSCAN08) ID28 IDR0 ID21 ID20 IDR1 ID10 IDR0 ID3 ID2 IDR1 AM7 CIDMR0 AM0 AC7 CIDAR0 AC0 ID15 ID14 IDE ID10 IDR2 ID7 ID6 IDR3 RTR IDR2 ID3 ID10 IDR3 ID3 ID ACCEPTED (FILTER 0 HIT) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID ACCEPTED (FILTER 1 HIT) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID ACCEPTED (FILTER 2 HIT) AM7 CIDMR3 AM0 AC7 CIDAR3 AC0 ID ACCEPTED (FILTER 3 HIT) Figure 12-6.
Interrupts 12.6 Interrupts The MSCAN08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked. For details, see 12.13.5 MSCAN08 Receiver Flag Register (CRFLG) through 12.13.8 MSCAN08 Transmitter Control Register. 1. Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXE flags of the empty message buffers are set. 2.
MSCAN08 Controller (MSCAN08) Table 12-1. MSCAN08 Interrupt Vector Addresses Function Source Local Mask Wakeup WUPIF WUPIE RWRNIF RWRNIE TWRNIF TWRNIE RERRIF RERRIE TERRIF TERRIE BOFFIF BOFFIE OVRIF OVRIE Error interrupts Receive Transmit RXF RXFIE TXE0 TXEIE0 TXE1 TXEIE1 TXE2 TXEIE2 Global Mask I bit 12.7 Protocol Violation Protection The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming errors.
Low-Power Modes . Table 12-2. MSCAN08 versus CPU Operating Modes MSCAN08 Mode Power Down CPU Mode STOP WAIT or RUN SLPAK = X(1) SFTRES = X Sleep SLPAK = 1 SFTRES = 0 Soft Reset SLPAK = 0 SFTRES = 1 Normal SLPAK = 0 SFTRES = 0 1. ‘X’ means don’t care. 12.8.1 MSCAN08 Sleep Mode The CPU can request the MSCAN08 to enter the low-power mode by asserting the SLPRQ bit in the module configuration register (see Figure 12-7).
MSCAN08 Controller (MSCAN08) During sleep mode, the SLPAK flag is set. The application software should use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode, the MSCAN08 stops its internal clocks. However, clocks to allow register accesses still run. If the MSCAN08 is in bus-off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks. The CANTX pin stays in recessive state.
Timer Link MSCAN08 bus activity can wake the MCU from CPU stop/MSCAN08 power-down mode. However, until the oscillator starts up and synchronization is achieved the MSCAN08 will not respond to incoming data. 12.8.4 CPU Wait Mode The MSCAN08 module remains active during CPU wait mode. The MSCAN08 will stay synchronized to the CAN bus and generates transmit, receive, and error interrupts to the CPU, if enabled. Any such interrupt will bring the MCU out of wait mode. 12.8.
MSCAN08 Controller (MSCAN08) CGMXCLK ÷2 OSC CGMOUT (TO SIM) BCS PLL ÷2 CGM MSCAN08 (2 * BUS FREQUENCY) ÷2 MSCANCLK PRESCALER (1 ... 64) CLKSRC Figure 12-8. Clocking Scheme A programmable prescaler is used to generate out of the MSCAN08 clock the time quanta (Tq) clock. A time quantum is the atomic unit of time handled by the MSCAN08. fTq = fMSCANCLK Presc value A bit time is subdivided into three segments(1) (see Figure 12-9): • SYNC_SEG: This segment has a fixed length of one time quantum.
Clock System The above parameters can be set by programming the bus timing registers, CBTR0 and CBTR1. See 12.13.3 MSCAN08 Bus Timing Register 0 and 12.13.4 MSCAN08 Bus Timing Register 1. NOTE It is the user’s responsibility to make sure that the bit timing settings are in compliance with the CAN standard, Table 12-8 gives an overview on the CAN conforming segment settings and the related parameter values. NRZ SIGNAL SYNC _SEG TIME SEGMENT 1 (PROP_SEG + PHASE_SEG1) TIME SEG. 2 (PHASE_SEG2) 1 4 ...
MSCAN08 Controller (MSCAN08) 12.11 Memory Map The MSCAN08 occupies 128 bytes in the CPU08 memory space. The absolute mapping is implementation dependent with the base address being a multiple of 128. $0500 $0508 $0509 $050D $050E $050F $0510 $0517 $0518 $053F $0540 $054F $0550 $055F $0560 $056F $0570 $057F CONTROL REGISTERS 9 BYTES RESERVED 5 BYTES ERROR COUNTERS 2 BYTES IDENTIFIER FILTER 8 BYTES RESERVED 40 BYTES RECEIVE BUFFER TRANSMIT BUFFER 0 TRANSMIT BUFFER 1 TRANSMIT BUFFER 2 Figure 12-10.
Programmer’s Model of Message Storage 12.12 Programmer’s Model of Message Storage This section details the organization of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers.
MSCAN08 Controller (MSCAN08) 12.12.1 Message Buffer Outline Figure 12-12 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 12-13. All bits of the 13-byte data structure are undefined out of reset. NOTE The foreground receive buffer can be read anytime but cannot be written. The transmit buffers can be read or written anytime. Addr.
Programmer’s Model of Message Storage Addr. Register $05b0 IDR0 $05b1 IDR1 $05b2 IDR2 $05b3 IDR3 Read: Write: Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE (=0) Read: Write: Read: Write: = Unimplemented Figure 12-13. Standard Identifier Mapping 12.12.2 Identifier Registers The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29 bits (ID28–ID0) for the extended format.
MSCAN08 Controller (MSCAN08) 12.12.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. DLC3–DLC0 — Data Length Code Bits The data length code contains the number of bytes (data byte count) of the respective message. At transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 12-5 shows the effect of setting the DLC bits. Table 12-5.
Programmer’s Model of Control Registers 12.13 Programmer’s Model of Control Registers The programmer’s model has been laid out for maximum simplicity and efficiency. Figure 12-15 gives an overview on the control register block of the MSCAN08. Addr.
MSCAN08 Controller (MSCAN08) Addr. Register Bit 7 6 5 4 3 2 1 Bit 0 $0514 CIDMR0 Read: Write: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 $0515 CIDMR1 Read: Write: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 $0516 CIDMR2 Read: Write: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 $0517 CIDMR3 Read: Write: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 R = Reserved = Unimplemented Figure 12-15. MSCAN08 Control Register Structure (Continued) 12.13.
Programmer’s Model of Control Registers SFTRES — Soft Reset When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing transmission or reception is aborted and synchronization to the bus is lost. The following registers enter and stay in their hard reset state: CMCR0, CRFLG, CRIER, CTFLG, and CTCR. The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–CIDAR3, and CIDMR0–CIDMR3 can only be written by the CPU when the MSCAN08 is in soft reset state.
MSCAN08 Controller (MSCAN08) CLKSRC — Clock Source This flag defines which clock source the MSCAN08 module is driven from (see 12.10 Clock System). 1 = The MSCAN08 clock source is CGMOUT (see Figure 12-8). 0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 12-8). NOTE The CMCR1 register can be written only if the SFTRES bit in the MSCAN08 module control register is set 12.13.
Programmer’s Model of Control Registers NOTE The CBTR0 register can be written only if the SFTRES bit in the MSCAN08 module control register is set. 12.13.4 MSCAN08 Bus Timing Register 1 Address: $0503 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0 0 0 0 0 0 0 0 Reset: Figure 12-19. Bus Timing Register 1 (CBTR1) SAMP — Sampling This bit determines the number of serial bus samples to be taken per bit time.
MSCAN08 Controller (MSCAN08) 12.13.5 MSCAN08 Receiver Flag Register (CRFLG) All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. A flag can be cleared only when the condition which caused the setting is valid no more. Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the CRIER register. A hard or soft reset will clear the register.
Programmer’s Model of Control Registers TERRIF — Transmitter Error Passive Interrupt Flag This flag is set when the MSCAN08 goes into error passive status due to the transmit error counter exceeding 127 and the bus-off interrupt flag is not set(1). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 went into transmit error passive status. 0 = No transmit error passive status has been reached.
MSCAN08 Controller (MSCAN08) 12.13.6 MSCAN08 Receiver Interrupt Enable Register Address: Read: Write: Reset: $0505 Bit 7 6 5 4 3 2 1 Bit 0 WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE 0 0 0 0 0 0 0 0 Figure 12-21. Receiver Interrupt Enable Register (CRIER) WUPIE — Wakeup Interrupt Enable 1 = A wakeup event will result in a wakeup interrupt. 0 = No interrupt will be generated from this event.
Programmer’s Model of Control Registers 12.13.7 MSCAN08 Transmitter Flag Register The abort acknowledge flags are read only. The transmitter buffer empty flags are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting. The transmitter buffer empty flags each have an associated interrupt enable bit in the CTCR register. A hard or soft reset will resets the register.
MSCAN08 Controller (MSCAN08) 12.13.8 MSCAN08 Transmitter Control Register Address: $0507 Bit 7 Read: 0 Write: Reset: 0 6 5 4 ABTRQ2 ABTRQ1 ABTRQ0 0 0 0 3 0 2 1 Bit 0 TXEIE2 TXEIE1 TXEIE0 0 0 0 0 = Unimplemented Figure 12-23. Transmitter Control Register (CTCR) ABTRQ2–ABTRQ0 — Abort Request The CPU sets an ABTRQx bit to request that an already scheduled message buffer (TXE = 0) be aborted.
Programmer’s Model of Control Registers IDAM2–IDAM0— Identifier Acceptance Mode The CPU sets these flags to define the identifier acceptance filter organization (see 12.5 Identifier Acceptance Filter). Table 12-9 summarizes the different settings. In “filter closed” mode no messages will be accepted so that the foreground buffer will never be reloaded. Table 12-9.
MSCAN08 Controller (MSCAN08) 12.13.11 MSCAN08 Transmit Error Counter Address: Read: $050F Bit 7 6 5 4 3 2 1 Bit 0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 12-26. Transmit Error Counter (CTXERR) This read-only register reflects the status of the MSCAN08 transmit error counter. NOTE Both error counters may only be read when in sleep or soft reset mode. 12.13.
Programmer’s Model of Control Registers AC7–AC0 — Acceptance Code Bits AC7–AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. NOTE The CIDAR0–CIDAR3 registers can be written only if the SFTRES bit in CMCR0 is set 12.13.
MSCAN08 Controller (MSCAN08) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Chapter 13 Input/Output (I/O) Ports 13.1 Introduction Bidirectional input-output (I/O) pins form seven parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, port D and port F are software configurable with pullup devices if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode. 13.
Input/Output (I/O) Ports Addr.
Unused Pin Termination Addr. Register Name Data Direction Register F Read: (DDRF) Write: See page 185. Reset: $0444 Data Direction Register G Read: (DDRG) Write: See page 187. Reset: $0445 Bit 7 6 5 4 3 2 1 Bit 0 DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 0 0 0 0 0 0 0 0 DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0 0 0 0 0 0 0 0 0 = Unimplemented Figure 13-1. I/O Port Register Summary (Sheet 3 of 3) Table 13-1.
Input/Output (I/O) Ports Table 13-1.
Port A 13.3 Port A Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module and the ADC module. Port A also has software configurable pullup devices if configured as an input port. 13.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins.
Input/Output (I/O) Ports 13.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer. Address: Read: Write: Reset: $0004 Bit 7 6 5 4 3 2 1 Bit 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 Figure 13-3.
Port A Table 13-2. Port A Pin Functions PTAPUE Bit DDRA Bit PTA Bit 1 0 X(1) 0 0 X 1 Accesses to DDRA I/O Pin Mode Accesses to PTA Read/Write Read Write VDD(2) DDRA7–DDRA0 Pin PTA7–PTA0(3) X Input, Hi-Z(4) DDRA7–DDRA0 Pin PTA7–PTA0(3) X Output DDRA7–DDRA0 PTA7–PTA0 PTA7–PTA0 Input, 1. X = Don’t care 2. I/O pin pulled up to VDD by internal pullup device 3. Writing affects data register, but does not affect input. 4. Hi-Z = High impedance 13.3.
Input/Output (I/O) Ports 13.4 Port B Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (ADC) module. 13.4.1 Port B Data Register The port B data register (PTB) contains a data latch for each of the eight port pins. Address: $0001 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 AD7 AD6 AD5 AD2 AD1 AD0 Reset: Unaffected by reset Alternate Function: AD4 AD3 Figure 13-6.
Port B DDRB7–DDRB0 — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB7–DDRB0, configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 13-8 shows the port B I/O logic.
Input/Output (I/O) Ports 13.5 Port C Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. PTC[1:0] are shared with the MSCAN module. 13.5.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the seven port C pins. NOTE Bit 6 through bit 2 of PTC are not available in the 32-pin LQFP package.
Port C DDRC6–DDRC0 — Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC6–DDRC0, configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 13-11 shows the port C I/O logic.
Input/Output (I/O) Ports 13.5.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRC is configured for output mode.
Port D T1CH1 and T1CH0 — Timer 1 Channel I/O Bits The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Chapter 18 Timer Interface Module (TIM1) and Chapter 19 Timer Interface Module (TIM2). SPSCK — SPI Serial Clock The PTD3/SPSCK pin is the serial clock input of the SPI module.
Input/Output (I/O) Ports When bit DDRDx is a 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 13-5 summarizes the operation of the port D pins. VDD PTDPUEx READ DDRD ($0007) INTERNAL PULLUP DEVICE WRITE DDRD ($0007) DDRDx INTERNAL DATA BUS RESET WRITE PTD ($0003) PTDx PTDx READ PTD ($0003) Figure 13-15.
Port E PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port D pin configured to have internal pullup 0 = Corresponding port D pin has internal pullup disconnected 13.7 Port E Port E is a 6-bit special-function port that shares two of its pins with the enhanced serial communications interface (ESCI) module. 13.7.
Input/Output (I/O) Ports 13.7.2 Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer. Address: Read: $000C Bit 7 6 0 0 0 0 Write: Reset: 5 4 3 2 1 Bit 0 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 0 0 0 0 0 0 = Unimplemented Figure 13-18.
Port F 13.8 Port F Port F is an 8-bit special-function port that shares four of its pins with the timer interface (TIM2) module. 13.8.1 Port F Data Register The port F data register (PTF) contains a data latch for each of the eight port F pins. Address: $0440 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 Reset: Alternate Function: Unaffected by reset T2CH5 T2CH4 T2CH3 T2CH2 = Unimplemented Figure 13-20.
Input/Output (I/O) Ports READ DDRF ($0444) WRITE DDRF ($0444) DDRFx INTERNAL DATA BUS RESET WRITE PTF ($0440) PTFx PTFx READ PTD ($0440) Figure 13-22. Port F I/O Circuit When bit DDRFx is a 1, reading address $0440 reads the PTFx data latch. When bit DDRFx is a 0, reading address $0440 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 13-7 summarizes the operation of the port F pins. Table 13-7.
Port G PTG7–PTG0 — Port G Data Bits These read/write bits are software-programmable. Data direction of each port G pin is under the control of the corresponding bit in data direction register G. Reset has no effect on port G data. AD23–AD16 — Analog-to-Digital Input Bits AD23–AD16 are pins used for the input channels to the analog-to-digital converter module.
Input/Output (I/O) Ports READ DDRG ($0445) INTERNAL DATA BUS WRITE DDRG ($0445) DDRGx RESET WRITE PTG ($0441) PTGx PTGx READ PTG ($0441) Figure 13-25. Port G I/O Circuit Table 13-8. Port G Pin Functions DDRG Bit PTG Bit I/O Pin Mode Accesses to DDRG Accesses to PTG Read/Write Read Write 0 X(1) Input, Hi-Z(2) DDRG7–DDRG0 Pin PTG7–PTG0(3) 1 X Output DDRG7–DDRG0 PTG7–PTG0 PTG7–PTG0 1. X = Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input.
Chapter 14 Enhanced Serial Communications Interface (ESCI) Module 14.1 Introduction The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU). 14.
Enhanced Serial Communications Interface (ESCI) Module INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/
Pin Name Conventions 14.3 Pin Name Conventions The generic names of the ESCI input/output (I/O) pins are: • RxD (receive data) • TxD (transmit data) ESCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an ESCI input or output reflects the name of the shared port pin. Table 14-1 shows the full names and the generic names of the ESCI I/O pins. The generic pin names appear in the text of this section. Table 14-1.
Enhanced Serial Communications Interface (ESCI) Module INTERNAL BUS SCI_TxD SCTIE BUS CLOCK R8 TCIE SL T8 SCRIE ILIE TE ACLK BIT IN SCIACTL SCTE RE TxD TRANSMIT SHIFT REGISTER TXINV LINR RxD ARBITER RxD ERROR INTERRUPT CONTROL RECEIVE SHIFT REGISTER ESCI DATA REGISTER RECEIVER INTERRUPT CONTROL TRANSMITTER INTERRUPT CONTROL ESCI DATA REGISTER SBK SCRF OR ORIE IDLE NF NEIE FE FEIE PE SCI_CLK TC RWU PEIE LOOPS LOOPS WAKEUP CONTROL BUS CLOCK CGMXCLK RECEIVE CONTROL ENSCI
Functional Description Addr. $0009 $000A $000B $0013 $0014 $0015 $0016 $0017 $0018 $0019 Register Name Read: ESCI Prescaler Register (SCPSC) Write: See page 214. Reset: Read: ESCI Arbiter Control Register (SCIACTL) Write: See page 217. Reset: Read: ESCI Arbiter Data Register (SCIADAT) Write: See page 218. Reset: Read: ESCI Control Register 1 (SCC1) Write: See page 204. Reset: Read: ESCI Control Register 2 (SCC2) Write: See page 206.
Enhanced Serial Communications Interface (ESCI) Module 14.4.2 Transmitter Figure 14-5 shows the structure of the SCI transmitter and the registers are summarized in Figure 14-4. The baud rate clock source for the ESCI can be selected via the configuration bit, SCIBDSRC.
Functional Description To initiate an ESCI transmission: 1. Enable the ESCI by writing a 1 to the enable ESCI bit (ENSCI) in ESCI control register 1 (SCC1). 2. Enable the transmitter by writing a 1 to the transmitter enable bit (TE) in ESCI control register 2 (SCC2). 3. Clear the ESCI transmitter empty bit (SCTE) by first reading ESCI status register 1 (SCS1) and then writing to the SCDR. For 9-bit data, also write the T8 bit in SCC3. 4. Repeat step 3 for each subsequent transmission.
Enhanced Serial Communications Interface (ESCI) Module 14.4.2.4 Idle Characters For TXINV = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress.
Functional Description INTERNAL BUS SCP1 SCR1 SCP0 SCR0 DATA RECOVERY PDS2 ALL ZEROS RPF PDS1 PDS0 PSSB4 PSSB3 PSSB2 11-BIT RECEIVE SHIFT REGISTER STOP ÷ 16 RxD BKF CGMXCLK OR BUS CLOCK BAUD DIVIDER H ALL ONES PRESCALER PRESCALER ÷4 ESCI DATA REGISTER 8 7 6 M WAKE ILTY PSSB1 PEN PSSB0 PTY PARITY CHECKING SCRF SCRIE OR ORIE NF NEIE ERROR CPU INTERRUPT REQUEST 5 4 3 SCRF WAKEUP LOGIC IDLE ILIE CPU INTERRUPT REQUEST START SCR2 2 1 0 L MSB LINR FE FEIE PE PEIE RWU
Enhanced Serial Communications Interface (ESCI) Module 14.4.3.2 Character Reception During an ESCI reception, the receive shift register shifts characters in from the RxD pin. The ESCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR.
Functional Description If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 14-3 summarizes the results of the data bit samples. Table 14-3.
Enhanced Serial Communications Interface (ESCI) Module 14.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs.
Functional Description Fast Data Tolerance Figure 14-9 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10. STOP IDLE OR NEXT CHARACTER RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK DATA SAMPLES Figure 14-9.
Enhanced Serial Communications Interface (ESCI) Module does not set the receiver idle bit, IDLE, or the ESCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting 1s as idle character bits after the start bit or after the stop bit. NOTE With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle will cause the receiver to wake up. 14.4.3.
ESCI During Break Module Interrupts 14.5.2 Stop Mode The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states. ESCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission or reception results in invalid data. 14.
Enhanced Serial Communications Interface (ESCI) Module • • • • ESCI baud rate register, SCBR ESCI prescaler register, SCPSC ESCI arbiter control register, SCIACTL ESCI arbiter data register, SCIADAT 14.8.
I/O Registers M — Mode (Character Length) Bit This read/write bit determines whether ESCI characters are eight or nine bits long (See Table 14-5).The ninth bit can serve as a receiver wakeup signal or as a parity bit. Reset clears the M bit. 1 = 9-bit ESCI characters 0 = 8-bit ESCI characters Table 14-5.
Enhanced Serial Communications Interface (ESCI) Module 14.8.
I/O Registers TE — Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition (high). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit.
Enhanced Serial Communications Interface (ESCI) Module Address: $0015 Bit 7 Read: R8 Write: Reset: U 6 5 4 3 2 1 Bit 0 T8 R R ORIE NEIE FEIE PEIE 0 0 0 0 0 = Unimplemented 0 0 R = Reserved U = Unaffected Figure 14-12. ESCI Control Register 3 (SCC3) R8 — Received Bit 8 When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits.
I/O Registers 14.8.4 ESCI Status Register 1 ESCI status register 1 (SCS1) contains flags to signal these conditions: • Transfer of SCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to SCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error Address: $0016 Bit 7 6 5 4 3 2 1 Bit 0 Read: SCTE TC SCRF IDLE OR NF FE PE 1 1 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 14-13.
Enhanced Serial Communications Interface (ESCI) Module IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive 1s appear on the receiver input. IDLE generates an ESCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit.
I/O Registers In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register. NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the ESCI detects noise on the RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR.
Enhanced Serial Communications Interface (ESCI) Module RPF — Reception in Progress Flag Bit This read-only bit is set when the receiver detects a 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. Polling RPF before disabling the ESCI module or entering stop mode can show whether a reception is in progress.
I/O Registers LINR — LIN Receiver Bits This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol as shown in Table 14-6. Reset clears LINR. Table 14-6.
Enhanced Serial Communications Interface (ESCI) Module 14.8.8 ESCI Prescaler Register The ESCI prescaler register (SCPSC) together with the ESCI baud rate register selects the baud rate for both the receiver and the transmitter. NOTE There are two prescalers available to adjust the baud rate. One in the ESCI baud rate register and one in the ESCI prescaler register.
I/O Registers Table 14-10. ESCI Prescaler Divisor Fine Adjust (Continued) PSSB[4:3:2:1:0] Prescaler Divisor Fine Adjust (PDFA) 0 0 1 0 1 5/32 = 0.15625 0 0 1 1 0 6/32 = 0.1875 0 0 1 1 1 7/32 = 0.21875 0 1 0 0 0 8/32 = 0.25 0 1 0 0 1 9/32 = 0.28125 0 1 0 1 0 10/32 = 0.3125 0 1 0 1 1 11/32 = 0.34375 0 1 1 0 0 12/32 = 0.375 0 1 1 0 1 13/32 = 0.40625 0 1 1 1 0 14/32 = 0.4375 0 1 1 1 1 15/32 = 0.46875 1 0 0 0 0 16/32 = 0.5 1 0 0 0 1 17/32 = 0.53125 1 0 0 1 0 18/32 = 0.
Enhanced Serial Communications Interface (ESCI) Module Table 14-11. ESCI Baud Rate Selection Examples PDS[2:1:0] PSSB[4:3:2:1:0] SCP[1:0] Prescaler Divisor (BPD) SCR[2:1:0] Baud Rate Divisor (BD) 0 0 0 X X X X X 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 9600 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 9562.65 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 9525.58 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 8563.
ESCI Arbiter 14.9 ESCI Arbiter The ESCI module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time detection. The arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. The CPU can control operation mode via the ESCI arbiter control register (SCIACTL). 14.9.
Enhanced Serial Communications Interface (ESCI) Module ARUN— Arbiter Counter Running Flag This read-only bit indicates the arbiter counter is running. Reset clears ARUN. 1 = Arbiter counter running 0 = Arbiter counter stopped AROVFL— Arbiter Counter Overflow Bit This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to SCIACTL. Writing 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears AROVFL.
ESCI Arbiter another bus is driving the bus dominant) ALOST is set. As long as ALOST is set, the TxD pin is forced to 1, resulting in a seized transmission. If SCI_TxD senses 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration operation will be restarted after the next rising edge of SCI_TxD. MEASURED TIME CPU READS RESULT OUT OF SCIADAT COUNTER STOPS, AFIN = 1 COUNTER STARTS, ARUN = 1 CPU WRITES SCIACTL WITH $20 RXD Figure 14-21.
Enhanced Serial Communications Interface (ESCI) Module MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Chapter 15 System Integration Module (SIM) 15.1 Introduction This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 15-1. Table 15-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing.
System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO CGM) SIM COUNTER CGMXCLK (FROM CGM) CGMOUT (FROM CGM) ÷2 CLOCK CONTROL VDD CLOCK GENERATORS INTERNAL PULLUP DEVICE RESET PIN LOGIC INTERNAL CLOCKS FORCED MONITOR MODE ENTRY LVI (FROM LVI MODULE) POR CONTROL MASTER RESET CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) RESET
Introduction 7 Addr. Register Name $FE00 Read: Break Status Register (BSR) Write: See page 237. Reset: Bit 7 6 5 4 3 2 1 R R R R R R 0 0 0 0 0 0 0 0 SBSW Note(1) Bit 0 R 1. Writing a 0 clears SBSW. $FE01 $FE03 $FE04 $FE05 $FE06 $FE07 Read: SIM Reset Status Register (SRSR) Write: See page 237. POR: Read: Break Flag Control Register (BFCR) Write: See page 238.
System Integration Module (SIM) 15.2 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 15-3. This clock originates from either an external oscillator or from the on-chip PLL.
Reset and System Initialization 15.3 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • Illegal address • Forced monitor mode entry reset (MODRST) All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST).
System Integration Module (SIM) RST PULLED LOW BY MCU RST 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH Figure 15-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR MODRST INTERNAL RESET Figure 15-6. Sources of Internal Reset Table 15-2. Reset Recovery Reset Recovery Type Actual Number of Cycles POR/LVI 4163 (4096 + 64 + 3) All others 67 (64 + 3) 15.3.2.
Reset and System Initialization OSC1 PORRST 4096 CYCLES 32 CYCLES 32 CYCLES CGMXCLK CGMOUT RST $FFFE IAB $FFFF Figure 15-7. POR Recovery 15.3.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the CONFIG1 register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset.
System Integration Module (SIM) 15.4 SIM Counter The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus clocks. The SIM counter also serves as a prescaler for the computer operating properly (COP) module. The SIM counter overflow supplies the clock for the COP module. The SIM counter is 12 bits long. 15.4.
Exception Control MODULE INTERRUPT I BIT IAB DUMMY IDB SP DUMMY SP – 1 SP – 2 PC – 1[7:0] PC – 1[15:8] SP – 3 X SP – 4 A VECT H CCR VECT L V DATA H START ADDR V DATA L OPCODE R/W Figure 15-8. Interrupt Entry Timing MODULE INTERRUPT I BIT IAB SP – 4 IDB SP – 3 CCR SP – 2 A SP – 1 X SP PC PC + 1 PC – 1 [7:0] PC – 1 [15:8] OPCODE OPERAND R/W Figure 15-9. Interrupt Recovery Timing 15.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction.
System Integration Module (SIM) FROM RESET BREAK INTERRUPT ? NO YES YES BITSET? SET? IIBIT NO IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO YES OTHER INTERRUPTS ? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION ? YES NO RTI INSTRUCTION ? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 15-10. Interrupt Processing MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Exception Control CLI BACKGROUND ROUTINE LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 15-11. Interrupt Recognition Example 15.5.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does.
System Integration Module (SIM) Table 15-3.
Exception Control Interrupt Status Register 2 Address: $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 15-13. Interrupt Status Register 2 (INT2) IF14–IF7 — Interrupt Flags 14–7 These flags indicate the presence of interrupt requests from the sources shown in Table 15-3.
System Integration Module (SIM) 15.5.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 15.5.3 Break Interrupts The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output (see Chapter 18 Timer Interface Module (TIM1) and Chapter 19 Timer Interface Module (TIM2)). The SIM puts the CPU into the break state by forcing it to the SWI vector location.
Low-Power Modes A module that is active during wait mode can wakeup the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode also can be exited by a reset or break.
System Integration Module (SIM) The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 15-19 shows stop mode entry timing. Figure 15-20 shows stop mode recovery time from interrupt. NOTE To minimize stop current, all pins configured as inputs should be driven to a 1 or 0.
SIM Registers 15.7.1 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: Read: Write: Reset: $FE00 Bit 7 6 5 4 3 2 R R R R R R 0 0 0 0 0 0 R = Reserved 1 SBSW Note(1) 0 Bit 0 R 0 1. Writing a 0 clears SBSW. Figure 15-21. Break Status Register (BSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine.
System Integration Module (SIM) ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST — Monitor Mode Entry Module Reset Bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = VDD 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset
Chapter 16 Serial Peripheral Interface (SPI) Module 16.1 Introduction This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices. The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. 16.
Serial Peripheral Interface (SPI) Module INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE
Functional Description INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER BUSCLK 7 6 5 4 3 2 1 MISO 0 ÷2 MOSI ÷8 CLOCK DIVIDER RECEIVE DATA REGISTER ÷ 32 PIN CONTROL LOGIC ÷ 128 SPMSTR SPE CLOCK SELECT SPR1 SPSCK M CLOCK LOGIC S SS SPR0 SPMSTR TRANSMITTER CPU INTERRUPT REQUEST RECEIVER/ERROR CPU INTERRUPT REQUEST CPHA MODFEN CPOL SPWOM ERRIE SPI CONTROL SPTIE SPRIE SPE SPRF SPTE OVRF MODF Figure 16-2. SPI Module Block Diagram Addr.
Serial Peripheral Interface (SPI) Module 16.3.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE In a multi-SPI system, configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See 16.12.1 SPI Control Register. Only a master SPI module can initiate transmissions.
Transmission Formats The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master.
Serial Peripheral Interface (SPI) Module input (SS) is low, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 16.6.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe.
Transmission Formats pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 16.6.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line.
Serial Peripheral Interface (SPI) Module WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 5 BIT 6 SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 1 3 2 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN WRITE TO SPDR BUS CLOCK EARLIEST BUS CLOCK WRITE TO SPDR EARLIEST BUS CLOCK WRITE TO SPDR EARLIEST BUS CLOCK WRITE TO SPDR EARLIEST LATEST SPSCK = BUS CLOCK ÷ 2; 2 POSSIBLE START POINTS SPSCK = BUS CLOCK ÷ 8; 8 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 32; 32 POSSIBLE ST
Queuing Transmission Data 16.5 Queuing Transmission Data The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when SPTE is high.
Serial Peripheral Interface (SPI) Module 16.6 Error Conditions The following flags signal SPI error conditions: • Overflow (OVRF) — Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register.
Error Conditions In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 16-11 illustrates this process.
Serial Peripheral Interface (SPI) Module In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes low. A mode fault in a master SPI causes the following events to occur: • If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. • The SPE bit is cleared. • The SPTE bit is set. • The SPI state counter is cleared. • The data direction register of the shared I/O port regains control of port drivers.
Interrupts 16.7 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests. See Table 16-1. Table 16-1.
Serial Peripheral Interface (SPI) Module The following sources in the SPI status and control register can generate CPU interrupt requests: • SPI receiver full bit (SPRF) — SPRF becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request.
SPI During Break Interrupts 16.9.2 Stop Mode The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. 16.10 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state.
Serial Peripheral Interface (SPI) Module When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. 16.11.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
I/O Registers Table 16-2. SPI Configuration SPE SPMSTR MODFEN SPI Configuration Function of SS Pin 0 X(1)) X Not enabled General-purpose I/O; SS ignored by SPI 1 0 X Slave Input-only to SPI 1 1 0 Master without MODF General-purpose I/O; SS ignored by SPI 1 1 1 Master with MODF Input-only to SPI 1. X = Don’t care 16.
Serial Peripheral Interface (SPI) Module CPOL — Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 16-5 and Figure 16-7.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit. CPHA — Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 16-5 and Figure 16-7.
I/O Registers SPRF — SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit.
Serial Peripheral Interface (SPI) Module If the MODFEN bit is 1, then the SS pin is not available as a general-purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN. See 16.11.4 SS (Slave Select). If the MODFEN bit is 0, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set.
Chapter 17 Timebase Module (TBM) 17.1 Introduction This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external clock source. This TBM version uses 15 divider stages, eight of which are user selectable. A configuration option bit to select an additional 128 divide of the external clock source can be selected. See Chapter 5 Configuration Register (CONFIG) 17.
Timebase Module (TBM) TMBCLKSEL FROM CONFIG2 CGMXCLK FROM CGM MODULE TBMCLK 0 1 DIVIDE BY 128 PRESCALER TBON ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 TACK ÷2 TBR0 ÷2 TBR1 ÷2 TBR2 TBMINT TBIF 000 TBIE R 001 010 100 SEL 011 101 110 111 Figure 17-1. Timebase Block Diagram 17.
Low-Power Modes Table 17-1. Timebase Divider Selection Divider TBR2 TBR1 TBR0 0 0 0 TMBCLKSEL 0 1 0 32,768 4,194,304 0 1 8192 1,048,576 0 1 0 2048 262144 0 1 1 128 16,384 1 0 0 64 8192 1 0 1 32 4096 1 1 0 16 2048 1 1 1 8 1024 As an example, a 4.9152 MHz crystal, with the TMBCLKSEL set for divide-by-128 and the TBR2–TBR0 set to {011}, the divider is 16,384 and the interrupt rate calculates to: 16,384 4.9152 x 106 = 3.
Timebase Module (TBM) 17.7 Timebase Control Register The timebase has one register, the timebase control register (TBCR), which is used to enable the timebase interrupts and set the rate. Address: $001C Bit 7 Read: TBIF Write: Reset: 0 6 5 4 TBR2 TBR1 TBR0 0 0 0 = Unimplemented 3 2 1 Bit 0 TBIE TBON R 0 0 0 0 R = Reserved 0 TACK Figure 17-2. Timebase Control Register (TBCR) TBIF — Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over.
Chapter 18 Timer Interface Module (TIM1) 18.1 Introduction This section describes the timer interface module (TIM1). TIM1 is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 18-2 is a block diagram of the TIM1. 18.
Timer Interface Module (TIM1) INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE5–PTE2 PTE1/
Functional Description PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 16-BIT COUNTER PS0 TOF TOIE 16-BIT COMPARATOR INTERRUPT LOGIC T1MODH:T1MODL TOV0 CHANNEL 0 ELS0B ELS0A CH0MAX 16-BIT COMPARATOR T1CH0H:T1CH0L PORT LOGIC PTD4/T1CH0 CH0F 16-BIT LATCH CH0IE MS0A INTERRUPT LOGIC MS0B INTERNAL BUS TOV1 CHANNEL 1 ELS1B ELS1A CH1MAX 16-BIT COMPARATOR T1CH1H:T1CH1L PORT LOGIC PTD5/T1CH1 CH1F 16-BIT LATCH MS1A CH1IE INTERRUPT LOGIC Figure 18-2.
Timer Interface Module (TIM1) Addr. Register Name $0020 TIM1 Status and Control Register (T1SC) See page 271. $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A TIM1 Counter Register High (T1CNTH) See page 273. TIM1 Counter Register Low (T1CNTL) See page 273. TIM1 Counter Modulo Register High (T1MODH) See page 273. TIM1 Counter Modulo Register Low (T1MODL) See page 273. TIM1 Channel 0 Status and Control Register (T1SC0) See page 274. TIM1 Channel 0 Register High (T1CH0H) See page 277.
Functional Description Use the following methods to synchronize unbuffered changes in the output compare value on channel x: • When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value.
Timer Interface Module (TIM1) OVERFLOW OVERFLOW OVERFLOW PERIOD POLARITY = 1 (ELSxA = 0) TCHx PULSE WIDTH POLARITY = 0 (ELSxA = 1) TCHx OUTPUT COMPARE OUTPUT COMPARE OUTPUT COMPARE Figure 18-4. PWM Period and Pulse Width 18.3.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 18.3.4 Pulse Width Modulation (PWM).
Functional Description 18.3.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the T1CH0 pin. The TIM1 channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM1 channel 0 status and control register (T1SC0) links channel 0 and channel 1. The TIM1 channel 0 registers initially control the pulse width on the T1CH0 pin.
Timer Interface Module (TIM1) register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM1 overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 18.8.
Input/Output Signals 18.7 Input/Output Signals Port D shares two of its pins with the TIM1. The two TIM1 channel I/O pins are PTD4/T1CH0 and PTD5/T1CH1. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTD4/T1CH0 can be configured as a buffered output compare or buffered PWM pin. 18.
Timer Interface Module (TIM1) TSTOP — TIM1 Stop Bit This read/write bit stops the TIM1 counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM1 counter until software clears the TSTOP bit. 1 = TIM1 counter stopped 0 = TIM1 counter active NOTE Do not set the TSTOP bit before entering wait mode if the TIM1 is required to exit wait mode.
Input/Output Registers 18.8.2 TIM1 Counter Registers The two read-only TIM1 counter registers contain the high and low bytes of the value in the TIM1 counter. Reading the high byte (T1CNTH) latches the contents of the low byte (T1CNTL) into a buffer. Subsequent reads of T1CNTH do not affect the latched T1CNTL value until T1CNTL is read. Reset clears the TIM1 counter registers. Setting the TIM1 reset bit (TRST) also clears the TIM1 counter registers.
Timer Interface Module (TIM1) 18.8.
Input/Output Registers MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1 channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts T1CH1 to general-purpose I/O. Reset clears the MSxB bit.
Timer Interface Module (TIM1) When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 18-2 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. NOTE After initially enabling a TIM1 channel register for input capture operation and selecting the edge sensitivity, clear CHxF to ignore any erroneous edge detection flags.
Input/Output Registers In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM1 channel x registers (T1CHxH) inhibits output compares until the low byte (T1CHxL) is written.
Timer Interface Module (TIM1) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Chapter 19 Timer Interface Module (TIM2) 19.1 Introduction This section describes the timer interface module (TIM2). The TIM2 is a 6-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 19-2 is a block diagram of the TIM2. 19.
Timer Interface Module (TIM2) INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE5–PTE2 PTE1/
Functional Description TCLK PTD6/T2CH0 INTERNAL BUS CLOCK PRESCALER SELECT PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR T2MODH:T2MODL CHANNEL 0 ELS0B ELS0A TOV0 CH0MAX 16-BIT COMPARATOR T2CH0H:T2CH0L CH0F 16-BIT LATCH MS0A CHANNEL 1 ELS1B ELS1A TOV1 CH1MAX 16-BIT COMPARATOR T2CH1H:T2CH1L CH0IE MS0B CH1F 16-BIT LATCH CH1IE MS1A CHANNEL 2 ELS2B ELS2A TOV2 CH2MAX 16-BIT COMPARATOR T2CH2H:T2CH2L CH2F 16-BIT LATCH MS2A CHANNEL 3 ELS
Timer Interface Module (TIM2) Addr. Register Name Bit 7 TOF $002B TIM2 Status and Control Read: Register (T2SC) Write: See page 291. Reset: $002C $002D 1 Bit 0 PS2 PS1 PS0 1 0 0 0 0 0 TIM2 Counter Register High Read: (T2CNTH) Write: See page 292. Reset: Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 TIM2 Counter Register Low Read: (T2CNTL) Write: See page 292.
Functional Description Addr. $0457 $0458 $0459 Register Name TIM2 Channel 2 Register High Read: (T2CH2H) Write: See page 297. Reset: TIM2 Channel 2 Register Low Read: (T2CH2L) Write: See page 297. Reset: TIM2 Channel 3 Status and Read: Control Register (T2SC3) Write: See page 293. Reset: $045A TIM2 Channel 3 Register High Read: (T2CH3H) Write: See page 297. Reset: $045B TIM2 Channel 3 Register Low Read: (T2CH3L) Write: See page 297.
Timer Interface Module (TIM2) 19.3.1 TIM2 Counter Prescaler The TIM2 clock source can be one of the seven prescaler outputs or the TIM2 clock pin, T2CH0. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM2 status and control register select the TIM2 clock source. 19.3.2 Input Capture An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit counter.
Functional Description 19.3.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 19.3.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM2 channel registers. An unsynchronized write to the TIM2 channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods.
Timer Interface Module (TIM2) Writing to the TIM2 channel 5 registers enables the TIM2 channel 5 registers to synchronously control the output after the TIM2 overflows. At each subsequent overflow, the TIM2 channel registers (4 or 5) that control the output are the ones written to last. T2SC4 controls and monitors the buffered output compare function, and TIM2 channel 5 status and control register (T2SC5) is unused.
Functional Description 19.3.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 19.3.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the TIM2 channel registers. An unsynchronized write to the TIM2 channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods.
Timer Interface Module (TIM2) function, and TIM2 channel 3 status and control register (T2SC3) is unused. While the MS2B bit is set, the channel 3 pin, T2CH3, is available as a general-purpose I/O pin. Channels 4 and 5 can be linked to form a buffered PWM channel whose output appears on the T2CH4 pin. The TIM2 channel registers of the linked pair alternately control the pulse width of the output. Setting the MS4B bit in TIM2 channel 4 status and control register (T2SC4) links channel 4 and channel 5.
Interrupts Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM2 channel 0 registers (T2CH0H:T2CH0L) initially control the buffered PWM output. TIM2 status control register 0 (T2SC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Setting MS2B links channels 2 and 3 and configures them for buffered PWM operation. The TIM2 channel 2 registers (T2CH2H:T2CH2L) initially control the buffered PWM output.
Timer Interface Module (TIM2) 19.6 TIM2 During Break Interrupts A break interrupt stops the TIM2 counter and inhibits input captures. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 15.7.3 Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit.
I/O Registers 19.8.1 TIM2 Status and Control Register The TIM2 status and control register: • Enables TIM2 overflow interrupts • Flags TIM2 overflows • Stops the TIM2 counter • Resets the TIM2 counter • Prescales the TIM2 counter clock Address: $002B Bit 7 Read: TOF Write: 0 Reset: 0 6 5 TOIE TSTOP 0 1 4 3 0 0 TRST 0 0 2 1 Bit 0 PS2 PS1 PS0 0 0 0 = Unimplemented Figure 19-5.
Timer Interface Module (TIM2) NOTE Setting the TSTOP and TRST bits simultaneously stops the TIM2 counter at a value of $0000. PS[2:0] — Prescaler Select Bits These read/write bits select either the T2CH0 pin or one of the seven prescaler outputs as the input to the TIM2 counter as Table 19-1 shows. Reset clears the PS[2:0] bits. Table 19-1.
I/O Registers 19.8.3 TIM2 Counter Modulo Registers The read/write TIM2 modulo registers contain the modulo value for the TIM2 counter. When the TIM2 counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM2 counter resumes counting from $0000 at the next timer clock. Writing to the high byte (T2MODH) inhibits the TOF bit and overflow interrupts until the low byte (T2MODL) is written. Reset sets the TIM2 counter modulo registers.
Timer Interface Module (TIM2) Address: $0033 Bit 7 T2SC1 6 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX 0 0 0 0 0 0 5 4 3 2 1 Bit 0 MS3A ELS3B ELS3A TOV3 CH3MAX 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX 0 0 0 0 0 0 5 4 3 2 1 Bit 0 MS5A ELS5B ELS5A TOV5 CH5MAX 0 0 0 0 0 Read: CH1F Write: 0 Reset: 0 0 Address: $0456 T
I/O Registers MSxB — Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM2 channel 0, TIM2 channel 2, and TIM2 channel 4 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts T2CH1 pin to general-purpose I/O. Setting MS2B disables the channel 3 status and control register and reverts T2CH3 pin to general-purpose I/O.
Timer Interface Module (TIM2) ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port D or port F, and pin PTDx/T2CHx or pin PTFx/T2CHx is available as a general- purpose I/O pin.
I/O Registers 19.8.5 TIM2 Channel Registers These read/write registers contain the captured TIM2 counter value of the input capture function or the output compare value of the output compare function. The state of the TIM2 channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM2 channel x registers (T2CHxH) inhibits input captures until the low byte (T2CHxL) is read.
Timer Interface Module (TIM2) Address: $045A Read: Write: T2CH3H Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate after reset Address: $045B Read: Write: T2CH3L Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset: Indeterminate after reset Address: $045D Read: Write: T2CH4H Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reset: Indeterminate aft
Chapter 20 Development Support 20.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 20.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
Development Support INTERNAL BUS MONITOR ROM 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE5–PTE2 PTE1/RxD PTE0/T
Break Module (BRK) ADDRESS BUS[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] BKPT (TO SIM) CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW ADDRESS BUS[7:0] Figure 20-2. Break Module Block Diagram Addr. Register Name $FE00 Read: Break Status Register (BSR) Write: See page 304. Reset: $FE03 $FE09 $FE0A $FE0B Read: Break Flag Control Register (BFCR) Write: See page 304. Reset: Read: Break Address High Register (BRKH) Write: See page 303.
Development Support When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not execute
Break Module (BRK) 20.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0B Read: Write: Reset: Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 20-4. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit.
Development Support 20.2.2.3 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode. Address: $FE00 Bit 7 Read: Write: R 6 R 5 R 4 R 3 R 2 R 1 Bit 0 SBSW R Note(1) Reset: 0 R = Reserved 1. Writing a 0 clears SBSW. Figure 20-7. Break Status Register (BSR) SBSW — SIM Break Stop/Wait SBSW can be read within the break state SWI routine.
Monitor Module (MON) 20.3 Monitor Module (MON) The monitor module allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
Development Support POR RESET NO CONDITIONS FROM Table 20-1 PTA0 = 1, PTA1 = 0, RESET VECTOR BLANK? IRQ = VTST? YES PTA0 = 1, PTA1 = 0, PTB0 = 1, AND PTB1 = 0? NO NO YES YES FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE INVALID USER MODE HOST SENDS 8 SECURITY BYTES IS RESET POR? YES NO YES ARE ALL SECURITY BYTES CORRECT? ENABLE FLASH NO DISABLE FLASH MONITOR MODE ENTRY DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) EXECUTE MONITOR CODE YES DOES RESET OCCUR? NO
Monitor Module (MON) MC68HC908GZ60 N.C. VDD RST 27 pF 1 1 μF + 3 4 1 μF + VDD VCC 16 C1+ C1– GND 15 C2+ V+ 2 + DB9 3 7 10 8 9 0.1 μF VDD OSC1 8 MHz + 10 k 1 μF PTB4 1 kΩ VDD + 2 1 μF VDDAD 10 MΩ 27 pF V– 6 5 C2– VDDA OSC2 MAX232 1 μF PTB0 IRQ 10 k 10 k 9.1 V PTB1 10 k PTA1 10 kΩ 74HC125 5 6 74HC125 3 2 VDD VSSAD PTA0 VSSA VSS 4 1 5 Figure 20-10. Normal Monitor Mode Circuit MC68HC908GZ60 N.C.
Development Support Table 20-1. Monitor Mode Signal Requirements and Options Mode IRQ Reset Vector RST Serial Communication Mode Selection Communication Speed Divider PLL PTA0 PTA1 PTB0 PTB1 PTB4 COP External Bus Clock Frequency Baud Rate VTST VDD or VTST X 1 0 1 0 0 OFF Disabled 4.0 MHz 2.0 MHz 7200 VTST VDD or VTST X 1 0 1 0 1 OFF Disabled 8.0 MHz 2.0 MHz 7200 Forced Monitor VDD or VSS VDD $FF (blank) 1 0 X X X OFF Disabled 8.0 MHz 2.
Monitor Module (MON) 20.3.1.1 Normal Monitor Mode If VTST is applied to IRQ and PTB4 is low upon monitor mode entry, the bus frequency is a divide-by-two of the input clock. If PTB4 is high with VTST applied to IRQ upon monitor mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTB4 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied to IRQ.
Development Support 20.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 20-12. Monitor Data Format 20.3.1.5 Break Signal A start bit (0) followed by nine 0 bits is a break signal.
Monitor Module (MON) FROM HOST 4 ADDRESS HIGH READ READ 4 1 ADDRESS HIGH ADDRESS LOW 1 ADDRESS LOW 4 DATA 1 3, 2 4 ECHO RETURN Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 20-14.
Development Support Table 20-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE ADDRESS HIGH WRITE ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 20-5.
Monitor Module (MON) Table 20-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 20-8.
Development Support 20.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
Chapter 21 Electrical Specifications 21.1 Introduction This section contains electrical and timing specifications. 21.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 21.5 5.0-Vdc Electrical Characteristics for guaranteed operating conditions. Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to + 6.
Electrical Specifications 21.3 Functional Operating Range Characteristic Symbol Value Unit TA –40 to +125 °C VDD 5.0 ±10% 3.3 ±10% V Symbol Value Unit Thermal resistance 32-pin LQFP 48-pin LQFP 64-pin QFP θJA 95 95 54 °C/W I/O pin power dissipation PI/O User determined W Power dissipation(1) PD PD = (IDD × VDD) + PI/O = K/(TJ + 273 °C) W Constant(2) K Average junction temperature TJ Operating temperature range Operating voltage range 21.
5.0-Vdc Electrical Characteristics 21.5 5.0-Vdc Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.8 VDD – 1.5 VDD – 1.5 — — — — — — — — 50 V V V mA IOH2 — — 50 mA IOHT — — 100 mA VOL VOL VOL IOL1 — — — — — — — — 0.4 1.5 1.5 50 V V V mA IOL2 — — 50 mA IOLT — — 100 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.
Electrical Specifications Characteristic(1) Symbol Min Typ(2) Max Unit Pullup/pulldown resistors (as input only) Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0/CANTX, PTD7/T2CH1–PTD0/SS RPU 20 45 65 kΩ Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 3.90 4.25 4.50 V Low-voltage inhibit, trip rising voltage VTRIPR 4.0 4.35 4.
3.3-Vdc Electrical Characteristics 21.6 3.3-Vdc Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.3 VDD – 1.0 VDD – 1.0 — — — — — — — — 30 V V V mA IOH2 — — 30 mA IOHT — — 60 mA VOL VOL VOL IOL1 — — — — — — — — 0.3 1.0 0.8 30 V V V mA IOL2 — — 30 mA IOLT — — 60 mA Input high voltage All ports, IRQ, RST, OSC1 VIH 0.7 × VDD — VDD V Input low voltage All ports, IRQ, RST, OSC1 VIL VSS — 0.
Electrical Specifications Characteristic(1) Symbol Min Typ(2) Max Unit Pullup/pulldown resistors (as input only) Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0, PTD7/T2CH1–PTD0/SS RPU 20 45 65 kΩ Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD + 2.5 — VDD + 4.0 V Low-voltage inhibit, trip falling voltage VTRIPF 2.35 2.6 2.8 V Low-voltage inhibit, trip rising voltage VTRIPR 2.4 2.66 2.
5.0-Volt Control Timing 21.7 5.0-Volt Control Timing Characteristic(1) Symbol Min Max Unit fOSC 1 dc 8 32 MHz Internal operating frequency fOP (fBus) — 8 MHz Internal clock period (1/fOP) tCYC 125 — ns RESET input pulse width low tRL 100 — ns IRQ interrupt pulse width low (edge-triggered) tILIH 100 — ns tILIL Note 3 — tCYC Frequency of operation Crystal option External clock option(2) (3) IRQ interrupt pulse period 1.
Electrical Specifications 21.9 Clock Generation Module (CGM) Characteristics 21.9.1 CGM Operating Conditions Characteristic Symbol Min Typ Max Unit Operating voltage VDDA VSSA VDD – 0.3 VSS – 0.3 — — VDD + 0.3 VSS + 0.3 V Crystal reference frequency fRCLK 1 — 8 MHz Input clock frequency (PLL off)(1) fXCLK — — 32 MHz Range nominal multiplier fNOM — 71.42 — kHz VCO center-of-range frequency(2) fVRS 71.42k — 40M Hz VCO operating frequency(3) fVCLK 71.42k — 32M Hz 1.
Clock Generation Module (CGM) Characteristics 21.9.3 CGM Acquisition/Lock Time Information Characteristic Symbol Min Typ Max Unit Acquisition mode entry frequency tolerance(1) ΔACQ ± 3.6 — ± 7.2 % Tracking mode entry frequency tolerance(2) ΔTRK 0 — ± 3.6 % LOCK entry frequency tolerance(3) ΔLOCK 0 — ± 0.9 % LOCK exit frequency tolerance(4) ΔUNL ± 0.9 — ± 1.
Electrical Specifications 21.10 5.0-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 4.5 5.5 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –4 +4 LSB Includes quantization ADC internal clock fADIC 500 k 1.
3.3-Volt ADC Characteristics 21.11 3.3-Volt ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 3.0 3.6 V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VDDAD Resolution BAD 10 10 Bits Absolute accuracy AAD –6 +6 LSB Includes quantization ADC internal clock fADIC 500 k 1.
Electrical Specifications 21.12 5.
3.3-Volt SPI Characteristics 21.13 3.
Electrical Specifications SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 11 MOSI OUTPUT MASTER MSB OUT 7 LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
3.
Electrical Specifications 21.14 Timer Interface Module Characteristics Characteristic Symbol Min Max Unit tTH, tTL 2 — tcyc tTLTL Note(1) — tcyc tTCL, tTCH tcyc + 5 — ns Timer input capture pulse width Timer input capture period Timer input clock pulse width 1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
Memory Characteristics 21.15 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz fRead(1) 0 — 8M Hz FLASH page erase time <1 k cycles >1 k cycles tErase 0.9 3.6 1 4 1.1 5.
Electrical Specifications MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev.
Chapter 22 Ordering Information and Mechanical Specifications 22.1 Introduction This section contains ordering numbers for the MC68HC908GZ60 and gives the dimensions for: • 32-pin low-profile quad flat pack (case 873A) • 48-pin low-profile quad flat pack (case 932-03) • 64-pin quad flat pack (case 840B) The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Freescale Sales Office. 22.
Appendix A MC68HC908GZ48 A.1 Introduction The MC68HC908GZ48 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. The information contained in this document pertains to the MC68HC908GZ48 with the exceptions shown in this appendix. A.2 Block Diagram See Figure A-1. A.
INTERNAL BUS MONITOR ROM — 304 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MEMORY MAP MODULE PTF7/T2CH5 PTF6/T2CH4 PTF5/T2CH3 PTF4/T2CH2 PTF3–PFT0(3) CONFIGURATION REGISTER
$0000 ↓ $003F I/O REGISTERS 64 BYTES $0040 ↓ $043F RAM-1 1024 BYTES $0440 ↓ $0461 I/O REGISTERS 34 BYTES $0462 ↓ $04FF RESERVED $0500 ↓ $057F MSCAN CONTROL AND MESSAGE BUFFER 128 BYTES $0580 ↓ $077F RAM-2 512 BYTES $0780 ↓ $1DFF RESERVED $1E00 ↓ $1E0F MONITOR ROM 16 BYTES $1E10 ↓ $3FFF RESERVED $4000 ↓ $7FFF FLASH-2 16,384 BYTES $8000 ↓ $FDFF FLASH-1 32,256 BYTES $FE00 SIM BREAK STATUS REGISTER (BSR) $FE01 SIM RESET STATUS REGISTER (SRSR) $FE02 RESERVED $FE03 SIM BREAK FLAG CONT
A.4 Ordering Information Table A-1.
Appendix B MC68HC908GZ32 B.1 Introduction The MC68HC908GZ32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. The information contained in this document pertains to the MC68HC908GZ32 with the exceptions shown in this appendix. B.2 Block Diagram See Figure B-1. B.
MONITOR ROM — 304 BYTES 2-CHANNEL TIMER INTERFACE MODULE USER FLASH VECTOR SPACE — 52 BYTES 6-CHANNEL TIMER INTERFACE MODULE COMPUTER OPERATING PROPERLY MODULE RST(1) SYSTEM INTEGRATION MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ(1) SINGLE EXTERNAL INTERRUPT MODULE MONITOR MODE ENTRY MODULE POWER-ON RESET MODULE VDD VSS VDDA VSSA POWER PTD7/T2CH1(2) PTD6/T2CH0(2) PTD5/T1CH1(2) PTD4/T1CH0(2) PTD3/SPSCK(2) PTD2/MOSI(2) PTD1/MISO(2) PTD0/SS/MCLK(2) PTE5–PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE ME
$0000 ↓ $003F I/O REGISTERS 64 BYTES $0040 ↓ $043F RAM-1 1024 BYTES $0440 ↓ $0461 I/O REGISTERS 34 BYTES $0462 ↓ $04FF RESERVED $0500 ↓ $057F MSCAN CONTROL AND MESSAGE BUFFER 128 BYTES $0580 ↓ $077F RAM-2 512 BYTES $0780 ↓ $1DFF RESERVED $1E00 ↓ $1E0F MONITOR ROM 16 BYTES $1E10 ↓ $7FFF RESERVED $8000 ↓ $FDFF FLASH-1 32,256 BYTES $FE00 SIM BREAK STATUS REGISTER (BSR) $FE01 SIM RESET STATUS REGISTER (SRSR) $FE02 RESERVED $FE03 SIM BREAK FLAG CONTROL REGISTER (BFCR) $FE04 INTERRUPT
B.4 Ordering Information Table B-1.
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