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MC68HC908QY4A Data Sheet, Addendum 5/2012

Freescale Semiconductor 1

Addendum to MC68HC908QY4A, rev. 3

This addendum introduces a change to this data sheet.

Chapter 15 Development Support, Section 15.3.2 Security

A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host

can bypass the security feature at monitor mode entry by sending eight security bytes that match the

bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.

NOTE

Do not leave locations $FFF6–$FFFD blank. For security reasons, program

locations $FFF6–$FFFD even if they are not used for vectors.

Changes to:

Chapter 15 Development Support, Section 15.3.2 Security

A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host

can bypass the security feature at monitor mode entry by sending eight security bytes that match the

bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data.

NOTE

Do not leave locations $FFF6–$FFFD blank. For security reasons, program

locations $FFF6–$FFFD even if they are not used for vectors. An improved

security function denies monitor mode entry if five or more of the eight

security bytes are $00 (zero bytes).

Summary of content (202 pages)

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Addendum to MC68HC908QY4A, rev. 3 This addendum introduces a change to this data sheet. Chapter 15 Development Support, Section 15.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank.
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MC68HC908QY4A MC68HC908QT4A MC68HC908QY2A MC68HC908QT2A MC68HC908QY1A MC68HC908QT1A Data Sheet M68HC08 Microcontrollers MC68HC908QY4A Rev. 3 03/2010 freescale.
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MC68HC908QY4A MC68HC908QY2A MC68HC908QY1A MC68HC908QT4A MC68HC908QT2A MC68HC908QT1A Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST.
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Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level December, 2005 N/A August, 2006 April, 2007 March, 2010 1 2 3 Page Number(s) Description Initial release N/A Added 1.7 Unused Pin Termination. 20 Figure 4-1. Auto Wakeup Interrupt Request Generation Logic — Corrected clock source. 51 4.
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List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3 Analog-to-Digital Converter (ADC10) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 4 Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Chapters MC68HC908QYA/QTA Family Data Sheet, Rev.
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Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . .
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Table of Contents 3.3.4 Sources of Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.1 Sampling Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.2 Pin Leakage Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4.3 Noise-Induced Errors . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 6 Computer Operating Properly (COP) 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.4 6.5 6.6 6.6.1 6.6.2 6.7 6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 8.4 8.5 8.5.1 8.5.2 8.6 8.7 8.7.1 8.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . .
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Chapter 11 Oscillator (OSC) Module 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3.
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Table of Contents Chapter 13 System Integration Module (SIM) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Bus Timing . . . . . . . . . . . . . . .
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14.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents Chapter 16 Electrical Specifications 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.12 16.13 16.14 16.15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1 General Description 1.1 Introduction The MC68HC908QY4A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. 0.4 Table 1-1.
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General Description • • • • • • • • • • • • • On-chip random-access memory (RAM) 2-channel, 16-bit timer interface (TIM) module 6-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel (ADC10) Up to 13 bidirectional input/output (I/O) lines and one input only: – Six shared with KBI – Six shared with ADC – Two shared with TIM – One input only shared with IRQ – High current sink/source capability on all port pins – Selectable pullups on all ports, selectable on an indiv
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MCU Block Diagram 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908QY4A.
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General Description 1.4 Pin Assignments The MC68HC908QT4A, MC68H908QT2A, and MC68HC098QT1A are available in 8-pin packages. The MC68HC908QY4A, MC68HC908QY2A, and MC68HC908QY1A are available in 16-pin packages. Figure 1-2 shows the pin assignment for these packages.
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Pin Functions 1.5 Pin Functions Table 1-2 provides a description of the pin functions. Table 1-2.
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General Description 1.6 Pin Function Priority Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. NOTE Upon reset all pins come up as input ports regardless of the priority table. Table 1-3.
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Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1. 2.2 Unimplemented Memory Locations Executing code from an unimplemented location will cause an illegal address reset. In Figure 2-1, unimplemented locations are shaded. 2.3 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation.
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Memory $0000 ↓ $003F IDIRECT PAGE REGISTERS 64 BYTES $0040 ↓ $007F UNIMPLEMENTED 64 BYTES $0080 ↓ $00FF RAM 128 BYTES $0100 ↓ $27FF UNIMPLEMENTED 9984 BYTES $2800 ↓ $2A1F AUXILIARY ROM 544 BYTES $2A20 ↓ $2F7D UNIMPLEMENTED 1374 BYTES $2F7E ↓ $2FFF AUXILIARY ROM 130 BYTES $3000 ↓ $EDFF UNIMPLEMENTED 48640 BYTES $EE00 ↓ $FDFF FLASH MEMORY 4096 BYTES RESERVED 2560 BYTES $EE00 ↓ $F7FF $FE00 ↓ $FE1F MISCELLANEOUS REGISTERS 32 BYTES FLASH MEMORY 1536 BYTES $F800 ↓ $FDFF $FE20 ↓ $FF7D MON
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Direct Page Registers Addr. Register Name Bit 7 Read: $0000 $0001 $0002 ↓ $0003 $0004 $0005 $0006 ↓ $000A $000B $000C $000D ↓ $0019 $001A $001B $001C Port A Data Register (PTA) Write: See page 104. Reset: Port B Data Register Read: (PTB) Write: See page 106.
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Memory Addr. Register Name Read: $001D $001E IRQ Status and Control Register (INTSCR) Write: See page 81. Reset: Configuration Register 2 Read: (CONFIG2)(1) Write: See page 57. Reset: Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 ACK 1 Bit 0 IMASK MODE 0 0 0 0 0 0 0 0 IRQPUD IRQEN R R R R OSCENINSTOP RSTEN 0 0 0 0 0 0 0 0(2) 1. One-time writable register after each reset. 2. RSTEN reset to 0 by a power-on reset (POR) only.
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Direct Page Registers Addr. Register Name Bit 7 Read: $0028 $0029 $002A $002B ↓ $0035 $0036 $0037 $0038 $0039 ↓ $003B $003C TIM Channel 1 Status and Control Register (TSC1) Write: See page 135. Reset: TIM Channel 1 Read: Register High (TCH1H) Write: See page 137. Reset: TIM Channel 1 Read: Register Low (TCH1L) Write: See page 137.
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Memory Addr. Register Name Bit 7 Read: $FE00 $FE01 $FE02 $FE03 Break Status Register (BSR) Write: See page 143. Reset: $FE05 $FE06 $FE07 $FE08 $FE0A $FE0B R R 3 R 2 1 SBSW R 0 Bit 0 R 0 PIN COP ILOP ILAD MODRST LVI 0 POR: 1 0 0 0 0 0 0 0 Break Auxiliary Read: Register (BRKAR) Write: See page 143. Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BCFE R R R R R R R Interrupt Status Register 1 (INT1) Write: See page 119.
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Direct Page Registers Addr. Register Name Read: $FE0C $FE0D ↓ $FE0F $FFBE $FFBF $FFC0 $FFC1 $FFFF LVI Status Register (LVISR) Write: See page 91. Reset: Bit 7 6 5 4 3 2 1 Bit 0 LVIOUT 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 TRIM2 TRIM1 TRIM0 TRIM2 TRIM1 TRIM0 Reserved FLASH Block Protect Read: Register (FLBPR) Write: See page 34.
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Memory Table 2-1.
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FLASH Memory (FLASH) 2.6 FLASH Memory (FLASH) The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after final assembly of the application product. It is possible to program the entire array through the single-wire monitor mode interface.
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Memory ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time.
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FLASH Memory (FLASH) 2.6.3 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory to read as a 1: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS. 5. Set the HVEN bit. 6. Wait for a time, tMErase. 7. Clear the ERASE and MASS bits.
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Memory 6. 7. 8. 9. 10. 11. 12. 13. Wait for a time, tPGS. Write data to the FLASH address being programmed(1). Wait for time, tPROG. Repeat step 7 and 8 until all desired bytes within the row are programmed. Clear the PGM bit (1). Wait for time, tNVH. Clear the HVEN bit. After time, tRCV, the memory can be accessed in read mode again. NOTE The COP register at location $FFFF should not be written between steps 5-12, when the HVEN bit is set.
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FLASH Memory (FLASH) Algorithm for Programming a Row (32 Bytes) of FLASH Memory 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED 4 WAIT FOR A TIME, tNVS 5 SET HVEN BIT 6 WAIT FOR A TIME, tPGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, tPROG 9 COMPLETED PROGRAMMING THIS ROW? Y N 10 11 12 NOTES: The time between each FLASH address change (step 7 to step 7 loop), or the time between
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Memory 2.6.6 FLASH Block Protect Register The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting address of the protected range within the FLASH memory. Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Reset: Unaffected by reset. Initial value from factory is 1.
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FLASH Memory (FLASH) 2.6.7 EEPROM Memory Emulation Using FLASH Memory In some applications, the user may want to repeatedly store and read a set of data from an area of nonvolatile memory. This is easily implemented in EEPROM memory because single byte erase is allowed in EEPROM. When using FLASH memory, the minimum erase size is a page. However, the FLASH can be used as EEPROM memory. This technique is called “EEPROM emulation”.
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Memory MC68HC908QYA/QTA Family Data Sheet, Rev.
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Chapter 3 Analog-to-Digital Converter (ADC10) Module 3.1 Introduction This section describes the 10-bit successive approximation analog-to-digital converter (ADC10). The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for port location of these shared pins. The ADC10 on this MCU uses VDD and VSS as its supply and reference pins. This MCU uses BUSCLKX4 as its alternate clock source for the ADC. This MCU does not have a hardware conversion trigger. 3.
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Analog-to-Digital Converter (ADC10) Module PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT VDD
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Functional Description ADIV ADLPC ADLSMP MODE COMPLETE 2 ADCO COCO AIEN ADCH 1 ADCK MCU STOP CONTROL SEQUENCER ADHWT ADICLK ADCLK ADSCR ACLKEN ASYNC CLOCK GENERATOR ACLK CLOCK DIVIDE BUS CLOCK ••• ADVIN ABORT CONVERT TRANSFER AD0 SAMPLE INITIALIZE ALTERNATE CLOCK SOURCE SAR CONVERTER AIEN 1 COCO 2 INTERRUPT ADn VREFH VREFL DATA REGISTERS ADRH:ADRL Figure 3-2.
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Analog-to-Digital Converter (ADC10) Module clocks are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV[1:0] bits and can be divide-by 1, 2, 4, or 8. 3.3.2 Input Select and Pin Control Only one analog input may be used for conversion at any given time. The channel select bits in ADSCR are used to select the input signal for conversion. 3.3.
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Functional Description Upon reset or when a conversion is otherwise aborted, the ADC10 module will enter a low power, inactive state. In this state, all internal clocks and references are disabled. This state is entered asynchronously and immediately upon aborting of a conversion. 3.3.3.4 Total Conversion Time The total conversion time depends on many factors such as sample time, bus frequency, whether ACLKEN is set, and synchronization time. The total conversion time is summarized in Table 3-1. Table 3-1.
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Analog-to-Digital Converter (ADC10) Module 3.3.4 Sources of Error Several sources of error exist for ADC conversions. These are discussed in the following sections. 3.3.4.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 15 kΩ and input capacitance of approximately 10 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.
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Functional Description 3.3.4.4 Code Width and Quantization Error The ADC10 quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step ideally has the same height (1 code) and width. The width is defined as the delta between the transition points from one code to the next. The ideal code width for an N bit converter (in this case N can be 8 or 10), defined as 1LSB, is: 1LSB = (VREFH–VREFL) / 2N Because of this quantization, there is an inherent quantization error.
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Analog-to-Digital Converter (ADC10) Module 3.4 Interrupts When AIEN is set, the ADC10 is capable of generating a CPU interrupt after each conversion. A CPU interrupt is generated when the conversion completes (indicated by COCO being set). COCO will set at the end of a conversion regardless of the state of AIEN. 3.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 3.5.
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I/O Signals break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the second step clears the status bit. 3.7 I/O Signals The ADC10 module shares its pins with general-purpose input/output (I/O) port pins. See Figure 3-1 for port location of these shared pins. The ADC10 on this MCU uses VDD and VSS as its supply and reference pins. This MCU does not have an external trigger source. 3.7.
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Analog-to-Digital Converter (ADC10) Module charging. If externally available, connect the VREFL pin to the same potential as VSSA at the single point ground location. 3.7.5 ADC10 Channel Pins (ADn) The ADC10 has multiple input channels. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. 0.01 μF capacitors with good high-frequency characteristics are sufficient.
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Registers If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in long-sample mode (ADLSMP = 1). When clear, the ADC10 will perform a single conversion (single conversion mode) each time ADSCR is written (assuming the ADCH[4:0] bits do not decode all 1s).
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Analog-to-Digital Converter (ADC10) Module Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 3-4. ADC10 Data Register High (ADRH), 8-Bit Mode Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 AD9 AD8 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 3-5. ADC10 Data Register High (ADRH), 10-Bit Mode 3.8.3 ADC10 Result Low Register (ADRL) This register holds the LSBs of the result.
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Registers ADIV[1:0] — ADC10 Clock Divider Bits ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK. Table 3-3 shows the available clock configurations. Table 3-3.
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Analog-to-Digital Converter (ADC10) Module MC68HC908QYA/QTA Family Data Sheet, Rev.
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Chapter 4 Auto Wakeup Module (AWU) 4.1 Introduction This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. Figure 4-1 is a block diagram of the AWU.
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Auto Wakeup Module (AWU) 4.3 Functional Description The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests, with the difference that instead of a pin, the interrupt signal is generated by an internal logic. Entering stop mode will enable the auto wakeup generation logic.
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Low-Power Modes 4.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.5.1 Wait Mode The AWU module is inactive in wait mode. 4.5.2 Stop Mode When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
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Auto Wakeup Module (AWU) 4.6.2 Keyboard Status and Control Register The keyboard status and control register (KBSCR): • Flags keyboard/auto wakeup interrupt requests • Acknowledges keyboard/auto wakeup interrupt requests • Masks keyboard/auto wakeup interrupt requests Read: Bit 7 6 5 4 3 0 0 0 0 KEYF Write: Reset: 2 0 ACKK 0 0 0 0 0 0 1 Bit 0 IMASKK MODEK 0 0 = Unimplemented Figure 4-3.
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Registers AWUIE — Auto Wakeup Interrupt Enable Bit This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears AWUIE. 1 = Auto wakeup enabled as interrupt input 0 = Auto wakeup not enabled as interrupt input NOTE KBIE5–KBIE0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 9.8.2 Keyboard Interrupt Enable Register (KBIER). 4.6.
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Auto Wakeup Module (AWU) COPRS (In Stop Mode) — Auto Wakeup Period Selection Bit, depends on OSCSTOPEN in CONFIG2 and bus clock source (BUSCLKX2). 1 = Auto wakeup short cycle = 512 × (INTRCOSC or BUSCLKX2) 0 = Auto wakeup long cycle = 16,384 × (INTRCOSC or BUSCLKX2) SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096 BUSCLKX4 cycle delay.
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Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2).
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Configuration Register (CONFIG) IRQPUD — IRQ Pin Pullup Control Bit 1 = Internal pullup is disconnected 0 = Internal pullup is connected between IRQ pin and VDD IRQEN — IRQ Pin Function Selection Bit 1 = Interrupt request function active in pin 0 = Interrupt request function inactive in pin OSCENINSTOP— Oscillator Enable in Stop Mode Bit OSCENINSTOP, when set, will allow the clock source to continue to generate clocks in stop mode.
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Functional Description LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. 1 = LVI module power disabled 0 = LVI module power enabled LVITRIP — LVI Trip Point Selection Bit LVITRIP selects the voltage operating mode of the LVI module. The voltage mode selected for the LVI should match the operating VDD for the LVI’s voltage trip points for each of the modes.
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Configuration Register (CONFIG) MC68HC908QYA/QTA Family Data Sheet, Rev.
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Chapter 6 Computer Operating Properly (COP) 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the configuration 1 (CONFIG1) register. 6.
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Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 262,128 BUSCLKX4 cycle overflow option, the internal 12.8-MHz oscillator gives a COP timeout period of 20.48 ms.
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Interrupts 6.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register (CONFIG). 6.4 Interrupts The COP does not generate CPU interrupt requests. 6.5 Monitor Mode The COP is disabled in monitor mode when VTST is present on the IRQ pin. 6.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 6.6.
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Computer Operating Properly (COP) MC68HC908QYA/QTA Family Data Sheet, Rev.
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Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 7.
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Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
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CPU Registers 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
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Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 7-6.
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Arithmetic/Logic Unit (ALU) Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
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Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set.
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Instruction Set Summary V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 (A) & (M) BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Tabl
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Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP Clear Compare A with M Complement (One’s Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Compare X with M DAA Decimal Adjust A Decrement DIV Divide INC opr INCA INCX INC opr,X INC ,X INC opr,SP Exclusive OR M with A Increment DIR INH INH 0 – – 0 1 – INH IX1 IX SP1
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Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine LDHX #opr LDHX opr Load H:X from M 2 3 4 3 2 PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – 1 PC ← Unconditional Address DIR EXT – – – – – – IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A ← (M) IMM DIR EXT IX2 0 – – – IX1 IX SP1 SP2 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 H:
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Central Processor Unit (CPU) V H I N Z C Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 7-1.
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Opcode Map SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte – – 1 – – – INH 83 9 CCR ← (A) INH 84 2 X ← (A) – – – – – – INH 97 1 A ← (CCR) – – – – – – INH 85 (A) – $00 or (X) – $00 or (M) – $00 DIR INH INH 0 – – – IX1 IX SP1 H:X ← (SP) + 1 – – – – – – INH 95 2 A ← (X) – – – – – – INH
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MSB Branch REL DIR INH 3 4 0 1 2 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR 3 BR
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Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. IRQ functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A zero disables the IRQ function and IRQ will assume the other shared functionalities. A one enables the IRQ function. See Chapter 5 Configuration Register (CONFIG) for more information on enabling the IRQ pin. The IRQ pin shares its pin with general-purpose input/output (I/O) port pins.
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External Interrupt (IRQ) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODU
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Functional Description RESET ACK TO CPU FOR BIL/BIH INSTRUCTIONS INTERNAL ADDRESS BUS IRQ VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D CLR Q CK IRQ IRQ LATCH SYNCHRONIZER IRQ INTERRUPT REQUEST IMASK MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC Figure 8-2. IRQ Module Block Diagram 8.3.1 MODE = 1 If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive.
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External Interrupt (IRQ) 8.4 Interrupts The following IRQ source can generate interrupt requests: • Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests. 8.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 8.5.1 Wait Mode The IRQ module remains active in wait mode.
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Registers 8.8 Registers The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • Masks the IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin Read: Bit 7 6 5 4 3 2 0 0 0 0 IRQF 0 Write: Reset: ACK 0 0 0 0 0 1 Bit 0 IMASK MODE 0 0 0 = Unimplemented Figure 8-3.
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External Interrupt (IRQ) MC68HC908QYA/QTA Family Data Sheet, Rev.
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Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides independently maskable external interrupts. The KBI shares its pins with general-purpose input/output (I/O) port pins. See Figure 9-1 for port location of these shared pins. 9.
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Keyboard Interrupt Module (KBI) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH POWER SUPPLY COP MODULE 6-CHANNEL 10-BIT ADC VDD DEVELOPMENT SUPP
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Functional Description INTERNAL BUS VECTOR FETCH DECODER ACKK RESET 1 KBI0 0 S VDD KBIE0 TO PULLUP/ PULLDOWN ENABLE KBIP0 KEYF D CLR Q CK 1 KBIx 0 KBI LATCH S IMASKK KBIEx TO PULLUP/ PULLDOWN ENABLE KBIPx SYNCHRONIZER MODEK KEYBOARD INTERRUPT REQUEST AWUIREQ (SEE Figure 4-1) Figure 9-2. Keyboard Interrupt Block Diagram The KBI vector fetch or software clear and the return of all enabled keyboard interrupt pins to a deasserted level may occur in any order.
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Keyboard Interrupt Module (KBI) 9.3.2 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup or pulldown device to pull the pin to its deasserted level. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting IMASKK in KBSCR. 2. Enable the KBI polarity by setting the appropriate KBIPx bits in KBIPR. 3.
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I/O Signals 9.7 I/O Signals The KBI module can share its pins with the general-purpose I/O pins. See Figure 9-1 for the port pins that are shared. 9.7.1 KBI Input Pins (KBIx:KBI0) Each KBI pin is independently programmable as an external interrupt source. KBI pin polarity can be controlled independently. Each KBI pin when enabled will automatically configure the appropriate pullup/pulldown device based on polarity. 9.
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Keyboard Interrupt Module (KBI) 9.8.2 Keyboard Interrupt Enable Register (KBIER) KBIER enables or disables each keyboard interrupt pin. Bit 7 Read: 0 Write: Reset: 0 6 5 4 3 2 1 Bit 0 AWUIE KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 = Unimplemented Figure 9-4. Keyboard Interrupt Enable Register (KBIER) KBIE5–KBIE0 — Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch KBI interrupt requests.
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Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction The low-voltage inhibit (LVI) module is provided as a system protection mechanism to prevent the MCU from operating below a certain operating supply voltage level. The module has several configuration options to allow functionality to be tailored to different system level demands. The configuration registers (see Chapter 5 Configuration Register (CONFIG)) contain control bits for this module. 10.
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Low-Voltage Inhibit (LVI) The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared, the default state at power-on reset, VTRIPF is configured for the lower VDD operating range. The actual trip points are specified in 16.5 5-V DC Electrical Characteristics and 16.8 3-V DC Electrical Characteristics.
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LVI Interrupts 10.4 LVI Interrupts The LVI module does not generate interrupt requests. 10.5 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 10.5.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 10.5.
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Low-Voltage Inhibit (LVI) MC68HC908QYA/QTA Family Data Sheet, Rev.
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Chapter 11 Oscillator (OSC) Module 11.1 Introduction The oscillator (OSC) module is used to provide a stable clock source for the MCU system and bus. The OSC shares its pins with general-purpose input/output (I/O) port pins. See Figure 11-1 for port location of these shared pins. The OSC2EN bit is located in the port A pull enable register (PTAPUEN) on this MCU. See Chapter 12 Input/Output Ports (PORTS) for information on PTAPUEN register. 11.
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Oscillator (OSC) Module PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT VDD POWER SUPPLY MONIT
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Functional Description 11.3.1.2 XTAL Oscillator Clock (XTALCLK) XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 11-2 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. The frequency of XTALCLK can be unstable at start up. 11.3.1.
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Oscillator (OSC) Module copy the trim value from $FFC0 or $FFC1 into OSCTRIM if needed. The factory trim value provides the accuracy required for communication using forced monitor mode. Some production programmers erase the factory trim values, so confirm with your programmer vendor that the trim values at $FFC0 and $FFC1 are preserved, or are re-trimmed. Trimming the device in the user application board will provide the most accurate trim value. 11.3.2.
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Functional Description The oscillator configuration uses five components: • Crystal, X1 • Fixed capacitor, C1 • Tuning capacitor, C2 (can also be a fixed capacitor) • Feedback resistor, RB • Series resistor, RS (optional) NOTE The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals.
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Oscillator (OSC) Module 11.3.5 RC Oscillator The RC oscillator circuit is designed for use with an external resistor (REXT) to provide a clock source with a tolerance within 25% of the expected frequency. See Figure 11-3. The capacitor (C) for the RC oscillator is internal to the MCU. The REXT value must have a tolerance of 1% or less to minimize its effect on the frequency. In this configuration, the OSC2 pin can be used as general-purpose input/output (I/O) port pins or other alternative pin function.
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OSC During Break Interrupts 11.6 OSC During Break Interrupts There are no status flags associated with the OSC module. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See BFCR in the SIM section of this data sheet. To allow software to clear status bits during a break interrupt, write a 1 to BCFE.
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Oscillator (OSC) Module 11.8 Registers The oscillator module contains two registers: • Oscillator status and control register (OSCSC) • Oscillator trim register (OSCTRIM) 11.8.1 Oscillator Status and Control Register The oscillator status and control register (OSCSC) contains the bits for switching between internal and external clock sources. If the application uses an external crystal, bits in this register are used to select the crystal oscillator amplifier necessary for the desired crystal.
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Registers ECFS1:ECFS0 — External Crystal Frequency Select Bits These read/write bits enable the specific amplifier for the crystal frequency range. Refer to oscillator characteristics table in the Electricals section for information on maximum external clock frequency versus supply voltage.
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Oscillator (OSC) Module MC68HC908QYA/QTA Family Data Sheet, Rev.
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Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction The MC68HC08QY1A, MC68HC08QY2A and MC68HC08QY4A have thirteen bidirectional input-output (I/O) pins and one input only pin. The MC68HC08QT1A, MC68HC08QT2A and MC68HC08QT4A has five bidirectional I/O pins and one input only pin. All I/O pins are programmable as inputs or outputs. 12.2 Unused Pin Termination Input pins and I/O port pins that are not used in the application must be terminated.
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Input/Output Ports (PORTS) 12.3.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the six port A pins. Bit 7 Read: Write: R 6 AWUL 5 4 3 PTA5 PTA4 PTA3 Reset: 2 PTA2 1 Bit 0 PTA1 PTA0 Unaffected by reset = Unimplemented Figure 12-1. Port A Data Register (PTA) PTA[5:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A.
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Port A READ DDRA PTAPUEx INTERNAL DATA BUS WRITE DDRA DDRAx RESET WRITE PTA PULLUP PTAx PTAx READ PTA Figure 12-3. Port A I/O Circuit NOTE Figure 12-3 does not apply to PTA2 When DDRAx is a 1, reading PTA reads the PTAx data latch. When DDRAx is a 0, reading PTA reads the logic level on the PTAx pin. The data latch can always be written, regardless of the state of its data direction bit. 12.3.
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Input/Output Ports (PORTS) 12.3.4 Port A Summary Table The following table summarizes the operation of the port A pins when used as a general-purpose input/output pins. Table 12-1. Port A Pin Functions PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode Accesses to DDRA Accesses to PTA Read/Write Read Write 1 0 X(1) Input, VDD(2) DDRA5–DDRA0 Pin PTA5–PTA0(3) 0 0 X Input, Hi-Z(4) DDRA5–DDRA0 Pin PTA5–PTA0(3) X 1 X Output DDRA5–DDRA0 PTA5–PTA0 PTA5–PTA0(5) 1. X = don’t care 2.
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Port B 12.4.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer. Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 Figure 12-6.
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Input/Output Ports (PORTS) 12.4.3 Port B Input Pullup Enable Register The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRBx bit is configured as output.
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Chapter 13 System Integration Module (SIM) 13.1 Introduction This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 13-1. The SIM is a system state controller that coordinates CPU and exception timing.
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System Integration Module (SIM) MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) STOP/WAIT CONTROL SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK BUSCLKX4 (FROM OSCILLATOR) BUSCLKX2 (FROM OSCILLATOR) ÷2 VDD INTERNAL PULL-UP RESET PIN LOGIC CLOCK CONTROL INTERNAL CLOCKS CLOCK GENERATORS POR CONTROL ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) MASTER RESET CONTROL RESET PIN CONTROL LVI RESET (FROM LVI MODULE) SIM RESET STATUS
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Reset and System Initialization 13.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four. 13.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The IBUS clocks start upon completion of the time out. 13.3.
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System Integration Module (SIM) 13.4.2 Active Resets from Internal Sources The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when describing activity on the RST pin. NOTE For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 13-4.
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Reset and System Initialization 13.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power on, the following events occur: • A POR pulse is generated. • The internal reset signal is asserted.
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System Integration Module (SIM) If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 13.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset.
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Exception Control 13.6 Exception Control Normal sequential program execution can be changed in three different ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 3. Break interrupts 13.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 13-7 flow charts the handling of system interrupts.
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System Integration Module (SIM) FROM RESET BREAK INTERRUPT? I BIT SET? YES NO YES I BIT SET? NO IRQ INTERRUPT? YES NO TIMER INTERRUPT? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR (AS MANY INTERRUPTS AS EXIST ON CHIP) FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 13-7. Interrupt Processing MC68HC908QYA/QTA Family Data Sheet, Rev.
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Exception Control MODULE INTERRUPT I BIT ADDRESS BUS DUMMY DATA BUS SP DUMMY SP – 1 SP – 2 PC – 1[7:0] PC – 1[15:8] SP – 3 X SP – 4 A VECT H CCR VECT L V DATA H START ADDR V DATA L OPCODE R/W Figure 13-8. Interrupt Entry MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS SP – 3 CCR SP – 2 A SP – 1 X SP PC PC + 1 PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND R/W Figure 13-9.
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System Integration Module (SIM) 13.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. 13.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources.
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Exception Control 13.6.2.1 Interrupt Status Register 1 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 13-11. Interrupt Status Register 1 (INT1) IF1–IF6 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 13-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1 — Always read 0 13.6.2.
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System Integration Module (SIM) 13.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 13.6.4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output. (See Chapter 15 Development Support.) The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
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Low-Power Modes In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR).
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System Integration Module (SIM) The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 13-17 shows stop mode entry timing and Figure 13-18 shows the stop mode recovery time from interrupt or break NOTE To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
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SIM Registers POR — Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN — External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP — Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented address) 1 = Last reset
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System Integration Module (SIM) MC68HC908QYA/QTA Family Data Sheet, Rev.
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Chapter 14 Timer Interface Module (TIM) 14.1 Introduction This section describes the timer interface module (TIM). The TIM module is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. The TIM module shares its pins with general-purpose input/output (I/O) port pins. See Figure 14-1 for port location of these shared pins. 14.
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Timer Interface Module (TIM) PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK
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Functional Description TCLK TCLK (IF AVAILABLE) PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TCNTH:TCNTL TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 TOV0 ELS0B ELS0A CH0MAX 16-BIT COMPARATOR TCH0H:TCH0L PORT LOGIC TCH0 CH0F 16-BIT LATCH CH0IE MS0A INTERRUPT LOGIC MS0B INTERNAL BUS TOV1 CHANNEL 1 ELS1B ELS1A CH1MAX 16-BIT COMPARATOR TCH1H:TCH1L PORT LOGIC TCH1 CH1F 16-BIT LATCH MS1A CH1IE INTERRUPT LOGIC Figure
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Timer Interface Module (TIM) the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 14.3.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
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Functional Description The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 14.3.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 14.3.4 Pulse Width Modulation (PWM).
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Timer Interface Module (TIM) channel. Writing to the active channel registers is the same as generating unbuffered PWM signals. 14.3.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the counter by setting the TIM stop bit, TSTOP. b. Reset the counter and prescaler by setting the TIM reset bit, TRST. 2.
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Interrupts 14.4 Interrupts The following TIM sources can generate interrupt requests: • TIM overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow interrupt requests. TOF and TOIE are in the TSC register. • TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare occurs on channel x.
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Timer Interface Module (TIM) 14.7 I/O Signals The TIM module can share its pins with the general-purpose I/O pins. See Figure 14-1 for the port pins that are shared. 14.7.1 TIM Channel I/O Pins (TCH1:TCH0) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. TCH0 can be configured as buffered output compare or buffered PWM pin. 14.7.
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Registers If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing a 1 to TOF has no effect. 1 = Counter has reached modulo value 0 = Counter has not reached modulo value TOIE — TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set.
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Timer Interface Module (TIM) 14.8.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
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Registers 14.8.
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Timer Interface Module (TIM) Setting MS0B causes the contents of TSC1 to be ignored by the TIM and reverts TCH1 to general-purpose I/O. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA — Mode Select Bit A When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 14-2.
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Registers TOVx — Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the counter overflows. When channel x is an input capture channel, TOVx has no effect. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow. NOTE When TOVx is set, a counter overflow takes precedence over a channel x output compare if both occur at the same time.
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Timer Interface Module (TIM) MC68HC908QYA/QTA Family Data Sheet, Rev.
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Chapter 15 Development Support 15.1 Introduction This section describes the break module, the monitor module (MON), and the monitor mode entry methods. 15.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
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Development Support PTA0/TCH0/AD0/KBI0 CLOCK GENERATOR PTA3/RST/KBI3 PTA PTA2/IRQ/KBI2/TCLK DDRA PTA1/TCH1/AD1/KBI1 KEYBOARD INTERRUPT MODULE PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 SINGLE INTERRUPT MODULE AUTO WAKEUP MODULE DDRB PTB0/AD4 PTB1/AD5 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTB M68HC08 CPU LOW-VOLTAGE INHIBIT 2-CHANNEL 16-BIT TIMER MODULE MC68HC908QY4A MC68HC908QY4A 128 BYTES 4096 BYTES USER RAM USER FLASH COP MODULE 6-CHANNEL 10-BIT ADC DEVELOPMENT SUPPORT MONITOR ROM BREAK MODULE V
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Break Module (BRK) The break interrupt timing is: • When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. • When a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. • When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction is executed.
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Development Support 15.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Read: Write: Reset: Bit 7 6 BRKE BRKA 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 15-3. Break Status and Control Register (BRKSCR) BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit.
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Break Module (BRK) 15.2.2.3 Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU is in a state of break interrupt with monitor mode. Read: Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: Bit 0 BDCOP 0 = Unimplemented Figure 15-6. Break Auxiliary Register (BRKAR) BDCOP — Break Disable COP Bit This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.
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Development Support BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break 15.2.3 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. If enabled, the break module will remain enabled in wait and stop modes.
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Monitor Module (MON) POR RESET NO CONDITIONS FROM Table 15-1 PTA0 = 1, RESET VECTOR BLANK? IRQ = VTST? YES PTA0 = 1, PTA1 = 1, AND PTA4 = 0? NO NO YES YES FORCED MONITOR MODE NORMAL USER MODE NORMAL MONITOR MODE INVALID USER MODE HOST SENDS 8 SECURITY BYTES IS RESET POR? YES NO YES ARE ALL SECURITY BYTES CORRECT? ENABLE FLASH NO DISABLE FLASH MONITOR MODE ENTRY DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED) EXECUTE MONITOR CODE YES DOES RESET OCCUR? NO Figure 15-9.
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Development Support VDD VDD 10 kΩ* VDD RST (PTA3) MAX232 1 1 μF + 3 4 1 μF + VDD 16 C1+ + 1 kΩ 9.1 V 1 μF 10 kΩ + 74HC125 3 2 9 8 PTA4 74HC125 5 6 10 10 kΩ* PTA0 4 VSS 1 5 10 kΩ* IRQ (PTA2) VDD V– 6 7 VDD PTA1 DB9 3 1 μF V+ 2 C2+ OSC1 (PTA5) 1 μF 15 C1– 0.1 μF VTST + 5 C2– 2 9.8304 MHz CLOCK * Value not critical Figure 15-10. Monitor Mode Circuit (External Clock, with High Voltage) VDD N.C. 1 1 μF 3 4 1 μF + C1+ C1– C2+ 5 C2– VDD 16 + 9.
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Monitor Module (MON) VDD N.C. RST (PTA3) VDD 0.1 μF MAX232 1 1 μF + 3 4 1 μF + C1+ C1– C2+ 5 C2– VDD + 3 1 μF 15 + OSC1 (PTA5) IRQ (PTA2) 1 μF VDD V– 6 1 μF 7 10 8 9 10 kΩ 74HC125 5 6 + 74HC125 3 2 PTA1 N.C. PTA4 N.C. 10 kΩ* V+ 2 DB9 2 N.C. 16 PTA0 VSS 4 1 5 * Value not critical Figure 15-12.
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Development Support Table 15-1. Monitor Mode Signal Requirements and Options Mode Serial Mode CommuniSelection RST Reset IRQ cation (PTA2) (PTA3) Vector PTA0 PTA1 PTA4 Communication Speed COP External Bus Clock Frequency Comments Baud Rate VTST VDD X 1 1 0 Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VDD X $FFFF (blank) 1 X X Disabled 9.8304 MHz 2.4576 MHz 9600 Provide external clock at OSC1. VSS X $FFFF (blank) 1 X X Disabled X 3.
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Monitor Module (MON) NOTE If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR). Once the reset vector has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to enter monitor mode. If monitor mode was entered as a result of the reset vector being blank, the COP is always disabled regardless of the state of IRQ.
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Development Support 15.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT Figure 15-13. Monitor Data Format 15.3.1.5 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal.
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Monitor Module (MON) FROM HOST 4 ADDRESS HIGH READ READ 4 1 ADDRESS HIGH 1 ADDRESS LOW 4 ECHO Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times ADDRESS LOW DATA 1 3, 2 4 RETURN 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte. Figure 15-15.
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Development Support Table 15-4. WRITE (Write Memory) Command Description Operand Data Returned Opcode Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence FROM HOST WRITE WRITE ADDRESS HIGH ADDRESS HIGH ADDRESS LOW ADDRESS LOW DATA DATA ECHO Table 15-5.
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Monitor Module (MON) Table 15-7. READSP (Read Stack Pointer) Command Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence FROM HOST READSP SP HIGH READSP SP LOW ECHO RETURN Table 15-8.
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Development Support 15.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user-defined data. NOTE Do not leave locations $FFF6–$FFFD blank. For security reasons, program locations $FFF6–$FFFD even if they are not used for vectors.
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Chapter 16 Electrical Specifications 16.1 Introduction This section contains electrical and timing specifications. 16.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE This device is not guaranteed to operate properly at the maximum ratings. Refer to 16.5 5-V DC Electrical Characteristics and 16.8 3-V DC Electrical Characteristics for guaranteed operating conditions.
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Electrical Specifications 16.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range Symbol Value Unit Temperature Code TA (TL to TH) – 40 to +125 – 40 to +105 – 40 to +85 °C M V C VDD 2.7 to 5.5 V — 16.
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5-V DC Electrical Characteristics 16.5 5-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.4 VDD –1.5 VDD –0.8 — — — — — — — — 50 — — — — — — 0.4 1.5 0.8 Unit Output high voltage ILoad = –2.0 mA, all I/O pins ILoad = –10.0 mA, all I/O pins ILoad = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 1.6 mA, all I/O pins ILoad = 10.0 mA, all I/O pins ILoad = 15.
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Electrical Specifications 16.6 Typical 5-V Output Drive Characteristics 1.6 1.4 VDD-VOH (V) 1.2 1.0 5V PTA 0.8 5V PTB 0.6 0.4 0.2 0.0 0 -5 -10 -15 -20 -25 -30 IOH (mA) Figure 16-1. Typical 5-Volt Output High Voltage versus Output High Current (25°C) 1.6 1.4 1.2 VOL (V) 1.0 5V PTA 0.8 5V PTB 0.6 0.4 0.2 0.0 0 5 10 15 20 25 30 IOL (mA) Figure 16-2. Typical 5-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QYA/QTA Family Data Sheet, Rev.
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5-V Control Timing 16.7 5-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBUS) — 8 MHz Internal clock period (1/fOP) tcyc 125 — ns RST input pulse width low(2) tRL 100 — ns IRQ interrupt pulse width low (edge-triggered)(2) tILIH 100 — ns — tcyc (2) tILIL IRQ interrupt pulse period (3) Note 1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VSS, unless otherwise noted. 2.
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Electrical Specifications 16.8 3-V DC Electrical Characteristics Characteristic(1) Symbol Min Typ(2) Max VDD –0.3 VDD –1.0 VDD –0.8 — — — — — — — — 50 — — — — — — 0.3 1.0 0.8 Unit Output high voltage ILoad = –0.6 mA, all I/O pins ILoad = –4.0 mA, all I/O pins ILoad = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only VOH Maximum combined IOH (all I/O pins) IOHT Output low voltage ILoad = 0.5 mA, all I/O pins ILoad = 6.0 mA, all I/O pins ILoad = 10.
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Typical 3-V Output Drive Characteristics 16.9 Typical 3-V Output Drive Characteristics 1.2 1.0 VDD-VOH (V) 0.8 3V PTA 0.6 3V PTB 0.4 0.2 0.0 0 -5 -10 -15 -20 -25 IOH (mA) Figure 16-4. Typical 3-Volt Output High Voltage versus Output High Current (25°C) 1.2 1.0 0.8 VOL (V) 3V PTA 0.6 3V PTB 0.4 0.2 0.0 0 5 10 15 20 25 IOL (mA) Figure 16-5. Typical 3-Volt Output Low Voltage versus Output Low Current (25°C) MC68HC908QYA/QTA Family Data Sheet, Rev.
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Electrical Specifications 16.10 3-V Control Timing Characteristic(1) Symbol Min Max Unit Internal operating frequency fOP (fBus) — 4 MHz Internal clock period (1/fOP) tcyc 250 — ns tRL 200 — ns IRQ interrupt pulse width low (edge-triggered)(2) tILIH 200 — ns IRQ interrupt pulse period(2) tILIL Note(3) — tcyc RST input pulse width low (2) 1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2.
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Oscillator Characteristics 16.11 Oscillator Characteristics Characteristic Symbol Min Typ Max — — — 4 8 12.8 — — — Unit (1) Internal oscillator frequency ICFS1:ICFS0 = 00 ICFS1:ICFS0 = 01 ICFS1:ICFS0 = 10 (not allowed if VDD <2.7V) fINTCLK MHz Trim accuracy(2)(3) ΔTRIM_ACC — ± 0.4 — % Deviation from trimmed Internal oscillator(3)(4) 4, 8, 12.8MHz, VDD ± 10%, 0 to 70°C 4, 8, 12.
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Electrical Specifications 12 5V 25 oC RC FREQUENCY,RCCLK f (MHz) 10 8 6 4 2 0 0 10 20 30 40 50 60 Rext (k ohms) Figure 16-7. RC versus Frequency (5 Volts @ 25°C) 12 3V 25 oC RC FREQUENCY,RCCLK f (MHz) 10 8 6 4 2 0 0 10 20 30 40 50 60 Rext (k ohms) Figure 16-8. RC versus Frequency (3 Volts @ 25°C) MC68HC908QYA/QTA Family Data Sheet, Rev.
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Supply Current Characteristics 16.12 Supply Current Characteristics Voltage Bus Frequency (MHz) Symbol Typ(2) Max Unit Run mode VDD supply current(3) 5.0 3.0 3.2 3.2 RIDD 6.0 3.1 7.0 3.8 mA Wait mode VDD supply current(4) 5.0 3.0 3.2 3.2 WIDD 1.8 1.1 2.5 1.75 mA 0.5 — — 20 150 1.2 2.0 5.0 — — 0.36 — — 4 130 1.0 1.2 4.
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Electrical Specifications 12 11 10 9 Internal OSC (No A/D, ESCI, SPI) 8 Internal OSC all Modules enabled IDD 7 6 External Reference No A/D 5 External Reference All modules enabled 4 3 2 1 0 0 1 2 3 4 5 FREQUENCY 6 7 8 9 Figure 16-9. Typical 5-Volt Run Current versus Bus Frequency (25•C) 3 2.5 2 Internal OSC (No A/D, ESCI, SPI) Idd(mA) Internal OSC all Modules enabled External OSC (No A/D) 1.5 External OSC all Modules Enabled 1 0.
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ADC10 Characteristics 16.13 ADC10 Characteristics Characteristic Conditions Supply voltage Absolute Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 VDD < 3.3 V (3.0 V Typ) Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 VDD < 3.3 V (3.0 V Typ) Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 VDD < 3.3 V (3.0 V Typ) Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 VDD < 3.3 V (3.0 V Typ) VDD < 5.5 V (5.0 V Typ) VDD < 5.5 V (5.0 V Typ) Symbol Min Typ(1) Max Unit VDD 2.7 — 5.
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Electrical Specifications Characteristic Conditions Symbol 10-bit mode Integral non-linearity Typ(1) Max 0 ±0.5 — 0 ±0.3 — 0 ±0.5 — 0 ±0.3 — 0 ±0.5 — 0 ±0.3 — — — ±0.5 — — ±0.5 0 ±0.2 ±5 INL 8-bit mode 10-bit mode Zero-scale error 8-bit mode 10-bit mode Full-scale error 8-bit mode 10-bit mode Quantization error 8-bit mode 10-bit mode Input leakage error 8-bit mode Bandgap voltage input(6) Min EZS EFS EQ EIL VBG Unit Comment LSB 0 ±0.1 ±1.2 1.17 1.245 1.
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Timer Interface Module Characteristics 16.14 Timer Interface Module Characteristics Characteristic Symbol Min Max Unit tTH, tTL 2 — tcyc tTLTL Note(2) — tcyc tTCL, tTCH tcyc + 5 — ns Timer input capture pulse width(1) Timer input capture period Timer input clock pulse width(1) 1. Values are based on characterization results, not tested in production. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
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Electrical Specifications 16.15 Memory Characteristics Characteristic Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz VPGM/ERASE 2.7 — 5.5 V fRead(2) 0 — 8M Hz FLASH page erase time <1 K cycles >1 K cycles tErase 0.9 3.6 1 4 1.1 5.
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Chapter 17 Ordering Information and Mechanical Specifications 17.1 Introduction This section contains order numbers for the MC68HC908QY1A, MC68HC908QY2A, MC68HC908QY4A, MC68HC908QT1A, MC68HC908QT2A, and MC69HC908QT4A. Dimensions are given for: • 8-pin plastic dual in-line package (PDIP) • 8-pin small outline integrated circuit (SOIC) package • 8-pin dual flat no lead (DFN) package • 16-pin PDIP • 16-pin SOIC • 16-pin thin shrink small outline package (TSSOP) 17.2 Ordering Information Table 17-1.
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Ordering Information and Mechanical Specifications 17.3 Orderable Part Numbering System 17.3.1 Consumer and Industrial Orderable Part Numbering System MC 9 08 QY2A C XX E STATUS (MC = CONSUMER AND INDUSTRIAL FULLY QUALIFIED) Pb FREE INDICATOR PACKAGE DESIGNATOR FQ = 8-PIN DFN DW = 8-PIN SOIC P = 8-PIN DIP DT = 16-PIN TSSOP DW = 16 PIN SOIC P = 16-PIN DIP MEMORY (9 = FLASH BASED) CORE FAMILY TEMPERATURE RANGE C = –40°C to +85°C M = –40°C to +125°C 17.3.
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Mechanical Drawings Case 626 page 1 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Ordering Information and Mechanical Specifications Case 626 page 2 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Mechanical Drawings Case 626 page 3 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Ordering Information and Mechanical Specifications Case 968 page 1 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Mechanical Drawings Case 968 page 2 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Ordering Information and Mechanical Specifications Case 968 page 3 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Mechanical Drawings Case 1452 page 1 of 4 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Ordering Information and Mechanical Specifications Case 1452 page 2 of 4 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Mechanical Drawings Case 1452 page 3 of 4 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Ordering Information and Mechanical Specifications Case 1452 page 4 of 4 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Mechanical Drawings Case 648 page 1 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Ordering Information and Mechanical Specifications Case 648 page 2 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Mechanical Drawings Case 648 page 3 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Ordering Information and Mechanical Specifications Case 751G page 1 of 2 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Mechanical Drawings Case 751G page 2 of 2 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Ordering Information and Mechanical Specifications Case 948F page 1 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Mechanical Drawings Case 948F page 2 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Ordering Information and Mechanical Specifications Case 948F page 3 of 3 MC68HC908QYA/QTA Family Data Sheet, Rev.
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Appendix A 908QTA/QYxA Conversion Guidelines A.1 Introduction This engineering bulletin describes the 908QTA/QYxA. The 908QTA/QYxA is an enhanced device intended to replace the 908QT/QYx series of devices (referred to as the QY Classic in this document). Customer requests have led to the advanced design of the QYxA that has added adaptability, new features, and contains lead-free packaging.
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• The ADC that is on the QYxA can operate while the MCU is in stop mode allowing lower power operation. This also adds a lower noise environment for precise ADC results. • Enabling an ADC channel no longer overrides the digital I/O function of the associated pin. To prevent the digital I/O from interfering with the ADC read of the pin, the data direction bit associated with the port pin must be set as input.
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A.2.2 Enhanced Oscillator Module (OSC) The QYxA contains a much enhanced oscillator module that allows more options than the QYx Classic. • The ICFS bits in the Oscillator Status and Control Register (OSCSC) allow the Internal Oscillator to be configured for 1-, 2-, or 3.2-MHz operation. Also, the ECFS bits in the same register allow a low, medium, or high crystal frequency range to be selected for the source of the system clock.
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A.2.3 Improved Auto Wakeup Module (AWU) The QYxA contains an AWU that has improved accuracy across voltage and temperature for typical testing. • A new feature provides ability to run the AWU from an alternate source (internal oscillator or external crystal). This is an advantage for an application that needs more accurate AWU operation. • On the QYxA AWU approximate time out will be 16 ms for short time out and 512 ms for long time out when running from the internal 32-kHz RC source.
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A.2.5 Keyboard Interface Module (KBI) Functionality The KBI module for the QYxA has the added capability of: • Triggering a KBI interrupt on the rising or falling edge of an input while the QYx Classic has the capability of triggering on falling edges only. – A new register (Keyboard Interrupt Polarity Register) determines the polarity of KBI and the default state of this register configures the QYxA for triggering on falling edges to be compatible with QYx Classic.
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A.3 Conversion Considerations Enhancements lead to slight differences in operation from QYx Classic to the QYxA. There are a few points that should be considered in the conversion process. • The Monitor ROM changed from 2 K to 1 K in size. This has led to the limitation that programming across page boundaries is no longer supported by the on-chip program range routine. Also, in very rare cases, ROM code improvements could cause customers to have to modify a few instructions in their application code.
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A.5 Development Tools Development hardware used for QYx can be used with QYxA. The QYxA is pin-for-pin compatible with QY Classic and can be placed on existing QY4 Classic hardware. Existing Cyclone/Multilink tools and any programming or evaluation boards will work for the QYxA. Emulation can be done using the EML08QCBLTYE. A.6 Differences in Packaging All QYxA packages will be lead free. All packages that the QYx classic supported will be supported by the QYxA. MC68HC908QYA/QTA Family Data Sheet, Rev.
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MC68HC908QYA/QTA Family Data Sheet, Rev.
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How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.