MC9S08EL32 MC9S08EL16 MC9S08SL16 MC9S08SL8 Data Sheet HCS08 Microcontrollers MC9S08EL32 Rev. 3 7/2008 freescale.
MC9S08EL32 Features 8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (central processor unit) • HC08 instruction set with added BGND instruction • Support for up to 32 interrupt/reset sources On-Chip Memory • FLASH read/program/erase over full operating voltage and temperature • EEPROM in-circuit programmable memory; program and erase while executing FLASH; erase abort • Random-access memory (RAM) • Security circuitry to prevent unauthorized access to RAM and NVM contents Power-Saving Modes • T
MC9S08EL32 Data Sheet Covers MC9S08EL32 MC9S08EL16 MC9S08SL16 MC9S08SL8 MC9S08EL32 Rev. 3 7/2008 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008. All rights reserved.
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Revision Number Revision Date 3 07/2008 Description of Changes Initial public revision © Freescale Semiconductor, Inc., 2008. All rights reserved.
List of Chapters Chapter 1 Device Overview ...................................................................... 19 Chapter 2 Pins and Connections ............................................................. 25 Chapter 3 Modes of Operation ................................................................. 31 Chapter 4 Memory ..................................................................................... 37 Chapter 5 Resets, Interrupts, and General System Control..................
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 Devices in the MC9S08EL32 Series and MC9S08SL16 Series .....................................................19 MCU Block Diagram ......................................................................................................................20 System Clock Distribution ..............................................................................................................23 Chapter 2 Pins and Connections 2.1 2.
Section Number 4.5.5 4.5.6 4.5.7 4.5.8 4.5.9 4.5.10 4.5.11 Title Page Sector Erase Abort ............................................................................................................51 Access Errors ....................................................................................................................52 Block Protection ...............................................................................................................53 Vector Redirection ..........................
Section Number Title Page 6.5.2 Port B Registers ................................................................................................................87 6.5.3 Port C Registers ................................................................................................................91 Chapter 7 Central Processor Unit (S08CPUV3) 7.1 7.2 7.3 7.4 7.5 Introduction .............................................................................................................................
Section Number 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 Title Page Operational Modes ..........................................................................................................123 Mode Switching ..............................................................................................................125 Bus Frequency Divider ...................................................................................................126 Low Power Bit Usage .......................................
Section Number Title Page 10.3.6 Compare Value Low Register (ADCCVL) .....................................................................147 10.3.7 Configuration Register (ADCCFG) ................................................................................147 10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................149 10.3.9 Pin Control 2 Register (APCTL2) ................................................................................
Section Number Title Page 11.6 Interrupts .......................................................................................................................................179 11.6.1 Byte Transfer Interrupt ....................................................................................................179 11.6.2 Address Detect Interrupt .................................................................................................180 11.6.3 Arbitration Lost Interrupt ..........................
Section Number Title Page 12.6.16Byte Transfer Mode Operation .......................................................................................224 12.6.17Oscillator Trimming with SLIC ......................................................................................228 12.6.18Digital Receive Filter ......................................................................................................230 Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Introduction ........................
Section Number Title Page 14.3 Functional Description ..................................................................................................................261 14.3.1 Baud Rate Generation .....................................................................................................261 14.3.2 Transmitter Functional Description ................................................................................262 14.3.3 Receiver Functional Description .......................................
Section Number Title Page 16.6 Interrupts .......................................................................................................................................300 16.6.1 General ............................................................................................................................300 16.6.2 Description of Interrupt Operation .................................................................................301 16.7 The Differences from TPM v2 to TPM v3 ...............
Section Number Title Page A.12.2 TPM/MTIM Module Timing ..........................................................................................348 A.12.3 SPI ...................................................................................................................................349 A.13 Flash and EEPROM Specifications ...............................................................................................352 A.14 EMC Performance ........................................................
Chapter 1 Device Overview The MC9S08EL32 Series and MC9S08SL16 Series are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.1 Devices in the MC9S08EL32 Series and MC9S08SL16 Series Table 1-1 summarizes the feature set available in the MC9S08EL32 Series and MC9S08SL16 Series of MCUs. t Table 1-1.
Chapter 1 Device Overview 1.2 MCU Block Diagram The block diagram in Figure 1-1 shows the structure of the MC9S08EL32 Series. Not all features are available on all devices in all packages. See Table 1-1 for details.
Chapter 1 Device Overview The block diagram in Figure 1-2 shows the structure of the MC9S08SL16 Series.
Chapter 1 Device Overview Table 1-2 provides the functional version of the on-chip modules Table 1-2.
Chapter 1 Device Overview 1.3 System Clock Distribution Figure 1-3 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module function. The following defines the clocks used in this MCU: • BUSCLK — The frequency of the bus is always half of ICSOUT. • ICSOUT — Primary output of the ICS and is twice the bus frequency.
Chapter 1 Device Overview MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 2 Pins and Connections This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 Device Pin Assignment This section describes pin assignments for the MC9S08EL32 Series and MC9S08SL16 Series devices. Not all features are available in all devices. See Table 1-1 for details.
Chapter 2 Pins and Connections 2.2 Recommended System Connections Figure 2-3 shows pin connections that are common to MC9S08EL32 Series and MC9S08SL16 Series application systems. MC9S08EL32 Background Header PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 RPU VDD PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 BKGD/MS PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 VDD RPU 4.7 kΩ–10 kΩ PORT A PTA3/PIA3/SCL/TxD/ADP3 RESET 0.
Chapter 2 Pins and Connections 2.2.2 Oscillator Immediately after reset, the MCU uses an internally generated clock provided by the clock source generator (ICS) module. This internal clock source is used during reset startup and can be enabled as the clock source for stop recovery to avoid the need for a long crystal startup delay. For more information on the ICS, see Chapter 8, “Internal Clock Source (S08ICSV2).
Chapter 2 Pins and Connections NOTE In EMC-sensitive applications, use an external RC filter on RESET. See Figure 2-3 for an example. 2.2.4 Background / Mode Select (BKGD/MS) While in reset, the BKGD/MS pin functions as a mode select pin. Immediately after reset rises, the pin functions as the background pin and can be used for background debug communication.
Chapter 2 Pins and Connections Table 2-1.
Chapter 2 Pins and Connections MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08EL32 Series and MC9S08SL16 Series are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes is described. 3.2 • • • 3.
Chapter 3 Modes of Operation Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running. Non-intrusive commands can be issued through the BKGD/MS pin while the MCU is in run mode; non-intrusive commands can also be executed when the MCU is in the active background mode.
Chapter 3 Modes of Operation Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. The selected mode is entered following the execution of a STOP instruction. Table 3-1.
Chapter 3 Modes of Operation Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the ENBDM bit is set. After entering background debug mode, all background commands are available. 3.
Chapter 3 Modes of Operation Table 3-2.
Chapter 3 Modes of Operation MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 4 Memory 4.1 MC9S08EL32 Series and MC9S08SL16 Series Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08EL32 Series and MC9S08SL16 Series consists of RAM, EEPROM, and FLASH program memory for nonvolatile data storage, and I/O and control/status registers.
Chapter 4 Memory 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor provided equate file for the MC9S08EL32 Series and MC9S08SL16 Series. Vector addresses for excluded features are reserved. Table 4-1.
Chapter 4 Memory 4.3 Register Addresses and Bit Assignments The registers in the MC9S08EL32 Series and MC9S08SL16 Series are divided into these groups: • Direct-page registers are located in the first 128 locations in the memory map; these are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and RAM.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. Table 4-3.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Nonvolatile FLASH registers, shown in Table 4-4, are located in the FLASH memory. These registers include an 8-byte backdoor key, NVBACKKEY, which can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Table 4-4.
Chapter 4 Memory 4.4 RAM The MC9S08EL32 Series and MC9S08SL16 Series includes static RAM. The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed program variables in this area of RAM is preferred. The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode.
Chapter 4 Memory 4.5 FLASH and EEPROM The MC9S08EL32 Series and MC9S08SL16 Series includes FLASH and EEPROM memory intended primarily for program and data storage. In-circuit programming allows the operating program and data to be loaded into FLASH and EEPROM, respectively, after final assembly of the application product. It is possible to program the arrays through the single-wire background debug interface.
Chapter 4 Memory Table 4-5. Program and Erase Times 1 4.5.3 Parameter Cycles of FCLK Time if FCLK = 200 kHz Byte program 9 45 μs Burst program 4 20 μs1 Sector erase 4000 20 ms Mass erase 20,000 100 ms Sector erase abort 4 20 μs1 Excluding start/end overhead Program and Erase Command Execution The FCDIV register must be initialized following any reset and any error flags cleared before beginning command execution. The command execution steps are: 1.
Chapter 4 Memory (1) Required only once WRITE TO FCDIV(1) PROGRAM AND ERASE FLOW after reset. START FACCERR ? 0 CLEAR ERROR WRITE TO FLASH OR EEPROM TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (2) FPVIOL OR FACCERR ? (2) Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NO 0 FCCF ? 1 DONE Figure 4-2. Program and Erase Flowchart 4.5.
Chapter 4 Memory The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst program time provided that the conditions above are met. If the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. This is because the high voltage to the array must be disabled and then enabled again.
Chapter 4 Memory 4.5.5 Sector Erase Abort The sector erase abort operation will terminate the active sector erase operation so that other sectors are available for read and program operations without waiting for the sector erase operation to complete. The sector erase abort command write sequence is as follows: 1. Write to any FLASH or EEPROM address to start the command write sequence for the sector erase abort command. The address and data written are ignored. 2.
Chapter 4 Memory NOTE The FCBEF flag will not set after launching the sector erase abort command. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the FACCERR flag in the FSTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. 4.5.
Chapter 4 Memory 4.5.7 Block Protection The block protection feature prevents the protected region of FLASH or EEPROM from program or erase changes. Block protection is controlled through the FLASH and EEPROM protection register (FPROT). The EPS bits determine the protected region of EEPROM and the FPS bits determine the protected region of FLASH. See Section 4.5.11.4, “FLASH and EEPROM Protection Register (FPROT and NVPROT)”.
Chapter 4 Memory FOPT register in high-page register space. A user engages security by programming the NVOPT location, which can be performed at the same time the FLASH memory is programmed. The 1:0 state disengages security; the other three combinations engage security. Notice the erased state (1:1) makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC0 bit to 0 in NVOPT so SEC = 1:0.
Chapter 4 Memory 4.5.10 EEPROM Mapping Only half of the EEPROM is in the memory map. The EPGSEL bit in FCNFG register selects which half of the array can be accessed in foreground while the other half can not be accessed in background. There are two mapping mode options that can be selected to configure the 8-byte EEPROM sectors: 4-byte mode and 8-byte mode. Each mode is selected by the EPGMOD bit in the FOPT register.
Chapter 4 Memory Table 4-6. FCDIV Register Field Descriptions Field Description 7 DIVLD Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless of the data written. 0 FCDIV has not been written since reset; erase and program operations disabled for FLASH and EEPROM.
Chapter 4 Memory 4.5.11.2 FLASH and EEPROM Options Register (FOPT and NVOPT) During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into FOPT. To change the value in this register, erase and reprogram the NVOPT location in FLASH memory as usual and then issue a new MCU reset. R 7 6 5 4 3 2 KEYEN FNORED EPGMOD 0 0 0 F F F 0 0 0 1 0 SEC W Reset F F = Unimplemented or Reserved Figure 4-6. FLASH and EEPROM Options Register (FOPT) Table 4-8.
Chapter 4 Memory 4.5.11.3 FLASH and EEPROM Configuration Register (FCNFG) 7 R 6 5 EPGSEL KEYACC 0 0 0 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 4-7. FLASH and EEPROM Configuration Register (FCNFG) Table 4-10. FCNFG Register Field Descriptions Field Description 6 EPGSEL EEPROM Page Select — This bit selects which EEPROM page is accessed in the memory map. 0 Page 0 is in foreground of memory map. Page 1 is in background and can not be accessed.
Chapter 4 Memory 4.5.11.4 FLASH and EEPROM Protection Register (FPROT and NVPROT) FPROT register defines which FLASH and EEPROM sectors are protected against program and erase operations. During the reset sequence, the FPROT register is loaded from the nonvolatile location NVPROT. To change the protection that will be loaded during the reset sequence, the sector containing NVPROT must be unprotected and erased, then NVPROT can be reprogrammed.
Chapter 4 Memory Table 4-13. FLASH Block Protection Address Area Protected Memory Size Protected (bytes) Number of Sectors Protected 0x1F N/A 0 0 0x1E 0xFC00–0xFFFF 1K 2 0x1D 0xF800–0xFFFF 2K 4 0x1C 0xF400–0xFFFF 3K 6 0x1B 0xF000–0xFFFF 4K 8 0x1A 0xEC00–0xFFFF 5K 10 0x19 0xE800–0xFFFF 6K 12 0x18 0xE400–0xFFFF 7K 14 0xE000–0xFFFF 8K 16 ... ... ...
Chapter 4 Memory 4.5.11.5 FLASH and EEPROM Status Register (FSTAT) 7 6 R 5 4 FPVIOL FACCERR 0 0 FCCF FCBEF 3 2 1 0 0 FBLANK 0 0 0 0 0 0 W Reset 1 1 = Unimplemented or Reserved Figure 4-9. FLASH and EEPROM Status Register (FSTAT) Table 4-14. FSTAT Register Field Descriptions Field Description 7 FCBEF Command Buffer Empty Flag — The FCBEF bit is used to launch commands.
Chapter 4 Memory 4.5.11.6 FLASH and EEPROM Command Register (FCMD) Only six command codes are recognized in normal user modes as shown in Table 4-15. All other command codes are illegal and generate an access error. Refer to Section 4.5.3, “Program and Erase Command Execution,” for a detailed discussion of FLASH and EEPROM programming and erase operations. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset FCMD 0 0 0 0 = Unimplemented or Reserved Figure 4-10.
Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt in the MC9S08EL32 Series and MC9S08SL16 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and General System Control 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically.
Chapter 5 Resets, Interrupts, and General System Control The COP counter is initialized by the first writes to the SOPT1 and SOPT2 registers after any system reset. Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application will use the reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings.
Chapter 5 Resets, Interrupts, and General System Control recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are difficult to debug. The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the stack.
Chapter 5 Resets, Interrupts, and General System Control The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current ISR. 5.5.2 Interrupt Vectors, Sources, and Local Masks Table 5-2 provides a summary of all interrupt sources.
Chapter 5 Resets, Interrupts, and General System Control Table 5-2. Vector Summary Vector Priority Lowest Highest 5.
Chapter 5 Resets, Interrupts, and General System Control for warning and detection. The LVD circuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon entering any of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter stop2, and the current consumption in stop3 with the LVD enabled will be higher. 5.6.
Chapter 5 Resets, Interrupts, and General System Control 5.7 Reset, Interrupt, and System Control Registers and Control Bits One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. Refer to Table 4-2 and Table 4-3 in Chapter 4, “Memory,” of this data sheet for the absolute address assignments for all registers. This section refers to registers and control bits only by their names.
Chapter 5 Resets, Interrupts, and General System Control 5.7.1 System Reset Status Register (SRS) This high page register includes read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address causes a COP reset when the COP is enabled except the values 0x55 and 0xAA.
Chapter 5 Resets, Interrupts, and General System Control Table 5-3. SRS Register Field Descriptions Field Description 3 ILAD Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented memory address. 0 Reset not caused by an illegal address 1 Reset caused by an illegal address 1 LVD Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR.
Chapter 5 Resets, Interrupts, and General System Control 5.7.3 System Options Register 1 (SOPT1) This high page register is a write-once register so only the first write after reset is honored. It can be read at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings.
Chapter 5 Resets, Interrupts, and General System Control 5.7.4 System Options Register 2 (SOPT2) This high page register contains bits to configure MCU specific features on the MC9S08EL32 Series and MC9S08SL16 Series devices. R 7 6 5 COPCLKS1 COPW1 0 0 0 4 3 2 1 0 ACIC1 T2CH1PS1 T2CH0PS1 T1CH1PS1 T1CH0PS1 0 0 0 0 0 W Reset: 0 = Unimplemented or Reserved Figure 5-5. System Options Register 2 (SOPT2) 1 This bit can be written only one time after reset.
Chapter 5 Resets, Interrupts, and General System Control 5.7.5 System Device Identification Register (SDIDH, SDIDL) These high page read-only registers are included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU.
Chapter 5 Resets, Interrupts, and General System Control 5.7.6 System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the ADC module.
Chapter 5 Resets, Interrupts, and General System Control 5.7.7 System Power Management Status and Control 2 Register (SPMSC2) This register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the MCU.
Chapter 5 Resets, Interrupts, and General System Control MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08EL32 has three parallel I/O ports which include a total of 22 I/O pins. See Chapter 2, “Pins and Connections,” for more information about pin assignments and external hardware considerations of these pins. Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or keyboard interrupts as shown in Table 2-1.
Chapter 6 Parallel Input/Output Control It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. PTxDDn D Output Enable Q PTxDn D Q Output Data 1 Port Read Data 0 Synchronizer Input Data BUSCLK Figure 6-1. Parallel I/O Block Diagram 6.
Chapter 6 Parallel Input/Output Control 6.3 Pin Interrupts Port A[3:0], port B[3:0] and port C pins can be configured as external interrupt inputs and as an external mean of waking the MCU from stop3 or wait low-power modes. The block diagram for each port interrupt logic is shown Figure 6-2. BUSCLK PTxACK VDD 1 PIxn 0 S RESET PTxIF D CLR Q PTxPS0 SYNCHRONIZER CK PTxS0 PORT INTERRUPT FF 1 PIxn 0 S STOP STOP BYPASS PTx INTERRUPT REQUEST PTxMOD PTxPSn PTxIE PTxESn Figure 6-2.
Chapter 6 Parallel Input/Output Control 6.3.3 Pull-up/Pull-down Resistors The port interrupt pins can be configured to use an internal pull-up/pull-down resistor using the associated I/O port pull enable register. If an internal resistor is enabled (PTxPEn=1) and the pin is selected for interrupt (PTxPSn=1), the PTxES register is used to select whether the resistor is a pull-up (PTxESn = 0) or a pull-down (PTxESn = 1). 6.3.
Chapter 6 Parallel Input/Output Control 6.5.1 Port A Registers Port A is controlled by the registers listed below. 6.5.1.1 Port A Data Register (PTAD) 7 6 PTAD7 PTAD6 0 0 R 5 4 0 0 3 2 1 0 PTAD3 PTAD2 PTAD1 PTAD0 0 0 0 0 W Reset: 0 0 Figure 6-3. Port A Data Register (PTAD) Table 6-1. PTAD Register Field Descriptions Field Description 7:6 PTAD[7:6] Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.1.3 Port A Pull Enable Register (PTAPE) 7 6 PTAPE7 PTAPE6 0 0 R 5 4 0 0 3 2 1 0 PTAPE3 PTAPE2 PTAPE1 PTAPE0 0 0 0 0 W Reset: 0 0 Figure 6-5. Internal Pull Enable for Port A Register (PTAPE) Table 6-3.
Chapter 6 Parallel Input/Output Control 6.5.1.5 Port A Drive Strength Selection Register (PTADS) 7 6 PTADS7 PTADS6 0 0 R 5 4 0 0 3 2 1 0 PTADS3 PTADS2 PTADS1 PTADS0 0 0 0 0 W Reset: 0 0 Figure 6-7. Drive Strength Selection for Port A Register (PTADS) Table 6-5. PTADS Register Field Descriptions Field Description 7:6 Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high PTADS[7:6] output drive for the associated PTA pin.
Chapter 6 Parallel Input/Output Control 6.5.1.7 R Port A Interrupt Pin Select Register (PTAPS) 7 6 5 4 0 0 0 0 3 2 1 0 PTAPS3 PTAPS2 PTAPS1 PTAPS0 0 0 0 0 W Reset: 0 0 0 0 Figure 6-9. Port A Interrupt Pin Select Register (PTAPS) Table 6-7. PTAPS Register Field Descriptions Field Description 3:0 Port A Interrupt Pin Selects — Each of the PTAPSn bits enable the corresponding port A interrupt pin. PTAPS[3:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. 6.5.1.
Chapter 6 Parallel Input/Output Control 6.5.2 Port B Registers Port B is controlled by the registers listed below. 6.5.2.1 Port B Data Register (PTBD) 7 6 5 4 3 2 1 0 PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-11. Port B Data Register (PTBD) Table 6-9. PTBD Register Field Descriptions Field Description 7:0 PTBD[7:0] Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.2.3 Port B Pull Enable Register (PTBPE) 7 6 5 4 3 2 1 0 PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-13. Internal Pull Enable for Port B Register (PTBPE) Table 6-11.
Chapter 6 Parallel Input/Output Control 6.5.2.5 Port B Drive Strength Selection Register (PTBDS) 7 6 5 4 3 2 1 0 PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-15. Drive Strength Selection for Port B Register (PTBDS) Table 6-13.
Chapter 6 Parallel Input/Output Control 6.5.2.7 R Port B Interrupt Pin Select Register (PTBPS) 7 6 5 4 0 0 0 0 3 2 1 0 PTBPS3 PTBPS2 PTBPS1 PTBPS0 0 0 0 0 W Reset: 0 0 0 0 Figure 6-17. Port B Interrupt Pin Select Register (PTBPS) Table 6-15. PTBPS Register Field Descriptions Field Description 3:0 Port B Interrupt Pin Selects — Each of the PTBPSn bits enable the corresponding port B interrupt pin. PTBPS[3:0] 0 Pin not enabled as interrupt. 1 Pin enabled as interrupt. 6.5.2.
Chapter 6 Parallel Input/Output Control 6.5.3 Port C Registers Port C is controlled by the registers listed below. 6.5.3.1 Port C Data Register (PTCD) 7 6 5 4 3 2 1 0 PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-19. Port C Data Register (PTCD) Table 6-17. PTCD Register Field Descriptions Field Description 7:0 PTCD[7:0] Port C Data Register Bits — For port C pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output Control 6.5.3.3 Port C Pull Enable Register (PTCPE) 7 6 5 4 3 2 1 0 PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-21. Internal Pull Enable for Port C Register (PTCPE) Table 6-19.
Chapter 6 Parallel Input/Output Control 6.5.3.5 Port C Drive Strength Selection Register (PTCDS) 7 6 5 4 3 2 1 0 PTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-23. Drive Strength Selection for Port C Register (PTCDS) Table 6-21.
Chapter 6 Parallel Input/Output Control 6.5.3.7 Port C Interrupt Pin Select Register (PTCPS) 7 6 5 4 3 2 1 0 PTCPS7 PTCPS6 PTCPS5 PTCPS4 PTCPS3 PTCPS2 PTCPS1 PTCPS0 0 0 0 0 0 0 0 0 R W Reset: Figure 6-25. Port C Interrupt Pin Select Register (PTCPS) Table 6-23. PTCPS Register Field Descriptions Field Description 7:0 Port C Interrupt Pin Selects — Each of the PTCPSn bits enable the corresponding port C interrupt pin. PTCPS[7:0] 0 Pin not enabled as interrupt.
Chapter 7 Central Processor Unit (S08CPUV3) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Chapter 7 Central Processor Unit (S08CPUV3) 7.2 Programmer’s Model and CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. 0 7 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 0 SP STACK POINTER 15 X 0 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers 7.2.
Chapter 7 Central Processor Unit (S08CPUV3) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
Chapter 7 Central Processor Unit (S08CPUV3) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
Chapter 7 Central Processor Unit (S08CPUV3) 7.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
Chapter 7 Central Processor Unit (S08CPUV3) 7.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 7.3.6.
Chapter 7 Central Processor Unit (S08CPUV3) 7.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
Chapter 7 Central Processor Unit (S08CPUV3) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence.
Chapter 7 Central Processor Unit (S08CPUV3) 7.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.
Chapter 7 Central Processor Unit (S08CPUV3) ASL opr8a ASLA ASLX ASL oprx8,X ASL ,X ASL oprx8,SP Operation Arithmetic Shift Left Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) Operation Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) Operation Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) Divide A ← (H:A)÷(X); H ← Remainder DIV EOR EOR EOR EOR EOR EOR EOR EOR Operation #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP Exclusive OR Memory with Accumulator A ← (A ⊕ M) Increment M ← (M) + $01 A ← (A) + $01 X ← (X) + $01 M ← (M) + $01 M ← (M) + $01 M ← (M) + $01 Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) LSL opr8a LSLA LSLX LSL oprx8,X LSL ,X LSL oprx8,SP LSR opr8a LSRA LSRX LSR oprx8,X LSR ,X LSR oprx8,SP Operation Logical Shift Left C 0 b7 b0 (Same as ASL) Logical Shift Right 0 C b7 b0 Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) Operation ROL opr8a ROLA ROLX ROL oprx8,X ROL ,X ROL oprx8,SP Rotate Left through Carry ROR opr8a RORA RORX ROR oprx8,X ROR ,X ROR oprx8,SP Rotate Right through Carry C b7 b0 C b7 b0 Object Code Cycles Source Form Address Mode Table 7-2.
Chapter 7 Central Processor Unit (S08CPUV3) STX STX STX STX STX STX STX opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP SUB SUB SUB SUB SUB SUB SUB SUB #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Operation Object Code DIR EXT IX2 IX1 IX SP2 SP1 BF CF DF EF FF 9E DF 9E EF dd hh ll ee ff ff IMM DIR EXT IX2 IX1 IX SP2 SP1 A0 B0 C0 D0 E0 F0 9E D0 9E E0 ii dd hh ll ee ff ff SWI Software Interrupt PC ← (PC) + $0001 Push (PCL); SP ← (SP) – $0001 Push (PCH); SP ← (SP) – $0001 Push (
Chapter 7 Central Processor Unit (S08CPUV3) Operation Object Code Cycles Source Form Address Mode Table 7-2. Instruction Set Summary (Sheet 9 of 9) Affect on CCR Cyc-by-Cyc Details V11H INZC TXS Transfer Index Reg. to SP SP ← (H:X) – $0001 INH 94 2 fp – 1 1 – – – – – WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Halt CPU INH 8F 2+ fp...
Chapter 7 Central Processor Unit (S08CPUV3) Table 7-3.
Chapter 7 Central Processor Unit (S08CPUV3) Table 7-3.
Chapter 7 Central Processor Unit (S08CPUV3) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 8 Internal Clock Source (S08ICSV2) 8.1 Introduction The internal clock source (ICS) module provides clock source choices for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by either an internal or an external reference clock. The module can provide this FLL clock or either of the internal or external reference clocks as a source for the MCU system clock.
Chapter 8 Internal Clock Source (S08ICSV2) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP INT SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE
Internal Clock Source (S08ICSV2) 8.1.2 Features Key features of the ICS module follow. For device specific information, refer to the ICS Characteristics in the Electricals section of the documentation. • Frequency-locked loop (FLL) is trimmable for accuracy — 0.
Internal Clock Source (S08ICSV2) Optional External Reference Clock Source Block RANGE HGO EREFS ERCLKEN EREFSTEN IRCLKEN IREFSTEN ICSERCLK ICSIRCLK CLKS BDIV / 2n Internal Reference Clock 9 IREFS ICSOUT n=0-3 LP DCO DCOOUT /2 ICSLCLK TRIM ICSFFCLK 9 / 2n RDIV_CLK Filter n=0-7 FLL RDIV Internal Clock Source Block Figure 8-2. Internal Clock Source (ICS) Block Diagram 8.1.
Internal Clock Source (S08ICSV2) FLL Bypassed Internal Low Power (FBILP) 8.1.4.4 In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock. The BDC clock is not available. FLL Bypassed External (FBE) 8.1.4.5 In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is bypassed. The ICS supplies a clock derived from the external reference clock.
Internal Clock Source (S08ICSV2) 8.3.1 ICS Control Register 1 (ICSC1) 7 6 5 4 3 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 R CLKS RDIV W Reset: 0 0 0 0 0 Figure 8-3. ICS Control Register 1 (ICSC1) Table 8-2. ICS Control Register 1 Field Descriptions Field Description 7:6 CLKS Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency depends on the value of the BDIV bits. 00 Output of FLL is selected. 01 Internal reference clock is selected.
Internal Clock Source (S08ICSV2) 8.3.2 ICS Control Register 2 (ICSC2) 7 6 5 4 3 2 RANGE HGO LP EREFS 0 0 0 0 1 0 R BDIV ERCLKEN EREFSTEN W Reset: 0 1 0 0 Figure 8-4. ICS Control Register 2 (ICSC2) Table 8-3. ICS Control Register 2 Field Descriptions Field Description 7:6 BDIV Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This controls the bus frequency.
Internal Clock Source (S08ICSV2) 8.3.3 ICS Trim Register (ICSTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U U U U U U Figure 8-5. ICS Trim Register (ICSTRM) Table 8-4. ICS Trim Register Field Descriptions Field Description 7:0 TRIM ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Internal Clock Source (S08ICSV2) Table 8-5. ICS Status and Control Register Field Descriptions (continued) Field Description 1 OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE, or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
Internal Clock Source (S08ICSV2) • • • CLKS bits are written to 00 IREFS bit is written to 1 RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to 39.0625 kHz. In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by the internal reference clock. The FLL loop will lock the frequency to 1024 times the reference frequency, as selected by the RDIV bits.
Internal Clock Source (S08ICSV2) 8.4.1.5 FLL Bypassed External (FBE) The FLL bypassed external (FBE) mode is entered when all the following conditions occur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is active or LP bit is written to 0. In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock.
Internal Clock Source (S08ICSV2) The CLKS bits can also be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. The actual switch to the newly selected clock will not occur until after a few full cycles of the new clock. If the newly selected clock is not available, the previous clock will remain selected. 8.4.
Internal Clock Source (S08ICSV2) If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. 8.4.7 Fixed Frequency Clock The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for peripheral modules.
Internal Clock Source (S08ICSV2) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 9 5-V Analog Comparator (S08ACMPV2) 9.1 Introduction The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). All MC9S08EL32 Series and MC9S08SL16 Series MCUs contain at least one ACMP. MC9S08EL32 and MC9S08EL16 contain two ACMPs in the 28-pin package. See Table 9-1.
Chapter 9 5-V Analog Comparator (S08ACMPV2) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE MODU
Analog Comparator (S08ACMPV2) 9.1.3 Features The ACMP has the following features: • Full rail to rail supply operation. • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. • Option to compare to fixed internal bandgap reference voltage. • Option to allow comparator output to be visible on a pin, ACMPxO. • Can operate in stop3 mode 9.1.4 Modes of Operation This section defines the ACMP operation in wait, stop and background debug modes. 9.1.4.
Analog Comparator (S08ACMPV2) 9.1.5 Block Diagram The block diagram for the Analog Comparator module is shown Figure 9-2. Internal Bus Internal Reference ACIE ACBGS ACME ACMPx INTERRUPT REQUEST Status & Control Register ACF ACMPx+ + - ACMPx- set ACF ACMOD ACOPE Interrupt Control Comparator ACMPxO Figure 9-2. Analog Comparator 5V (ACMP5) Block Diagram MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Analog Comparator (S08ACMPV2) 9.2 External Signal Description The ACMP has two analog input pins, ACMPx+ and ACMPx- and one digital output pin ACMPxO. Each of these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As shown in Figure 9-2, the ACMPx- pin is connected to the inverting input of the comparator, and the ACMPx+ pin is connected to the comparator non-inverting input if ACBGS is a 0.
Analog Comparator (S08ACMPV2) 9.3.1.1 ACMPx Status and Control Register (ACMPxSC) ACMPxSC contains the status flag and control bits which are used to enable and configure the ACMP. 7 6 5 4 3 ACME ACBGS ACF ACIE 0 0 0 0 R 2 1 0 ACO ACOPE ACMOD W Reset: 0 0 0 0 = Unimplemented Figure 9-3. ACMPx Status and Control Register Table 9-3. ACMPx Status and Control Register Field Descriptions Field 7 ACME Description Analog Comparator Module Enable — ACME enables the ACMP module.
Analog Comparator (S08ACMPV2) 9.4 Functional Description The analog comparator can be used to compare two analog input voltages applied to ACMPx+ and ACMPx-; or it can be used to compare an analog input voltage applied to ACMPx- with an internal bandgap reference voltage. ACBGS is used to select between the bandgap reference voltage or the ACMPx+ pin as the input to the non-inverting input of the analog comparator.
Analog Comparator (S08ACMPV2) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 10 Analog-to-Digital Converter (S08ADCV1) 10.1 Introduction The 10-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE MC9S08EL32 Series and MC9S08SL16 Series devices operates at a higher voltage range (2.7 V to 5.5 V) and does not include stop1 mode.
Chapter 10 Analog-to-Digital Converter (S08ADCV1) 10.1.2 Alternate Clock The ADC module is capable of performing conversions using the MCU bus clock, the bus clock divided by two, the local asynchronous clock (ADACK) within the module, or the alternate clock, ALTCLK. The alternate clock for the MC9S08EL32 Series and MC9S08SL16 Series MCU devices is the external reference clock (ICSERCLK).
Chapter 10 Analog-to-Digital Converter (S08ADCV1) Figure 10-1 shows the MC9S08EL32 with the ADC module highlighted.
Chapter 10 Analog-to-Digital Converter (S08ADCV1) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Analog-to-Digital Converter (S08ADC10V1) 10.1.5 Features Features of the ADC module include: • Linear successive approximation algorithm with 10 bits resolution. • Up to 28 analog inputs. • Output formatted in 10- or 8-bit right-justified format. • Single or continuous conversion (automatic return to idle after single conversion). • Configurable sample time and conversion speed/power. • Conversion complete flag and interrupt. • Input clock selectable from up to four sources.
Analog-to-Digital Converter (S08ADC10V1) ADIV ADLPC MODE ADLSMP ADTRG 2 ADCO ADCH 1 ADCCFG complete COCO ADCSC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK ÷2 ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 COCO 2 ADVIN Interrupt SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 Compare Value Registers ACFGT Value Compare Logic ADCSC2 Figure 10-2.
Analog-to-Digital Converter (S08ADC10V1) 10.2.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 10.2.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
Analog-to-Digital Converter (S08ADC10V1) 7 R 6 5 4 AIEN ADCO 0 0 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 = Unimplemented or Reserved Figure 10-3. Status and Control Register (ADCSC1) Table 10-3. ADCSC1 Register Field Descriptions Field Description 7 COCO Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (ACFE = 0).
Analog-to-Digital Converter (S08ADC10V1) Figure 10-4. Input Channel Select (continued) 10.3.
Analog-to-Digital Converter (S08ADC10V1) Table 10-4. ADCSC2 Register Field Descriptions (continued) Field Description 5 ACFE Compare Function Enable — ACFE is used to enable the compare function. 0 Compare function disabled 1 Compare function enabled 4 ACFGT Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value.
Analog-to-Digital Converter (S08ADC10V1) R 7 6 5 4 3 2 1 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented or Reserved Figure 10-7. Data Result Low Register (ADCRL) 10.3.5 Compare Value High Register (ADCCVH) This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled.
Analog-to-Digital Converter (S08ADC10V1) 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 0 0 0 0 0 0 0 0 Figure 10-10. Configuration Register (ADCCFG) Table 10-5. ADCCFG Register Field Descriptions Field Description 7 ADLPC Low Power Configuration — ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required.
Analog-to-Digital Converter (S08ADC10V1) Table 10-8. Input Clock Select ADICLK 00 10.3.8 Selected Clock Source Bus clock 01 Bus clock divided by 2 10 Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK) Pin Control 1 Register (APCTL1) The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0–7 of the ADC module.
Analog-to-Digital Converter (S08ADC10V1) Table 10-9. APCTL1 Register Field Descriptions (continued) Field Description 1 ADPC1 ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1. 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled 0 ADPC0 ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0. 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 10.3.
Analog-to-Digital Converter (S08ADC10V1) Table 10-10. APCTL2 Register Field Descriptions (continued) Field Description 1 ADPC9 ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9. 0 AD9 pin I/O control enabled 1 AD9 pin I/O control disabled 0 ADPC8 ADC Pin Control 8 — ADPC8 is used to control the pin associated with channel AD8. 0 AD8 pin I/O control enabled 1 AD8 pin I/O control disabled 10.3.
Analog-to-Digital Converter (S08ADC10V1) Table 10-11. APCTL3 Register Field Descriptions (continued) Field Description 1 ADPC17 ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17. 0 AD17 pin I/O control enabled 1 AD17 pin I/O control disabled 0 ADPC16 ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16. 0 AD16 pin I/O control enabled 1 AD16 pin I/O control disabled 10.
Analog-to-Digital Converter (S08ADC10V1) are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1, 2, 4, or 8. 10.4.2 Input Select and Pin Control The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the pins used as analog inputs.
Analog-to-Digital Converter (S08ADC10V1) 10.4.4.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high at the time that COCO is set.
Analog-to-Digital Converter (S08ADC10V1) result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm. If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (ADLSMP=1).
Analog-to-Digital Converter (S08ADC10V1) 10.4.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set.
Analog-to-Digital Converter (S08ADC10V1) 10.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion.
Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 10.5.1.
Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? NO YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE Figure 10-14. Initialization Flowchart for Example 10.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 10.6.
Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 10.6.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs.
Analog-to-Digital Converter (S08ADC10V1) 10.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 10.6.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.
Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 10.6.2.
Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around ±1/2 LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 10.6.2.3 will reduce this error.
Analog-to-Digital Converter (S08ADC10V1) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 11 Inter-Integrated Circuit (S08IICV2) 11.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
Chapter 11 Inter-Integrated Circuit (S08IICV2) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE M
Inter-Integrated Circuit (S08IICV2) 11.1.
Inter-Integrated Circuit (S08IICV2) 11.1.4 Block Diagram Figure 11-2 is a block diagram of the IIC. Address Data Bus Interrupt ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync Start Stop Arbitration Control Clock Control In/Out Data Shift Register Address Compare SCL SDA Figure 11-2. IIC Functional Block Diagram 11.2 External Signal Description This section describes each user-accessible pin signal. 11.2.
Inter-Integrated Circuit (S08IICV2) Refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.
Inter-Integrated Circuit (S08IICV2) Table 11-3. IICF Field Descriptions Field 7–6 MULT 5–0 ICR Description IIC Multiplier Factor. The MULT bits define the multiplier factor, mul. This factor, along with the SCL divider, generates the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved IIC Clock Rate. The ICR bits are used to prescale the bus clock for bit rate selection.
Inter-Integrated Circuit (S08IICV2) Table 11-5.
Inter-Integrated Circuit (S08IICV2) 11.3.3 IIC Control Register (IICC1) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-5. IIC Control Register (IICC1) Table 11-6. IICC1 Field Descriptions Field Description 7 IICEN IIC Enable. The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled 1 IIC is enabled 6 IICIE IIC Interrupt Enable.
Inter-Integrated Circuit (S08IICV2) Table 11-7. IICS Field Descriptions Field Description 7 TCF Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the IICD register in receive mode or writing to the IICD in transmit mode. 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed as a Slave.
Inter-Integrated Circuit (S08IICV2) Table 11-8. IICD Field Descriptions Field Description 7–0 DATA Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Inter-Integrated Circuit (S08IICV2) 11.4 Functional Description This section provides a complete functional description of the IIC module. 11.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
Inter-Integrated Circuit (S08IICV2) 11.4.1.2 Slave Address Transmission The first byte of data transferred immediately after the start signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave.
Inter-Integrated Circuit (S08IICV2) 11.4.1.5 Repeated Start Signal As shown in Figure 11-9, a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 11.4.1.6 Arbitration Procedure The IIC bus is a true multi-master bus that allows more than one master to be connected on it.
Inter-Integrated Circuit (S08IICV2) 11.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such a case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 11.4.1.9 Clock Stretching The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer.
Inter-Integrated Circuit (S08IICV2) After a repeated start condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does not match.
Inter-Integrated Circuit (S08IICV2) 11.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 11.6.3 Arbitration Lost Interrupt The IIC is a true multi-master bus that allows more than one master to be connected on it.
Inter-Integrated Circuit (S08IICV2) 11.7 Initialization/Application Information Module Initialization (Slave) 1. Write: IICC2 — to enable or disable general call — to select 10-bit or 7-bit addressing mode 2. Write: IICA — to set the slave address 3. Write: IICC1 — to enable IIC and interrupts 4. Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data 5. Initialize RAM variables used to achieve the routine shown in Figure 11-12 Module Initialization (Master) 1.
Inter-Integrated Circuit (S08IICV2) Clear IICIF Master Mode ? Y TX N Arbitration Lost ? Y RX Tx/Rx ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y Address Transfer See Note 1 Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 Generate Stop Signal (MST = 0) TX Y Set TX Mode RX TX/RX ? N (Write) N N Data Transfer See Note 2 ACK from Receiver ?
Chapter 12 Slave LIN Interface Controller (S08SLICV1) 12.1 Introduction The slave LIN interface controller (SLIC) is designed to provide slave node connectivity on a local interconnect network (LIN) sub-bus. LIN is an open-standard serial protocol developed for the automotive industry to connect sensors, motors, and actuators. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 12 Slave LIN Interface Controller (S08SLICV1) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTE
12.1.
12.1.2 Modes of Operation Figure 12-2 shows the modes in which the SLIC will operate.
will clear INITACK after the module has left reset mode and the SLIC will seek the next LIN header. It is the responsibility of the user to verify that this operation is compatible with the application before implementing this feature. In this mode, the internal SLIC module voltage references are operative, VDD is supplied to the internal circuits, which are held in their reset state and the internal SLIC module system clock is running. Registers will assume their reset condition.
entering SLIC stop mode, any activity on the network will cause the SLIC module to exit SLIC stop mode and generate an unmaskable interrupt of the CPU. This wakeup interrupt state is reflected in the SLCSV, encoded as the highest priority interrupt. This interrupt can be cleared by the CPU with a read of the SLCSV and clearing of the SLCF interrupt flag.
12.1.3 Block Diagram STATUS REGISTERS SLCSV AND SLCF SLCSV REGISTER CONTROL CONTROL REGISTERS LIN PROTOCOL STATE MACHINE (PSM) MESSAGE BUFFER — 9 BYTES SLCID SLCD7, SLCD6, SLCD5, SLCD4 SLCD3, SLCD2, SLCD1, SLCD0 SHADOW REGISTER 1 BYTE SLIC CLOCK BUS CLOCK DIGITAL RX FILTER PRESCALER (RXFP) DIGITAL RX FILTER SLCTx SLCRx Figure 12-3. SLIC Module Block Diagram 12.2 12.2.1 External Signal Description SLCTx — SLIC Transmit Pin The SLCTx pin serves as the serial output of the SLIC module. 12.2.
R 7 6 0 0 5 4 3 2 1 0 INITREQ BEDD WAKETX TXABRT IMSG SLCIE 1 0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 12-4. SLIC Control Register 1 (SLCC1) Table 12-1. SLCC1 Field Descriptions Field Description 5 INITREQ Initialization Request — Requesting initialization mode by setting this bit will place the SLIC module into its initialized state immediately. As a result of setting INITREQ, INITACK will be set in SLCS.
Table 12-1. SLCC1 Field Descriptions (continued) Field Description 2 TXABRT Transmit Abort Message 0 Normal operation 1 Transmitter aborts current transmission at next byte boundary; TXABRT resets to 0 after the transmission is successfully aborted TXABRT also resets to 0 upon detection of a bit error. 1 IMSG SLIC Ignore Message Bit — IMSG cannot be cleared by a write of 0, but is cleared automatically by the SLIC module after the next BREAK/SYNC symbol pair is validated.
Table 12-2. SLCC2 Field Descriptions Field 6:4 RXFP 1 Description Receive Filter Prescaler — These bits configure the effective filter width for the digital receive filter circuit. The RXFP bits control the maximum number of SLIC clock counts required for the filter to change state, which determines the total maximum filter delay. Any pulse which is smaller than the maximum filter delay value will be rejected by the filter and ignored as noise.
Table 12-3. Digital Receive Filter Clock Prescaler Max Filter Delay (in μs) RXFP[2:0] Digital RX Filter Clock Prescaler (Divide by) Filter Input Clock (SLIC clock in MHz) 2 4 6 8 10 12 14 16 18 20 000 1 8.00 4.00 2.67 2.00 1.60 1.33 1.14 1.00 0.89 0.80 001 2 16.00 8.00 5.33 4.00 3.20 2.67 2.29 2.00 1.78 1.60 010 3 24.00 12.00 8.00 6.00 4.80 4.00 3.43 3.00 2.67 2.40 011 4 32.00 16.00 10.67 8.00 6.40 5.33 4.57 4.00 3.56 3.20 100 5 40.00 20.00 13.
7 R 6 5 4 3 2 1 0 BT14 BT13 BT12 BT11 BT10 BT9 BT8 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved1 Figure 12-6. SLIC Bit Time Register High (SLCBTH) 1 Do not write to unimplemented bits as unexpected operation may occur. Table 12-4. SLCBTH Field Descriptions Field Description 6:0 BT[14:8] Bit Time Value — BT displays the number of SLIC clocks that equals one bit time in LIN mode (BTM = 0).
R 7 6 5 4 3 2 1 SLCACT 0 INITACK 0 0 0 0 0 SLCF W Reset 0 0 1 0 0 0 0 0 = Unimplemented or Reserved Figure 12-8. SLIC Status Register (SLCS) Table 12-6. SLCS Field Descriptions 1 Field Description 7 SLCACT1 SLIC Active (Oscillator Trim Blocking Semaphore) — SLCACT is used to indicate if it is safe to trim the oscillator based upon current SLIC activity in LIN mode.
R 7 6 5 4 3 2 1 0 0 0 I3 I2 I1 I0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-9. SLIC State Vector Register (SLCSV) Table 12-7. SLCSV Field Descriptions Field 5:2 I[3:0] Description Interrupt State Vector — These bits indicate the source of the interrupt request that is currently pending. READ: any time WRITE: ignored 12.3.5.
• • • • • • • • • No Interrupts Pending This value indicates that all pending interrupt sources have been serviced. In polling mode, the SLCSV is read and interrupts serviced until this value reads back 0. This source will not generate an interrupt of the CPU, regardless of state of SLCIE.
• method was employed for this message frame. Refer to the LIN specification for more details on the calculations. Byte Framing Error This error comes from the standard UART definition for byte encoding and occurs when the STOP bit is sampled and reads back as a 090. STOP should always read as 1. NOTE A byte framing error can also be an indication that the number of data bytes received in a LIN message frame does not match the value written to the SLCDLC register. See Section 12.6.
Table 12-9. Interrupt Sources Summary (BTM = 1) • • • • • • • • SLCSV I3 I2 I1 I0 Interrupt Source Priority 0x28 1 0 1 0 Byte Framing Error 10 0x38 1 1 1 0 Reserved 14 0x3C 1 1 1 1 Wakeup 15 (Highest) No Interrupts Pending This value indicates that all pending interrupt sources have been serviced. In polling mode, the SLCSV is read and interrupts serviced until this value reads back 0. This source will not generate an interrupt of the CPU, regardless of state of SLCIE.
12.3.6 SLIC Data Length Code Register (SLCDLC) The SLIC data length code register (SLCDLC) is the primary functional control register for the SLIC module during normal LIN operations. It contains the data length code of the message buffer, indicating how many bytes of data are to be sent or received, as well as the checksum mode control and transmit enabling bit. 7 6 5 4 3 2 1 0 TXGO CHKMOD DLC5 DLC4 DLC3 DLC2 DLC1 DLC0 0 0 0 0 0 0 0 0 R W Reset Figure 12-10.
12.3.7 SLIC Identifier and Data Registers (SLCID, SLCD7-SLCD0) The SLIC identifier (SLCID) and eight data registers (SLCD7–SLCD0) comprise the transmit and receive buffer and are used to read/write the identifier and message buffer 8 data bytes. In BTM mode (BTM = 1), only SLCID is used to send and receive bytes, as only one byte is handled at any one time. The number of bytes to be read from or written to these registers is determined by the user software and written to SLCDLC.
7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 12-12. SLIC Data Register x (SLCD7–SLCD0) R — Read SLC Receive Data T — Write SLC Transmit Data 12.4 Functional Description The SLIC provides full standard LIN message buffering for a slave node, minimizing the need for CPU intervention.
HEADER DATA 0x55 SYNCH BREAK SYNCH BYTE IDENT FIELD DATA FIELD DATA FIELD DATA FIELD DATA FIELD DATA FIELD DATA FIELD DATA FIELD DATA FIELD 0 1 2 3 4 5 6 7 CHECKSUM FIELD 13 OR MORE BITS (LIN 1.3) Figure 12-13. Typical LIN MESSAGE FRAME 12.6.1 LIN Message Frame Header The HEADER section of all LIN messages is transmitted by the master node in the network and contains synchronization data, as well as the identifier to define what information is to be contained in the message frame.
12.6.3 LIN Checksum Field The checksum field is a data integrity measure for LIN message frames, used to signal errors in data consistency. The LIN 1.3 checksum calculation only covers the data field, but the SLIC module also supports an enhanced checksum calculation which also includes the identifier field. For more information on the checksum calculation, refer to Section 12.6.13, “LIN Data Integrity Checking Methods.” 12.6.
The SLIC clock is the same as the CPU bus clock. The module is designed to provide better than 1% bit rate accuracy at the lowest value of the SLIC clock frequency and the accuracy improves as the SLIC clock frequency is increased. For this reason, it is advantageous to choose the fastest SLIC clock which is still within the acceptable operating range of the SLIC.
2. When INITACK = 0, write SLCC2 with desired values for: a) SLCWCM — Wait clock mode. 3. Write SLCC2 to set up: a) RXFP — Digital receive filter clock prescaler. 4. Enable the SLIC module by writing SLCC2: a) SLCE = 1 to place SLIC module into run mode. b) BTM = 1 to enable byte transfer mode. 5. Write SLCBT value. 6. Write SLCC1 to enable SLIC interrupts (if desired).
LIN MESSAGE HEADER RECEIVED VALID BREAK AND SYNCH DATA? N INTERRUPT READ SLCSV Y SLIC UPDATES SLCBT ID ARRIVING IN RX BUFFER PROCESS ERROR CODE: BYTE FRAMING ERROR CLEAR SLCF INTERRUPT READ SLCSV ERROR CODE ? Y PROCESS ERROR CODE: IDENTIFIER-PARITY ERROR BYTE FRAMING ERROR CLEAR SLCF EXIT ISR RETURN TO LIN BUS IDLE N READ ID FROM SLCID CLEAR SLCF ID FOR THIS NODE ? N SET IMSG BIT Y PROCESS VALID ID Figure 12-14. Handling LIN Message Headers 12.6.7.
• The third section of the message frame header is the IDENTIFIER FIELD (ID). The identifier is covered more in Section 12.6.8, “Handling Command Message Frames,” and Section 12.6.9, “Handling Request LIN Message Frames.
For clarification, in this document, “command” messages will refer to any message frame where the SLIC module is receiving data bytes and “request” messages refer to message frames where the SLIC module will be expected to transmit data bytes. This is a generic description and should not be confused with the terminology in the LIN specification. The LIN use of the terms “command” and “request” have the same basic meaning, but are limited in scope to specific identifier values of 0x3C and 0x3D.
PROCESS VALID ID COMMAND MESSAGE ? N PROCESS REQUEST MESSAGE Y EXTENDED FRAME Y ? INITIALIZE SW BYTE COUNT WRITE SLCDLC FOR THIS ID 0nxx xxxx (TXGO = 0) (CHKMOD = n) N WRITE SLCDLC FOR THIS ID 0n00 0xxx (TXGO = 0) (CHKMOD = n) EXIT ISR INTERRUPT READ SLCSV PROCESS ERROR CODE: BYTE FRAMING ERROR NO-BUS-ACTIVITY RECEIVE BUFFER OVERRUN EXIT ISR ERROR CODE PROCESS ERROR CODE: BYTE FRAMING ERROR CHECKSUM-ERROR NO-BUS-ACTIVITY RECEIVE BUFFER OVERRUN INTERRUPT READ SLCSV Y CLEAR SLCF ? N Y ERROR
on the first data byte. Using CHKMOD in this way allows the SLIC to receive messages with either method of data consistency check and change on a frame-by-frame basis. If a system uses both types of data consistency checking methods, the software must simply change the setting of this bit based on the identifier of each message. If the network only uses one type of check, CHKMOD can be set as a constant value in the user’s code.
unmasked, after 8 bytes are received or an error is detected. At this interrupt, the SLCSV will indicate an error condition (in case of byte framing error, idle bus) or that the receive buffer is full. If the data is successfully received, the user must then empty the buffer by reading SLCD7-SLCD0 and then subtract 8 from the software byte count. When this software counter reaches 8 or fewer, the remaining data bytes will fit in the buffer and only one interrupt should occur.
This means an extra step is taken inside the interrupt service routine after the identifier has been decoded and is determined to be an ID for a request message frame. Figure 12-16 deals with request messages, where the SLIC will be transmitting data to the master node. If the received identifier corresponds to a standard LIN command frame (i.e., 1-8 data bytes), the message processing is very simple. The user must load the data to be transmitted into the transmit buffer by writing it to the SLCD registers.
PROCESS REQUEST MESSAGE EXTENDED FRAME Y ? N 1. CLEAR SLCF 2. LOAD DATA INTO MESSAGE BUFFER 3. WRITE SLCDLC FOR THIS ID 1n00 0xxx (TXGO = 1) (CHKMOD = n) 1. CLEAR SLCF 2. INITIALIZE SW BYTE COUNT 3. LOAD FIRST 8 DATA BYTES 4.
The SLIC module cannot begin to transmit the data until the user writes a 1 to TXGO, indicating that data is ready. If the user writes TXGO without loading data into the transmit buffer, whatever data is in storage will be transmitted, where the number of bytes transmitted is based on the data length value in the data length register.
NOTE Do not write the CHKMOD or data length values in SLCDLC more than one time per message frame. The SLIC tracks the number of sent or received bytes based on the value written to this register at the beginning of the data field and rewriting this register will corrupt the checksum calculation and cause unpredictable behavior in the SLIC module. The application software must track the number of sent or received bytes to know what the current byte count in the SLIC is.
12.6.11 Sleep and Wakeup Operation The SLIC module itself has no special sleep mode, but does support low-power modes and wake-up on network activity. For low-power operations, the user must select whether or not to allow the SLIC clock to continue operating when the MCU issues a wait instruction through the SLC wait clock mode (SLCWCM) bit in SLCC1. If SLCWCM = 1, the SLIC will enter SLIC STOP mode when the MCU executes a WAIT instruction.
The LIN 1.3 and earlier specifications transmit a checksum byte in the “CHECKSUM FIELD” of the LIN message frame. This CHECKSUM FIELD contains the inverted modulo-256 sum over all data bytes. The sum is calculated by an “ADD with Carry” where the carry bit of each addition is added to the least significant bit (LSB) of its resulting sum. This guarantees security also for the MSBs of the data bytes. The sum of modulo-256 sum over all data bytes and the checksum byte must be ‘0xFF’.
1 Bit rates over 120,000 bits per second are not recommended for LIN communications, as physical layer delay between the TX and RX pins can cause the stop bit of a byte to be mis-sampled as the last data bit. This could result in a byte framing error. The above numbers assume a perfect input waveforms into the SLCRX pin, where 1 and 0 bits are of equal length and are exactly the correct length for the appropriate speed.
Table 12-13. Maximum LIN Bit Rates for High-Speed Operation Due to Digital Receive Filter SLIC Clock (MHz) 1 Maximum LIN Bit Rate for ±1.5% SLIC Accuracy (for Master-Slave Communication (kbps) DIGITAL RX FILTER NOT CONSIDERED RXFP Prescaler Values (See Table 12-11) ÷8 (Note 1) ÷7 (Note 1) ÷6 (Note 1) ÷÷5 (Note 1) ÷÷4 (Note 1) ÷÷3 (Note 1) ÷÷2 ÷÷1 Maximum LIN Bit Rate (kbps)1 20 300 120.00 120.00 120.00 120.00 120.00 120.00 120.00 120.00 18 270 120.00 120.00 120.00 120.00 120.
Table 12-14. Digital Receive Filter Absolute Cutoff (Ideal Conditions)1 SLIC clock (MHz) Max Bit Rate (kbps) Min Pulse Width Allowed (μs) RXFP = ÷8 2 15,625 Min Pulse Width Allowed (μs) RXFP = ÷7 64.00 RXFP = ÷4 1 Max Bit Rate (kbps) 17,857 Max Bit Rate (kbps) Min Pulse Width Allowed (μs) Max Bit Rate (kbps) RXFP = ÷6 56.00 RXFP = ÷3 20,833 Min Pulse Width Allowed (μs) RXFP = ÷5 48.00 25,000 RXFP = ÷2 40.00 RXFP = ÷1 20 312,500 3.20 416,667 2.40 625,000 1.60 1,250,000 0.
12.6.16 Byte Transfer Mode Operation This subsection describes the operation and limitations of the optional UART-like byte transfer mode (BTM). This mode allows sending and receiving individual bytes, but changes the behavior of the SLCBT registers (now read/write registers) and locks the SLCDLC to 1 byte data length. The SLCBT value now becomes the bit time reference for the SLIC, where the software sets the length of one bit time rather than the SLIC module itself.
Desired Bit Rate: External Crystal Frequency: 57,600 bps 4.9152 MHz 1 Second 57,600 Bits 1 Second 4,915,200 Clock Out Period 17.36111 μs 1 Bit X X 2 Clock Out Period = = 1 SLIC Clock Period 1 SLIC Clock Period 406.901 ns 17.36111 μs 1 Bit 406.901 ns 1 SLIC Clock Period = 42.67 SLIC Clock Periods 1 Bit Therefore, the closest SLCBT value would be 43 SLIC clocks (SLCBT = 0x002B). Because you can only use even values in SLCBT, the closest acceptable value is 42 (0x002A). Figure 12-17.
Desired Bit Rate: External Crystal Frequency: 9,615 bps 8.000 MHz 1 Second 9,615 Bits 1 Second 8,000,000 Clock Out Periods 104.004 μs 1 Bit X X 2 Clock Out Period = = 1 SLIC Clock Period 1 SLIC Clock Period 250 ns 104.004 μs 1 Bit 250 ns 1 SLIC Clock Period = 416.017 SLIC Clock Periods 1 Bit Therefore, the closest SLCBT value would be 416 SLIC clocks (SLCBT = 0x01A0). Figure 12-20.
UNFILTERED RX DATA FILTERED RX DATA (³1 PRESCALE) FILTER CLOCK (³1 PRESCALE) 16 FILTER CLOCKS (³1 PRESCALE) 16 FILTER CLOCKS (³1 PRESCALE) FILTER BEGINS COUNTING DOWN FILTER REACHES 0X0 AND TOGGLES FILTER OUTPUT FILTER BEGINS COUNTING UP FILTER REACHES 0XF AND TOGGLES FILTER OUTPUT SLIC CLOCK 15 SLIC CLOCKS (1/2 OF SLCBT VALUE) 35 SLIC CLOCKS (ACTUAL FILTERED BIT LENGTH) IDEAL SLIC SAMPLE POINT (17 SLIC CLOCKS) This example assumes a SLCBT value of 30 (0x1E).
Because perfect conditions are almost impossible to attain, more robust values must be chosen for bit rates. For reliable communication, it is best to ensure that a bit time is no smaller 2x–3x longer than the filter delay on the digital receive filter. This is true in LIN or BTM mode and ensures that valid data bits which have been shortened due to ground shift, asymmetrical rise and fall times, etc., are accepted by the filter without exception.
SLCACT will only be cleared by the SLIC upon successful completion of a normal LIN message frame (see Section , “,” description for more detail). This means that in some cases, if a message frame terminates with an error condition or some source other than those cited in the SLCACT bit description, SLCACT might remain set during an otherwise idle bus time. SLCACT will then clear upon the successful completion of the next LIN message frame.
12.6.18 Digital Receive Filter The receiver section of the SLIC module includes a digital low-pass filter to remove narrow noise pulses from the incoming message. A block diagram of the digital filter is shown in Figure 12-22. DIGITAL RX FILTER PRESCALER (RXFP) INPUT SYNC RX DATA FROM SLCRX PIN D 4-BIT UP/DOWN COUNTER Q UP/DOWN OUT 4 EDGE & COUNT COMPARATOR D Q FILTERED RX DATA OUT HOLD SLIC CLOCK Figure 12-22. SLIC Module Rx Digital Filter Block Diagram 12.6.18.
12.6.18.2 Digital Filter Performance The performance of the digital filter is best described in the time domain rather than the frequency domain. If the signal on the SLCRX signal transitions, then there will be a delay before that transition appears at the filtered Rx data output signal. This delay will be between 15 and 16 clock periods, depending on where the transition occurs with respect to the sampling points.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Introduction The serial peripheral interface (SPI) module provides full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, and so forth.
Chapter 13 Serial Peripheral Interface (S08SPIV3) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFAC
Serial Peripheral Interface (S08SPIV3) 13.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 13.1.
Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 13-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 13.1.2.
Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPID) ENABLE SPI SYSTEM M SHIFT OUT SPI SHIFT REGISTER SHIFT IN MISO (SISO) S SPC0 Rx BUFFER (READ SPID) BIDIROE SHIFT DIRECTION LSBFE SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY MASTER CLOCK BUS RATE CLOCK SPIBR CLOCK GENERATOR MSTR CLOCK LOGIC SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODFEN SSOE MODE FAULT DETECTION SPRF SS SPTEF SPTIE MODF SPIE SPI INTERRUPT REQUEST Fi
Serial Peripheral Interface (S08SPIV3) BUS CLOCK PRESCALER CLOCK RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 13-4. SPI Baud Rate Generation 13.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits.
Serial Peripheral Interface (S08SPIV3) 13.3 Modes of Operation 13.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
Serial Peripheral Interface (S08SPIV3) Table 13-1. SPIC1 Field Descriptions (continued) Field Description 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 13.5.1, “SPI Clock Formats” for more details.
Serial Peripheral Interface (S08SPIV3) Table 13-3. SPIC2 Register Field Descriptions Field Description 4 MODFEN Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 13-2 for more details).
Serial Peripheral Interface (S08SPIV3) Table 13-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 13-6. SPI Baud Rate Divisor 13.4.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPIS) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Serial Peripheral Interface (S08SPIV3) Table 13-7. SPIS Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
Serial Peripheral Interface (S08SPIV3) 13.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
Serial Peripheral Interface (S08SPIV3) MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ...
Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1).
Serial Peripheral Interface (S08SPIV3) 13.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF).
Serial Peripheral Interface (S08SPIV3) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 14 Serial Communications Interface (S08SCIV4) 14.1 Introduction The MC9S08EL32 Series and MC9S08SL16 Series include a specially designed serial communications interface modules. NOTE The MC9S08EL32 Series and MC9S08SL16 Series Family of devices operates at a higher voltage range (2.7 V to 5.5 V) and does not include stop1 mode. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 14 Serial Communications Interface (S08SCIV4) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTE
Serial Communications Interface (S08SCIV4) 14.1.
Serial Communications Interface (S08SCIV4) 14.1.3 Block Diagram Figure 14-2 shows the transmitter portion of the SCI.
Serial Communications Interface (S08SCIV4) Figure 14-3 shows the receiver portion of the SCI.
Serial Communications Interface (S08SCIV4) 14.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names.
Serial Communications Interface (S08SCIV4) 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 0 0 0 0 1 0 0 R W Reset Figure 14-5. SCI Baud Rate Register (SCIxBDL) Table 14-2. SCIxBDL Field Descriptions Field 7:0 SBR[7:0] 14.2.2 Description Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator.
Serial Communications Interface (S08SCIV4) Table 14-3. SCIxC1 Field Descriptions (continued) Field 3 WAKE Description Receiver Wakeup Method Select — Refer to Section 14.3.3.2, “Receiver Wakeup Operation” for more information. 0 Idle-line wakeup. 1 Address-mark wakeup. 2 ILT Idle Line Type Select — Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic.
Serial Communications Interface (S08SCIV4) Table 14-4. SCIxC2 Field Descriptions (continued) Field Description 3 TE Transmitter Enable 0 Transmitter off. 1 Transmitter on. TE must be 1 in order to use the SCI transmitter. When TE = 1, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin).
Serial Communications Interface (S08SCIV4) Table 14-5. SCIxS1 Field Descriptions Field Description 7 TDRE Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD). 0 Transmit data register (buffer) full. 1 Transmit data register (buffer) empty.
Serial Communications Interface (S08SCIV4) Table 14-5. SCIxS1 Field Descriptions (continued) Field Description 1 FE Framing Error Flag — FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIxS1 with FE = 1 and then read the SCI data register (SCIxD). 0 No framing error detected. This does not guarantee the framing is correct. 1 Framing error.
Serial Communications Interface (S08SCIV4) Table 14-6. SCIxS2 Field Descriptions (continued) 1 Field Description 1 LBKDE LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting. 0 Break character is detected at length of 10 bit times (11 if M = 1). 1 Break character is detected at length of 11 bit times (12 if M = 1).
Serial Communications Interface (S08SCIV4) Table 14-7. SCIxC3 Field Descriptions (continued) Field 4 TXINV1 1 Description Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output. 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1.
Serial Communications Interface (S08SCIV4) MODULO DIVIDE BY (1 THROUGH 8191) BUSCLK SBR12:SBR0 BAUD RATE GENERATOR OFF IF [SBR12:SBR0] = 0 DIVIDE BY 16 Tx BAUD RATE Rx SAMPLING CLOCK (16 × BAUD RATE) BAUD RATE = BUSCLK [SBR12:SBR0] × 16 Figure 14-12. SCI Baud Rate Generation SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate.
Serial Communications Interface (S08SCIV4) Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity that is in progress must first be completed. This includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 Send Break and Queued Idle The SBK control bit in SCIxC2 is used to send break characters which were originally used to gain the attention of old teletype receivers.
Serial Communications Interface (S08SCIV4) status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double-buffered, the program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun.
Serial Communications Interface (S08SCIV4) message characters. At the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message. 14.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level.
Serial Communications Interface (S08SCIV4) Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD.
Serial Communications Interface (S08SCIV4) 14.3.5.2 Stop Mode Operation During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. .
Serial Communications Interface (S08SCIV4) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 15 Real-Time Counter (S08RTCV1) 15.1 Introduction The RTC module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, two clock sources, and one programmable periodic interrupt. This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wake up from low power modes without the need of external components. MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 15 Real-Time Counter (S08RTCV1) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFACE MODULE (
Chapter 15 Real-Time Counter (S08RTCV1) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Real-Time Counter (S08RTCV1) 15.1.1 Features Features of the RTC module include: • 8-bit up-counter — 8-bit modulo match limit — Software controllable periodic interrupt on match • Three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values — 1-kHz internal low-power oscillator (LPO) — External clock (ERCLK) — 32-kHz internal clock (IRCLK) 15.1.
Real-Time Counter (S08RTCV1) 15.1.3 Block Diagram The block diagram for the RTC module is shown in Figure 15-2. LPO Clock Source Select ERCLK IRCLK 8-Bit Modulo (RTCMOD) RTCLKS VDD RTCLKS[0] Q D Background Mode RTCPS Prescaler Divide-By E 8-Bit Comparator RTC Clock RTC Interrupt Request RTIF R Write 1 to RTIF 8-Bit Counter (RTCCNT) RTIE Figure 15-2. Real-Time Counter (RTC) Block Diagram 15.2 External Signal Description The RTC does not include any off-chip signals. 15.
Real-Time Counter (S08RTCV1) 15.3.1 RTC Status and Control Register (RTCSC) RTCSC contains the real-time interrupt status flag (RTIF), the clock select bits (RTCLKS), the real-time interrupt enable bit (RTIE), and the prescaler select bits (RTCPS). 7 6 5 4 3 2 1 0 0 0 R RTIF RTCLKS RTIE RTCPS W Reset: 0 0 0 0 0 0 Figure 15-3. RTC Status and Control Register (RTCSC) Table 15-2.
Real-Time Counter (S08RTCV1) 15.3.2 RTC Counter Register (RTCCNT) RTCCNT is the read-only value of the current RTC count of the 8-bit counter. 7 6 5 4 R 3 2 1 0 0 0 0 0 RTCCNT W Reset: 0 0 0 0 Figure 15-4. RTC Counter Register (RTCCNT) Table 15-4. RTCCNT Field Descriptions Field Description 7:0 RTCCNT RTC Count. These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register.
Real-Time Counter (S08RTCV1) RTCPS and the RTCLKS[0] bit select the desired divide-by value. If a different value is written to RTCPS, the prescaler and RTCCNT counters are reset to 0x00. Table 15-6 shows different prescaler period values. Table 15-6. Prescaler Period RTCPS 1-kHz Internal Clock (RTCLKS = 00) 1-MHz External Clock 32-kHz Internal Clock 32-kHz Internal Clock (RTCLKS = 01) (RTCLKS = 10) (RTCLKS = 11) 0000 Off Off Off Off 0001 8 ms 1.024 ms 250 μs 32 ms 0010 32 ms 2.
Real-Time Counter (S08RTCV1) Internal 1-kHz Clock Source RTC Clock (RTCPS = 0xA) RTCCNT 0x52 0x53 0x54 0x55 0x00 0x01 RTIF RTCMOD 0x55 Figure 15-6. RTC Counter Overflow Example In the example of Figure 15-6, the selected clock source is the 1-kHz internal oscillator clock source. The prescaler (RTCPS) is set to 0xA or divide-by-4. The modulo value in the RTCMOD register is set to 0x55.
Real-Time Counter (S08RTCV1) #pragma TRAP_PROC void RTC_ISR(void) { /* Clear the interrupt flag */ RTCSC.byte = RTCSC.byte | 0x80; /* RTC interrupts every 1 Second */ Seconds++; /* 60 seconds in a minute */ if (Seconds > 59){ Minutes++; Seconds = 0; } /* 60 minutes in an hour */ if (Minutes > 59){ Hours++; Minutes = 0; } /* 24 hours in a day */ if (Hours > 23){ Days ++; Hours = 0; } MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Chapter 16 Timer Pulse-Width Modulator (S08TPMV2) 16.1 Introduction The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–4). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and Connections chapter for more information). All MC9S08EL32 Series and MC9S08SL16 Series MCUs have two TPM modules. In all packages, TPM2 is 2-channel.
Chapter 16 Timer Pulse-Width Modulator (S08TPMV2) HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFAC
Timer/PWM Module (S08TPMV3) 16.1.
Timer/PWM Module (S08TPMV3) • • Edge-aligned PWM mode The value of a 16-bit modulo register plus 1 sets the period of the PWM output signal. The channel value register sets the duty cycle of the PWM output signal. The user may also choose the polarity of the PWM output signal. Interrupts are available at the end of the period and at the duty-cycle transition point.
Timer/PWM Module (S08TPMV3) BUS CLOCK FIXED SYSTEM CLOCK SYNC EXTERNAL CLOCK CLOCK SOURCE SELECT OFF, BUS, FIXED SYSTEM CLOCK, EXT PRESCALE AND SELECT ³1, 2, 4, 8, 16, 32, 64, or ³128 CLKSB:CLKSA PS2:PS1:PS0 CPWMS 16-BIT COUNTER TOF COUNTER RESET TOIE INTERRUPT LOGIC 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT LOGIC TPMxCH0 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERNAL BUS 16-BIT LATCH CHANNEL 1 MS0B MS0A ELS1B ELS1A CH0IE INTERRUPT LOGIC PORT LOGIC TPMx
Timer/PWM Module (S08TPMV3) The TPM channels are programmable independently as input capture, output compare, or edge-aligned PWM channels. Alternately, the TPM can be configured to produce CPWM outputs on all channels. When the TPM is configured for CPWMs, the counter operates as an up/down counter; input capture, output compare, and EPWM functions are not practical. If a channel is configured as input capture, an internal pullup device may be enabled for that channel.
Timer/PWM Module (S08TPMV3) 16.2.1.1 EXTCLK — External Clock Source Control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the TPM prescaler and subsequently the 16-bit TPM counter. The external clock source is synchronized in the TPM.
Timer/PWM Module (S08TPMV3) When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not = 0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM, and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced low when the channel value register matches the timer counter.
Timer/PWM Module (S08TPMV3) When the TPM is configured for center-aligned PWM (and ELSnB:ELSnA not = 0:0), the data direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output.
Timer/PWM Module (S08TPMV3) 16.3 Register Definition This section consists of register descriptions in address order. A typical MCU system may contain multiple TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1. 16.3.
Timer/PWM Module (S08TPMV3) Table 16-3. TPMxSC Field Descriptions (continued) Field Description 4–3 Clock source selects. As shown in Table 16-4, this 2-bit field is used to disable the TPM system or select one of CLKS[B:A] three clock sources to drive the counter prescaler. The fixed system clock source is only meaningful in systems with a PLL-based or FLL-based system clock. When there is no PLL or FLL, the fixed-system clock source is the same as the bus rate clock.
Timer/PWM Module (S08TPMV3) Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data involved in the write. R 7 6 5 4 3 2 1 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 W Reset Any write to TPMxCNTH clears the 16-bit counter 0 0 0 0 0 0 Figure 16-8.
Timer/PWM Module (S08TPMV3) When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while BDM is active.
Timer/PWM Module (S08TPMV3) Table 16-6. TPMxCnSC Field Descriptions Field Description 7 CHnF Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers.
Timer/PWM Module (S08TPMV3) Table 16-7. Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration 0 00 01 Input capture Capture on rising edge only 01 10 Capture on falling edge only 11 Capture on rising or falling edge 01 1X Output compare 10 Clear output on compare 11 Set output on compare 10 Edge-aligned PWM X1 1 XX High-true pulses (clear output on compare) Low-true pulses (set output on compare) 10 Center-aligned PWM X1 16.3.
Timer/PWM Module (S08TPMV3) (becomes unlatched) when the TPMxCnSC register is written (whether BDM mode is active or not). Any write to the channel registers will be ignored during the input capture mode. When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxCnSC register) such that the buffer latches remain in the state they were in when the BDM became active, even if one or both halves of the channel register are read while BDM is active.
Timer/PWM Module (S08TPMV3) The following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 16.4.1 Counter All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL).
Timer/PWM Module (S08TPMV3) Table 16-8. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 00 No clock selected (TPM counter disabled) 01 Bus rate clock 10 Fixed system clock 11 External source The bus rate clock is the main system bus clock for the MCU. This clock source requires no synchronization because it is the clock that is used for all internal MCU activities including operation of the CPU and buses.
Timer/PWM Module (S08TPMV3) 16.4.1.3 Counting Modes The main timer counter has two counting modes. When center-aligned PWM is selected (CPWMS=1), the counter operates in up/down counting mode. Otherwise, the counter operates as a simple up counter. As an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL.
Timer/PWM Module (S08TPMV3) In output compare mode, values are transferred to the corresponding timer channel registers only after both 8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so: • If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written • If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter (end of the prescaler counting) after the second byte is written.
Timer/PWM Module (S08TPMV3) the TPM counter is a free-running counter then the update is made when the TPM counter changes from 0xFFFE to 0xFFFF. 16.4.2.4 Center-Aligned PWM Mode This type of PWM output uses the up/down counting mode of the timer counter (CPWMS=1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal while the period is determined by the value in TPMxMODH:TPMxMODL.
Timer/PWM Module (S08TPMV3) Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a TPM must be used in CPWM mode when CPWMS=1. The TPM may be used in an 8-bit MCU. The settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths.
Timer/PWM Module (S08TPMV3) All TPM interrupts are listed in Table 16-9 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt processing logic. Table 16-9.
Timer/PWM Module (S08TPMV3) 16.6.2.1.2 Center-Aligned PWM Case When CPWMS=1, TOF gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). In this case the TOF corresponds to the end of a PWM period. 16.6.2.2 Channel Event Interrupt Description The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare, edge-aligned PWM, or center-aligned PWM). 16.6.2.2.
Timer/PWM Module (S08TPMV3) BDM mode returns the latched value of TPMxCNTH:L from the read buffer instead of the frozen TPM counter value. — This read coherency mechanism is cleared in TPM v3 in BDM mode if there is a write to TPMxSC, TPMxCNTH or TPMxCNTL. Instead, in these conditions the TPM v2 does not clear this read coherency mechanism. 3. Read of TPMxCnVH:L registers (Section 16.3.
Timer/PWM Module (S08TPMV3) TPM counter changes from (TPMxMODH:L - 1) to (TPMxMODH:L). If the TPM counter is a free-running counter, then this update is made when the TPM counter changes from $FFFE to $FFFF. Instead, the TPM v2 makes this update after that the both bytes were written and when the TPM counter changes from TPMxMODH:L to $0000. — Center-Aligned PWM (Section 16.4.2.
EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxMODH:TPMxMODL = 0x0005 RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 0 1 2 3 4 6 7 0 1 2 ... 01 00 CLKSB:CLKSA BITS 5 MSnB:MSnA BITS 00 10 ELSnB:ELSnA BITS 00 10 TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure 0-1. Generation of high-true EPWM signal by TPM v2 and v3 after the reset MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Timer/PWM Module (S08TPMV3) EPWM mode TPMxMODH:TPMxMODL = 0x0007 TPMxMODH:TPMxMODL = 0x0005 RESET (active low) BUS CLOCK TPMxCNTH:TPMxCNTL 0 1 2 3 4 6 7 0 1 2 ... 01 00 CLKSB:CLKSA BITS 5 MSnB:MSnA BITS 00 10 ELSnB:ELSnA BITS 00 01 TPMv2 TPMxCHn TPMv3 TPMxCHn CHnF BIT (in TPMv2 and TPMv3) Figure 0-2.
Chapter 17 Development Support 17.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories.
Development SupportChapter 17 Development Support HCS08 CORE BKGD/MS BDC BKP TCLK 2-CHANNEL TIMER/PWM 0 MODULE (TPM2) 1 HCS08 SYSTEM CONTROL RESET PORT A ANALOG COMPARATOR + (ACMP1) – OUT CPU RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTA0/PIA0/TPM1CH0/TCLK/ACMP1+/ADP0 PTA1/PIA1/TPM2CH0/ACMP1–/ADP1 PTA2/PIA2/SDA/RxD/ACMP1O/ADP2 PTA3/PIA3/SCL/TxD/ADP3 PTA6/TPM2CH0 PTA7/TPM2CH1 COP SLAVE LIN INTERFACE CONTROLLER (SLIC) USER FLASH 32K / 16K RxD TxD Rx Tx SERIAL PERIPHERAL INTERFAC
Development SupportChapter 17 Development Support MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Development Support 17.1.
Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system.
Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section).
Development Support Figure 17-3 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges.
Development Support Figure 17-4 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles).
Development Support Figure 17-5 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
Development Support 17.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program.
Development Support Table 17-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
Development Support 17.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture.
Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port.
Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU.
Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match.
Development Support 17.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 17.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue.
Development Support 17.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 17-6.
Development Support Table 17-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 17-7. System Background Debug Force Reset Register (SBDFR) Table 17-3.
Development Support 17.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word.
Development Support 17.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 17-8. Debug Control Register (DBGC) Table 17-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
Development Support 17.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 17-9. Debug Trigger Register (DBGT) Table 17-5.
Development Support 17.4.3.9 Debug Status Register (DBGS) This is a read-only status register. R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-10. Debug Status Register (DBGS) Table 17-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming.
Appendix A Electrical Characteristics A.1 Introduction This section contains the most accurate electrical and timing information for the MC9S08EL32 Series and MC9S08SL16 Series of microcontrollers available at the time of publication. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods.
Appendix A Electrical Characteristics Table A-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to +5.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID ± 25 mA Tstg –55 to 150 °C Storage temperature range 1 Input must be current limited to the value specified.
Appendix A Electrical Characteristics 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Junction to Ambient Natural Convection The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn.
Appendix A Electrical Characteristics Table A-4. ESD and Latch-up Test Conditions Model Description Human Body Latch-up Symbol Value Unit Series resistance R1 1500 Ω Storage capacitance C 100 pF Number of pulses per pin — 3 Minimum input voltage limit – 2.5 V Maximum input voltage limit 7.5 V Table A-5. ESD and Latch-Up Protection Characteristics Rating1 No. 1 A.
Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Num C 7 Characteristic P Input low voltage; all digital inputs Condition Min Typ1 Max Unit VIL 5V — — 0.35 x VDD V 3V — — 0.35 x VDD C 8 C Input hysteresis 9 P Input leakage current (per pin) Vhys 0.06 x VDD V |IIn| VIn = VDD or VSS — — 1 μA |IOZ| VIn = VDD or VSS — — 1 μA VIn = VDD or VSS — — 2 μA 17 37 52 kΩ 17 37 52 kΩ VIN > VDD 0 — 2 mA VIN < VSS, 0 — –0.
Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Num C Characteristic Symbol Condition Min Typ1 Max 5V — 100 — 3V — 60 — 1.18 1.202 1.21 23 T Low-voltage inhibit reset/recover hysteresis Vhys 24 P Bandgap Voltage Reference10 VBG Unit mV V 1 Typical values are measured at 25°C. Characterized, not tested When a pin interrupt is configured to detect rising edges, pulldown resistors are used in place of pullup resistors.
Appendix A Electrical Characteristics 1.0 2 125°C 25°C –40°C 0.8 VOL (V) VOL (V) 1.5 1 0.5 0 125°C 25°C –40°C Max 1.5V@4mA Max 0.8V@1mA 0.6 0.4 0.2 0 1 2 3 IOL (mA) a) VDD = 5V, Low Drive 4 0 5 0 0.4 0.8 1.2 IOL (mA) b) VDD = 3V, Low Drive 1.6 2.0 Figure A-2. Typical VOL vs IOL, Low Drive Strength 1.0 2 125°C 25°C –40°C 0.8 VDD – VOH (V) VDD – VOH (V) 1.5 1 0.5 0 125°C 25°C –40°C Max 1.5V@20mA Max 0.8V@5mA 0.6 0.4 0.
Appendix A Electrical Characteristics 1.0 2 125°C 25°C –40°C 0.8 VDD – VOH (V) VDD – VOH (V) 1.5 1 0.5 0 125°C 25°C –40°C Max 1.5V@4mA Max 0.8V@1mA 0.6 0.4 0.2 0 –1 –2 –3 IOH (mA) a) VDD = 5V, Low Drive –4 –5 0 0 –0.4 –0.8 –1.2 –1.6 IOH (mA) b) VDD = 3V, Low Drive –2.0 Figure A-4. Typical VDD – VOH vs IOH, Low Drive Strength A.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table A-7.
Appendix A Electrical Characteristics Table A-7. Supply Current Characteristics (continued) Num C Parameter Symbol VDD (V) Typ1 Max2 Unit Stop2 mode supply current 5 6 7 8 1 2 3 4 5 6 7 C –40°C (C,M, & V suffix) 0.9 – P 25°C (All parts) 0.9 – P5 85°C (C suffix only) 5.0 40.0 P5 105°C (V suffix only) 11.0 50.0 P5 125°C (M suffix only) 29.1 65.0 C –40°C (C,M, & V suffix) 0.9 – P 25°C (All parts) 0.9 – P5 85°C (C suffix only) 4.2 35.0 P5 105°C (V suffix only) 8.
Appendix A Electrical Characteristics 12 FEI FBELP 10 Run IDD (mA) 8 6 4 2 0 0 1 2 4 8 20 16 fbus (MHz) Figure A-5. Typical Run IDD vs. Bus Frequency (VDD = 5V) 6 RUN 5 Run IDD (μA) 4 3 WAIT 2 1 0 –40 0 25 Temperature (°C) 85 105 125 Figure A-6. Typical Run and Wait IDD vs. Temperature (VDD = 5V; fbus = 8MHz) MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev.
Appendix A Electrical Characteristics 60 STOP2 STOP3 STOP IDD (μA) 50 40 30 20 10 0 –40 0 25 Temperature (°C) 85 105 125 Figure A-7. Typical Stop IDD vs. Temperature (VDD = 5V) A.8 External Oscillator (XOSC) Characteristics Table A-8. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient) Num Symbol Min Typ1 Max Unit flo 32 — 38.
Appendix A Electrical Characteristics Table A-8. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient) (continued) Num C Symbol Min Typ1 Max t CSTL-LP — 200 — CSTL-HGO — 400 — t CSTH-LP — 5 — CSTH-HGO — 20 — fextal 0.
Appendix A Electrical Characteristics Table A-9. ICS Frequency Specifications (continued) (Temperature Range = –40 to 125°C Ambient) Num C Rating Symbol Min Typical Max Unit 9 D Total deviation of trimmed DCO output frequency over voltage and temperature Δfdco_t — + 0.5 – 1.0 ±2 %fdco 10 D Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0°C to 70 °C Δfdco_t — ± 0.5 ±1 %fdco 11 D FLL acquisition time 2 1 ms 0.
Appendix A Electrical Characteristics Table A-10. Analog Comparator Electrical Specifications (continued) Num C Rating 4 D Analog input offset voltage 5 D Analog Comparator hysteresis 6 D 7 D A.11 Symbol Min Typical Max Unit 20 40 mV VAIO VH 3.0 6.0 20.0 mV Analog input leakage current IALKG — — 1.0 μA Analog Comparator initialization delay tAINIT — — 1.0 μs ADC Characteristics Table A-11. ADC Operating Conditions Symb Min Typ1 Max Unit VDDAD 2.7 — 5.
Appendix A Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN + VADIN VAS – CAS + – RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure A-9. ADC Input Impedance Equivalency Diagram Table A-12.
Appendix A Electrical Characteristics Table A-12. ADC Characteristics (continued) Characteristic Conditions C Symb Min Typ1 Max Unit Comment Conversion time (including sample time) Short sample (ADLSMP=0) D tADC — 20 — — 40 — ADCK cycles — 3.5 — See ADC Chapter for conversion time variances — 23.5 — — ±1 ±2.5 — ±0.5 ±1 — ±.5 ±3.5 — ±0.7 ±1.5 — ±0.5 ±1.0 — ±0.3 ±0.
Appendix A Electrical Characteristics Table A-12. ADC Characteristics (continued) Characteristic Conditions Temp sensor slope -40°C to 25°C Temp sensor voltage 25°C C Symb Min Typ1 Max Unit D m — 3.266 — mV/°C — 3.638 — — 1.396 — 25°C to 125°C D VTEMP25 Comment V 1 Typical values assume VDD = 5.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production.
Appendix A Electrical Characteristics textrst RESET PIN Figure A-10. Reset Timing tIHIL Pin Interrupts Pin Interrupts tILIH Figure A-11. Pin Interrupt Timing A.12.2 TPM/MTIM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-14.
Appendix A Electrical Characteristics tICPW TPMCHn TPMCHn tICPW Figure A-13. Timer Input Capture Pulse A.12.3 SPI Table A-15 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system. Table A-15.
Appendix A Electrical Characteristics Table A-15. SPI Electrical Characteristic (continued) Num1 C 11 D 12 D Rating2 Symbol Min Max Unit Master Slave tHO tHO –10 –10 — — ns ns Master Slave fop fop fBus/2048 dc 55 fBus/4 MHz Data hold time (outputs) Operating frequency 1 Refer to Figure A-14 through Figure A-17. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.
Appendix A Electrical Characteristics SS(1) (OUTPUT) 1 3 2 SCK (CPOL = 0) (OUTPUT) 5 4 SCK (CPOL = 1) (OUTPUT) 5 4 6 MISO (INPUT) 7 MSB IN(2) BIT 6 . . . 1 LSB IN 11 10 MOSI (OUTPUT) MSB OUT(2) BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (MODFEN = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-15.
Appendix A Electrical Characteristics SS (INPUT) 3 1 2 SCK (CPOL = 0) (INPUT) 5 4 SCK (CPOL = 1) (INPUT) 5 4 10 MISO (OUTPUT) SEE NOTE 11 SLAVE MSB OUT 6 8 MOSI (INPUT) 9 BIT 6 . . . 1 SLAVE LSB OUT 7 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure A-17. SPI Slave Timing (CPHA = 1) A.13 Flash and EEPROM Specifications This section provides details about program/erase times and program-erase endurance for the Flash and EEPROM memory.
Appendix A Electrical Characteristics Table A-16. Flash Characteristics (continued) Num 10 11 C Characteristic C EEPROM Program/erase endurance3 TL to TH = –40°C to + 0°C TL to TH = 0°C to + 125°C T = 25°C C Data retention4 Symbol Min nEEPE 10,000 50,000 tD_ret 15 Typical Max Unit cycles 100,000 — — — 100 — years 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles.
Appendix A Electrical Characteristics 1 Data based on qualification test results. A.14.2 Conducted Transient Susceptibility Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method.
Appendix B Ordering Information and Mechanical Drawings Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering information for MC9S08EL32 Series and MC9S08SL16 Series devices. Table B-1. Devices in the MC9S08EL32 Series and MC9S08SL16 Series Memory Device Number1 FLASH 1 2 B.1.
Appendix B Ordering Information and Mechanical Drawings B.2 Mechanical Drawings The latest package outline drawings are available on the product summary pages on http://www.freescale.com. Table B-2 lists the document numbers per package type. Use these numbers in the web page’s keyword search engine to find the latest package outline drawings. Table B-2. Package Descriptions Pin Count Type Abbreviation Designator Document No.
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