MC9S08GB60A MC9S08GB32A MC9S08GT60A MC9S08GT32A Data Sheet HCS08 Microcontrollers MC9S08GB60A Rev. 2 07/2008 freescale.
MC9S08GB60A Data Sheet Covers: MC9S08GB60A MC9S08GB32A MC9S08GT60A MC9S08GT32A MC9S08GB60A Rev.
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Revision Number Revision Date 1.00 07/14/2005 Initial public release. 1.01 09/04/2007 Added a footnote to RTI of Table 3.
List of Chapters Chapter Number Title Page Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 1.4 Overview .........................................................................................................................................17 Features ...........................................................................................................................................17 1.2.1 Standard Features of the HCS08 Family .........................................................................17 1.2.
Section Number Title Page Chapter 4 Memory 4.1 4.2 4.3 4.4 4.5 4.6 MC9S08GBxxA/GTxxA Memory Map ..........................................................................................43 4.1.1 Reset and Interrupt Vector Assignments ..........................................................................43 Register Addresses and Bit Assignments ........................................................................................45 RAM ..............................................................
Section Number 5.8.2 5.8.3 5.8.4 5.8.5 5.8.6 5.8.7 5.8.8 Title Page System Reset Status Register (SRS) ................................................................................74 System Background Debug Force Reset Register (SBDFR) ...........................................75 System Options Register (SOPT) ....................................................................................76 System Device Identification Register (SDIDH, SDIDL) ...............................................
Section Number 7.3 7.4 7.5 Title Page 7.2.3 External Clock Connections ..........................................................................................108 7.2.4 External Crystal/Resonator Connections .......................................................................108 Functional Description ..................................................................................................................109 7.3.1 Off Mode (Off) ...........................................................
Section Number 8.3 8.4 8.5 Title Page Addressing Modes .........................................................................................................................133 8.3.1 Inherent Addressing Mode (INH) ..................................................................................133 8.3.2 Relative Addressing Mode (REL) .................................................................................133 8.3.3 Immediate Addressing Mode (IMM) ............................................
Section Number Title Page 10.5.1 Counter ..........................................................................................................................159 10.5.2 Channel Mode Selection ................................................................................................160 10.5.2.1 Input Capture Mode ......................................................................................160 10.5.2.2 Output Compare Mode .................................................................
Section Number Title Page 11.3.5.4 Single-Wire Operation ..................................................................................188 Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.1 Introduction ...................................................................................................................................189 12.1.1 Features ..........................................................................................................................191 12.1.
Section Number 13.4 13.5 13.6 13.7 Title Page 13.3.4 IIC Status Register (IIC1S) ............................................................................................213 13.3.5 IIC Data I/O Register (IIC1D) .......................................................................................214 Functional Description ..................................................................................................................215 13.4.1 IIC Protocol ........................................
Section Number Title Page 14.6.4 ATD Pin Enable (ATD1PE) ...........................................................................................238 Chapter 15 Development Support 15.1 Introduction ...................................................................................................................................239 15.1.1 Features ..........................................................................................................................240 15.
Section Number Title Page A.6 Supply Current Characteristics ......................................................................................................267 A.7 ATD Characteristics ......................................................................................................................271 A.8 Internal Clock Generation Module Characteristics .......................................................................273 A.8.1 ICG Frequency Specifications .................................
Chapter 1 Device Overview 1.1 Overview The MC9S08GBxxA/GTxxA are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.2 Features Features have been organized to reflect: • Standard features of the HCS08 Family • Features of the MC9S08GBxxA/GTxxA MCU 1.2.
Chapter 1 Device Overview 1.2.
Chapter 1 Device Overview 1.2.3 Devices in the MC9S08GBxxA/GTxxA Series Table 1-1 lists the devices available in the MC9S08GBxxA/GTxxA series and summarizes the differences among them. Table 1-1. Devices in the MC9S08GBxxA/GTxxA Series 1 1.
Chapter 1 Device Overview IRQ RTI COP IRQ LVD USER FLASH (Gx60A = 61,268 BYTES) (Gx32A = 32,768 BYTES) ANALOG-TO-DIGITAL CONVERTER (10-BIT) (ATD1) IIC MODULE (IIC1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 5-CHANNEL TIMER/PWM MODULE (TPM2) USER RAM (Gx60A = 4096 BYTES) (Gx32A = 2048 BYTES) 8 SCL1 SDA1 SCL1 SCL1 5 3 SERIAL PERIPHERAL INTERFACE MODULE (SPI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) VOLTAGE REGULATOR SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 PT
Chapter 1 Device Overview Table 1-2 lists the functional versions of the on-chip modules. Table 1-2. Block Versions 1.
Chapter 1 Device Overview • • • FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK. Otherwise the fixed-frequency clock will be BUSCLK. ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow.
Chapter 2 Pins and Connections 2.1 Introduction This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. MC9S08GB60A Data Sheet, Rev.
Chapter 2 Pins and Connections PTG4 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS VSSAD VDDAD PTF1 PTF0 PTA7/KBI1P7 PTA6/KBI1P6 PTA5/KBI1P5 PTA4/KBI1P4 63 62 61 60 59 58 57 56 55 54 53 52 51 50 64 PTA3/KBI1P3 PTG5 Device Pin Assignment PTG6 2.
PTA2/KBI1P2 37 PTA4/KBI1P4 39 38 PTA3/KBI1P3 PTA5/KBI1P5 40 41 PTA6/KBI1P6 VDDAD 42 PTA7/KBI1P7 RESET 1 43 44 VSSAD 45 PTG0/BKGD/MS 46 PTG1/XTAL 47 PTG2/EXTAL 48 PTG3 Chapter 2 Pins and Connections 36 PTA1/KBI1P1 IRQ 12 25 PTB0/AD1P0 24 PTB1/AD1P1 PTD4/TPM2CH1 26 23 PTE1/RxD1 11 PTD3/TPM2CH0 PTB2/AD1P2 22 27 PTD2/TPM1CH2 PTE0/TxD1 10 21 PTB3/AD1P3 PTD1/TPM1CH1 28 20 PTC7 9 PTD0/TPM1CH0 PTB4/AD1P4 19 29 VDD PTC6 8 18 30 PTB5/AD1P5 VSS2 PTC5 7 17 31 PTB6/AD1P6
PTG0/BKGD/MS VSSAD VDDAD PTA7/KBI1P7 PTA6/KBI1P6 PTA5/KBI1P5 PTA4/KBI1P4 PTA3/KBI1P3 42 41 40 39 38 37 36 35 34 PTA2/KBI1P2 PTG1/XTAL RESET 1 43 44 PTG2/EXTAL Chapter 2 Pins and Connections 33 PTA1/KBI1P1 28 PTB6/AD1P6 PTC5 7 27 PTB5/AD1P5 PTC6 8 26 PTB4/AD1P4 PTE0/TxD1 9 25 PTB3/AD1P3 PTE1/RxD1 10 24 PTB2/AD1P2 23 PTB1/AD1P1 PTB0/AD1P0 22 PTE2/SS1 12 IRQ 11 21 6 PTD4/TPM2CH1 PTC4 20 PTB7/AD1P7 PTD3/TPM2CH0 29 19 5 PTD1/TPM1CH1 PTC3/SCL1 18 VREFH PT
Chapter 2 Pins and Connections VDDAD 1 42 PTA7/KBI1P7 VSSAD 2 41 PTA6/KBI1P6 PTG0/BKGD/MS 3 40 PTA5/KBI1P5 PTG1/XTAL 4 39 PTA4/KBI1P4 PTG2/EXTAL 5 38 PTA3/KBI1P3 RESET 6 37 PTA2/KBI1P2 PTC0/TxD2 7 36 PTA1/KBI1P1 PTC1/RXD2 8 35 PTA0/KBI1P0 PTC2/SDA1 9 34 VREFL PTC3/SCL1 10 33 VREFH PTC4 11 32 PTB7/AD1P7 PTE0/TxD1 12 31 PTB6/AD1P6 PTE1/RxD1 13 30 PTB5/AD1P5 IRQ 14 29 PTB4/AD1P4 PTE2/SS1 15 28 PTB3/AD1P3 PTE3/MISO1 16 27 PTB2/AD1P2 PTE4/MOSI1 17
Chapter 2 Pins and Connections VREFH CBYAD 0.1 μF + 3V MC9S08GBxxA/GTxxA PTA0/KBI1P0 VSSAD VREFL VDD VDD SYSTEM POWER VDDAD CBLK + 10 μF CBY 0.1 μF VSS NOTE 4 PTA1/KBI1P1 PTA2/KBI1P2 PORT A PTA3/KBI1P3 PTA4/KBI1P4 PTA5/KBI1P5 PTA6/KBI1P6 PTA7/KBI1P7 NOTE 1 RF C1 RS C2 X1 PTB0/AD1P0 XTAL NOTE 2 PTB1/AD1P1 PTB2/AD1P2 EXTAL NOTE 2 PORT B PTB4/AD1P4 PTB5/AD1P5 BACKGROUND HEADER VDD BKGD/MS NOTE 3 VDD 4.
Chapter 2 Pins and Connections 2.3.1 Power VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins.
Chapter 2 Pins and Connections debug connector so a development system can directly reset the MCU system. If desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). Whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for approximately 34 cycles of fSelf_reset, released, and sampled again approximately 38 cycles of fSelf_reset later.
Chapter 2 Pins and Connections For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the appropriate section from Table 2-1. Table 2-1.
Chapter 2 Pins and Connections 2.3.6 Signal Properties Summary Table 2-2 summarizes I/O pin characteristics. These characteristics are determined by the way the common pin interfaces are hardwired to internal circuits. Table 2-2. Signal Properties Pin Name High Current Pin Output Slew 1 Pull-Up2 VDD — — — VSS — — — VDDAD — — — VSSAD — — — VREFH — — — VREFL — — — Y N Y Pin contains integrated pullup. IRQPE must be set to enable IRQ function.
Chapter 2 Pins and Connections Table 2-2.
Chapter 2 Pins and Connections MC9S08GB60A Data Sheet, Rev.
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08GBxxA/GTxxA are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • • 3.
Chapter 3 Modes of Operation • When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.
Chapter 3 Modes of Operation when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2. Table 3-1 summarizes the behavior of the MCU in each of the stop modes. Table 3-1.
Chapter 3 Modes of Operation into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting stop2 mode until a 1 is written to PPDACK in SPMSC2. Exit from stop2 is performed by asserting either of the wake-up pins: RESET or IRQ, or by an RTI interrupt. IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured before entering stop2.
Chapter 3 Modes of Operation 3.6.4 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in the Chapter 15, “Development Support,” section of this data sheet. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible.
Chapter 3 Modes of Operation clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop1 Mode,” Section 3.6.2, “Stop2 Mode,” and Section 3.6.3, “Stop3 Mode,” for specific information on system behavior in stop modes. I/O Pins • All I/O pin states remain unchanged when the MCU enters stop3 mode. • If the MCU is configured to go into stop2 mode, all I/O pins states are latched before entering stop.
Chapter 3 Modes of Operation IIC — When the MCU enters stop mode, the clocks to the IIC module stops. The module halts operation. If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. MC9S08GB60A Data Sheet, Rev.
Chapter 3 Modes of Operation MC9S08GB60A Data Sheet, Rev.
Chapter 4 Memory 4.1 MC9S08GBxxA/GTxxA Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08GBxxA/GTxxA series of MCUs consists of RAM, flash program memory for nonvolatile data storage, plus I/O and control/status registers.
Chapter 4 Memory 4.1.1 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08GBxxA/GTxxA. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets, Interrupts, and System Configuration.” Table 4-1.
Chapter 4 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08GBxxA/GTxxA are divided into these three groups: • Direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. Table 4-3.
Chapter 4 Memory Table 4-4. Nonvolatile Register Summary Address Register Name Bit 7 6 5 0xFFB0 – NVBACKKEY 0xFFB7 0xFFB8 – Reserved 0xFFBC 0xFFBD NVPROT 1 0xFFBE Reserved 0xFFBF NVOPT 1 4 3 2 1 Bit 0 8-Byte Comparison Key — — — — — — — — — — — — — — — — FPOPEN FPDIS FPS2 FPS1 FPS0 0 0 0 — — — — — — — — KEYEN FNORED 0 0 0 0 SEC01 SEC00 This location is used to store the factory trim value for the ICG.
Chapter 4 Memory to program the entire array through the single-wire background debug interface. Because no special voltages are needed for flash erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. 4.4.
Chapter 4 Memory 4.4.3 Program and Erase Command Execution The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are: 1. Write a data value to an address in the flash array. The address and data information from this write is latched into the flash interface. This write is a required first step in any command sequence.
Chapter 4 Memory START FACCERR ? 0 CLEAR ERROR (1) WRITE TO FCDIV(1) Only required once after reset. WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (2) FPVIO OR FACCERR ? (2) Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NO 0 FCCF ? 1 DONE Figure 4-2. Flash Program and Erase Flowchart 4.4.
Chapter 4 Memory program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. This is because the high voltage to the array must be disabled and then enabled again. If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array.
Chapter 4 Memory 4.4.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
Chapter 4 Memory 4.4.7 Vector Redirection Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at address 0xFFBF to zero.
Chapter 4 Memory 2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations. These writes must be done in order, starting with the value for NVBACKKEY and ending with NVBACKKEY+7. STHX should not be used for these writes because these writes cannot be done on adjacent bus cycles. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O. 3. Writing 0 to KEYACC in the FCNFG register.
Chapter 4 Memory 7 R 6 5 4 3 2 1 0 PRDIV8 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 0 0 0 0 0 0 0 DIVLD W Reset 0 = Unimplemented or Reserved Figure 4-4. Flash Clock Divider Register (FCDIV) Table 4-6. FCDIV Field Descriptions Field Description 7 DIVLD Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been written since reset.
Chapter 4 Memory 4.6.2 Flash Options Register (FOPT and NVOPT) During reset, the contents of the nonvolatile location NVOPT are copied from flash into FOPT. Bits 5 through 2 are not used and always read 0. This register may be read at any time, but writes have no meaning or effect. To change the value in this register, erase and reprogram the NVOPT location in flash memory as usual and then issue a new MCU reset.
Chapter 4 Memory 4.6.3 Flash Configuration Register (FCNFG) Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written. R 7 6 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 = Unimplemented or Reserved Figure 4-6. Flash Configuration Register (FCNFG) Table 4-9. FCNFG Field Descriptions Field Description 5 KEYACC Enable Writing of Access Key — This bit enables writing of the backdoor comparison key.
Chapter 4 Memory Table 4-10. FPROT Field Descriptions (continued) Field 6 FPDIS 5:3 FPS[2:0] Description Flash Protection Disable 0 Flash block specified by FPS2:FPS0 is block protected (program and erase not allowed). 1 No flash block is protected. Flash Protect Size Selects — When FPDIS = 0, this 3-bit field determines the size of a protected block of flash locations at the high address end of the flash (see Table 4-11). Protected flash locations cannot be erased or programmed. Table 4-11.
Chapter 4 Memory 4.6.5 Flash Status Register (FSTAT) Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits that can be read at any time. Writes to these bits have special meanings that are discussed in the bit descriptions. 7 R 6 5 4 FPVIOL FACCERR 0 0 FCCF FCBEF 3 2 1 0 0 FBLANK 0 0 0 0 0 0 W Reset 1 1 = Unimplemented or Reserved Figure 4-8. Flash Status Register (FSTAT) Table 4-12.
Chapter 4 Memory 4.6.6 Flash Command Register (FCMD) Only five command codes are recognized in normal user modes as shown in Table 4-14. Refer to Section 4.4.3, “Program and Erase Command Execution” for a detailed discussion of flash programming and erase operations. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0 0 0 0 0 0 0 0 0 Reset Figure 4-9. Flash Command Register (FCMD) Table 4-13.
Chapter 4 Memory MC9S08GB60A Data Sheet, Rev.
Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08GBxxA/GTxxA. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data manual. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and System Configuration • • • • Illegal opcode detect Background debug forced reset The reset pin (RESET) Clock generator loss of lock and loss of clock reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) module switches to self-clocked mode with the frequency of fSelf_reset selected.
Chapter 5 Resets, Interrupts, and System Configuration in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts. When the CPU receives a qualified interrupt request, it completes the current instruction before responding to the interrupt.
Chapter 5 Resets, Interrupts, and System Configuration UNSTACKING ORDER ² TOWARD LOWER ADDRESSES 7 0 5 1 CONDITION CODE REGISTER 4 2 ACCUMULATOR 3 3 INDEX REGISTER (LOW BYTE X)* 2 4 PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT ² ² STACKING ORDER ² TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1.
Chapter 5 Resets, Interrupts, and System Configuration 5.5.2.2 Edge and Level Sensitivity The IRQMOD control bit re-configures the detection logic so it detects edge events and pin levels. In this edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level. 5.5.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-1.
Chapter 5 Resets, Interrupts, and System Configuration 5.6 Low-Voltage Detect (LVD) System The MC9S08GBxxA/GTxxA includes a system to protect against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system comprises a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (VLVDH) or low (VLVDL).
Chapter 5 Resets, Interrupts, and System Configuration configured for low bandwidth operation (RANGE = 0). If active BDM mode is enabled in stop3, the internal RTI clock is not available. The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control value (RTIS2:RTIS1:RTIS0) used to select one of seven RTI periods. The RTI has a local interrupt enable, RTIE, to allow masking of the real-time interrupt.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes two unimplemented bits which always read 0, four read/write bits, one read-only status bit, and one write-only bit. These bits are used to configure the IRQ function, report status, and acknowledge IRQ events.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.2 System Reset Status Register (SRS) This register includes six read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-3. SRS Field Descriptions (continued) Field Description 2 ICG Internal Clock Generation Module Reset — Reset was caused by an ICG module reset. 0 Reset not caused by ICG module. 1 Reset caused by ICG module. 1 LVD Low Voltage Detect — If the LVD reset is enabled (LVDE = LVDRE = 1) and the supply drops below the LVD trip voltage, an LVD reset occurs. The LVD function is disabled when the MCU enters stop.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.4 System Options Register (SOPT) This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.5 System Device Identification Register (SDIDH, SDIDL) This read-only register is included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.6 System Real-Time Interrupt Status and Control Register (SRTISC) This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay selects, and three unimplemented bits, which always read 0. R 7 6 RTIF 0 W 5 4 RTICLKS RTIE 0 0 3 2 1 0 RTIS2 RTIS1 RTIS0 0 0 0 0 RTIACK Reset 0 0 0 = Unimplemented or Reserved Figure 5-8. System RTI Status and Control Register (SRTISC) Table 5-8.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.7 R System Power Management Status and Control 1 Register (SPMSC1) 7 6 LVDF 0 4 3 2 LVDIE LVDRE1 LVDSE(1) LVDE(1) 0 1 1 1 1 0 0 0 0 0 LVDACK W Reset 5 0 0 = Unimplemented or Reserved 1 This bit can be written only one time after reset. Additional writes are ignored. Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1) Table 5-10.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.8 System Power Management Status and Control 2 Register (SPMSC2) This register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the MCU.
Chapter 6 Parallel Input/Output 6.1 Introduction This section explains software controls related to parallel input/output (I/O). The MC9S08GBxxA has seven I/O ports which include a total of 56 general-purpose I/O pins (one of these pins is output only). The MC9S08GTxxA has six I/O ports which include a total of up to 39 general-purpose I/O pins (one pin, PTG0, is output only). See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins.
Chapter 6 Parallel Input/Output IRQ IRQ LVD USER FLASH (Gx60A = 61,268 BYTES) (Gx32A = 32,768 BYTES) IIC MODULE (IIC1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 5-CHANNEL TIMER/PWM MODULE (TPM2) USER RAM (Gx60A = 4096 BYTES) (Gx32A = 2048 BYTES) 8 SCL1 SDA1 SCL1 SCL1 5 3 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 PTE3/MISO1 PTE2/SS1 PTE1/RxD1 PTE0/TxD1 PORT G EXTAL XTAL BKGD LOW-POWER OSCILLATOR PTB7/AD1P7– PTB0/AD1P0
Chapter 6 Parallel Input/Output 6.
Chapter 6 Parallel Input/Output Port A can be configured to be keyboard interrupt input pins. Refer to Chapter 9, “Keyboard Interrupt (S08KBIV1),” for more information about using port A pins as keyboard interrupts pins. 6.3.2 Port B and Analog to Digital Converter Inputs j Port B MCU Pin: Bit 7 6 5 4 3 2 1 Bit 0 PTB7/ AD1P7 PTB6/ AD1P6 PTB5/ AD1P5 PTB4/ AD1P4 PTB3/ AD1P3 PTB2/ AD1P2 PTB1/ AD1P1 PTB0/ AD1P0 Figure 6-3.
Chapter 6 Parallel Input/Output 6.3.4 Port D, TPM1 and TPM2 Port D MCU Pin: Bit 7 6 5 4 3 2 1 Bit 0 PTD7/ PTD6/ PTD5/ PTD4/ PTD3/ PTD2/ PTD1/ PTD0/ TPM2CH4 TPM2CH3 TPM2CH2 TPM2CH1 TPM2CH0 TPM1CH2 TPM1CH1 TPM1CH0 Figure 6-5. Port D Pin Names Port D is an 8-bit port shared with the two TPM modules, TPM1 and TPM2, and general-purpose I/O.
Chapter 6 Parallel Input/Output 6.3.6 Port F and High-Current Drivers Port F MCU Pin: Bit 7 6 5 4 3 2 1 Bit 0 PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 Figure 6-7. Port F Pin Names Port F is an 8-bit port general-purpose I/O that is not shared with any peripheral module. Port F has high current output drivers. Port F pins are available as general-purpose I/O pins controlled by the port F data (PTFD), data direction (PTFDD), pullup enable (PTFPE), and slew rate control (PTFSE) registers.
Chapter 6 Parallel Input/Output 6.4 Parallel I/O Controls Provided no on-chip peripheral is controlling a port pin, the pins operate as general-purpose I/O pins that are accessed and controlled by a data register (PTxD), a data direction register (PTxDD), a pullup enable register (PTxPE), and a slew rate control register (PTxSE) where x is A, B, C, D, E, F, or G. Reads of the data register return the pin value (if PTxDDn = 0) or the contents of the port data register (if PTxDDn = 1).
Chapter 6 Parallel Input/Output 6.5 Stop Modes Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An explanation of I/O behavior for the various stop modes follows: • When the MCU enters stop1 mode, all internal registers including general-purpose I/O control and data registers are powered down. All of the general-purpose I/O pins assume their reset state: output buffers and pullups turned off.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-9. Port A Data Register (PTAD) Table 6-1. PTAD Field Descriptions Field Description 7:0 PTAD[7:0] Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-11. Slew Rate Control Enable for Port A (PTASE) Table 6-3. PTASE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits PTASE[7:0] determine whether the slew rate controlled outputs are enabled.
Chapter 6 Parallel Input/Output 6.6.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as general-purpose I/O pins are controlled by the port B data (PTBD), data direction (PTBDD), pullup enable (PTBPE), and slew rate control (PTBSE) registers. If the ATD takes control of a port B pin, the corresponding PTBDD, PTBSE, and PTBPE bits are ignored.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-15. Data Direction for Port A (PTBSE) Table 6-7. PTBSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port B Bits — For port B pins that are outputs, these read/write control bits PTBSE[7:0] determine whether the slew rate controlled outputs are enabled.
Chapter 6 Parallel Input/Output 6.6.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) Port C includes eight general-purpose I/O pins that share with the SCI2 and IIC modules. Port C pins used as general-purpose I/O pins are controlled by the port C data (PTCD), data direction (PTCDD), pullup enable (PTCPE), and slew rate control (PTCSE) registers. If the SCI2 takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to provide slew rate on the SCI2 transmit pin, TxD2.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-18. Pullup Enable for Port C (PTCPE) Table 6-10. PTCPE Field Descriptions Field Description 7:0 Pullup Enable for Port C Bits — For port C pins that are inputs, these read/write control bits determine whether PTCPE[7:0] internal pullup devices are enabled.
Chapter 6 Parallel Input/Output 6.6.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) Port D includes eight pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as general-purpose I/O pins are controlled by the port D data (PTDD), data direction (PTDDD), pullup enable (PTDPE), and slew rate control (PTDSE) registers. If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-23. Slew Rate Control Enable for Port D (PTDSE) Table 6-15. PTDSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits PTDSE[7:0] determine whether the slew rate controlled outputs are enabled.
Chapter 6 Parallel Input/Output 6.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) Port E includes eight general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. If the SCI1 takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to provide slew rate on the SCI1 transmit pin, TxD1.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-26. Pullup Enable for Port E (PTEPE) Table 6-18. PTEPE Field Descriptions Field Description 7:0 Pullup Enable for Port E Bits — For port E pins that are inputs, these read/write control bits determine whether PTEPE[7:0] internal pullup devices are enabled.
Chapter 6 Parallel Input/Output 6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD) Port F includes eight general-purpose I/O pins that are not shared with any peripheral module. Port F pins used as general-purpose I/O pins are controlled by the port F data (PTFD), data direction (PTFDD), pullup enable (PTFPE), and slew rate control (PTFSE) registers. 7 6 5 4 3 2 1 0 PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-29.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-31. Slew Rate Control Enable for Port F (PTFSE) Table 6-23. PTFSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port F Bits — For port F pins that are outputs, these read/write control bits PTFSE[7:0] determine whether the slew rate controlled outputs are enabled.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-33. Port PTG Data Register (PTGD) Table 6-25. PTGD Field Descriptions Field Description 7:0 PTGD[7:0] Port PTG Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G pins that are configured as outputs, reads return the last value written to this register.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-35. Slew Rate Control Enable for Port G (PTGSE) Table 6-27. PTGSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits PTGSE[7:0] determine whether the slew rate controlled outputs are enabled.
Chapter 7 Internal Clock Generator (S08ICGV2) The MC9S08GBxxA/GTxxA microcontroller provides one internal clock generation (ICG) module to create the system bus frequency. All functions described in this section are available on the MC9S08GBxxA/GTxxA microcontroller. The EXTAL and XTAL pins share port G bits 2 and 1, respectively. Analog supply lines VDDA and VSSA are internally derived from the MCU’s VDD and VSS pins.
Chapter 7 Internal Clock Generator (S08ICGV2) IRQ RTI COP IRQ LVD USER FLASH (Gx60A = 61,268 BYTES) (Gx32A = 32,768 BYTES) ANALOG-TO-DIGITAL CONVERTER (10-BIT) (ATD1) IIC MODULE (IIC1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 5-CHANNEL TIMER/PWM MODULE (TPM2) USER RAM (Gx60A = 4096 BYTES) (Gx32A = 2048 BYTES) VDDAD VSSAD VREFH VREFL VSS 8 SCL1 SDA1 SCL1 SCL1 5 3 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 PTE3/MISO1 PTE
Internal Clock Generator (S08ICGV2) 7.1 Introduction Figure 7-3 is a top-level diagram that shows the functional organization of the internal clock generation (ICG) module. This section includes a general description and a feature list.
Internal Clock Generator (S08ICGV2) • Clock select block — The clock select block provides several switch options for connecting different clock sources to the system clock tree. ICGDCLK is the multiplied clock frequency out of the FLL, ICGERCLK is the reference clock frequency from the crystal or external clock source, and FFE (fixed frequency enable) is a control signal used to control the system fixed frequency clock (XCLK). ICGLCLK is the clock source for the background debug controller (BDC).
Internal Clock Generator (S08ICGV2) 7.1.2 Modes of Operation This is a high-level description only. Detailed descriptions of operating modes are contained in Section 7.3, “Functional Description.” • Mode 1 — Off The output clock, ICGOUT, is static. This mode may be entered when the STOP instruction is executed. • Mode 2 — Self-clocked (SCM) Default mode of operation that is entered out of reset.
Internal Clock Generator (S08ICGV2) pin is not used by the ICG. The oscillator is capable of being configured to provide a higher amplitude output for improved noise immunity. This mode of operation is selected by HGO = 1. 7.2.3 External Clock Connections If an external clock is used, then the pins are connected as shown in Figure 7-4. ICG EXTAL XTAL VSS NOT CONNECTED CLOCK INPUT Figure 7-4. External Clock Connections 7.2.
Internal Clock Generator (S08ICGV2) 7.3 Functional Description This section provides a functional description of each of the five operating modes of the ICG. Also covered are the loss of clock and loss of lock errors and requirements for entry into each mode. The ICG is very flexible, and in some configurations, it is possible to exceed certain clock specifications. When using the FLL, configure the ICG so that the frequency of ICGDCLK does not exceed its maximum value to ensure proper MCU operation. 7.
Internal Clock Generator (S08ICGV2) In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given by fICGDCLK / R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value into the filter registers (ICGFLTU and ICGFLTL). This is the only mode in which the filter registers can be written. If this mode is entered due to a reset, fICGDCLK will default to fSelf_reset which is nominally 8 MHz.
Internal Clock Generator (S08ICGV2) 7.3.3 FLL Engaged, Internal Clock (FEI) Mode FLL engaged internal (FEI) is entered when any of the following conditions occur: • CLKS bits are written to 01 • The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01 In FLL engaged internal mode, the reference clock is derived from the internal reference clock ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. 7.3.3.
Internal Clock Generator (S08ICGV2) In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO. The minimum multiplier for the FLL, from Table 7-7, is 4.
Internal Clock Generator (S08ICGV2) the off state. Because this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up from stop. Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the LOLS will not be set. 7.3.7 FLL Loss-of-Clock Detection The reference clock and the DCO clock are monitored under different conditions (see Table 7-1).
Internal Clock Generator (S08ICGV2) 7.3.8 Clock Mode Requirements A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should be the same as the requested mode in CLKS1:CLKS0. Table 7-2 shows the relationship between CLKS, CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS ≠ CLKST.
Internal Clock Generator (S08ICGV2) 7.3.9 Fixed Frequency Clock The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is equal to the internal bus clock, BUSCLK, in FBE mode. In FEE mode, XCLK is equal to ICGERCLK ÷ 2 when the following conditions are met: • (P × N) ÷ R ≥ 4 where P is determined by RANGE (see Table 7-4), N and R are determined by MFD and RFD, respectively (see Table 7-5). • LOCK = 1.
Internal Clock Generator (S08ICGV2) Table 7-3. ICG Configuration Consideration Clock Reference Source = Internal 1 Clock Reference Source = External FLL Engaged FEI 4 MHz < fBus < 20 MHz. Medium power (will be less than FEE if oscillator range = high) Medium clock accuracy (After IRG is trimmed) Lowest system cost (no external components required) IRG is on. DCO is on.
Internal Clock Generator (S08ICGV2) Table 7-5.
Internal Clock Generator (S08ICGV2) 7.4.2 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to 8.38 MHz to achieve 4.19 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (fBus). The clock scheme will be FLL engaged, external (FEE).
Internal Clock Generator (S08ICGV2) Figure 7-8 shows flow charts for three conditions requiring ICG initialization. RECOVERY FROM RESET, STIO1, STOP2 INITIALIZE ICG ICG1 = $38 ICG2 = $00 CHECK FLL LOCK STATUS. LOCK = 1? QUICK RECOVERY FROM STOP MINIMUM CURRENT DRAW IN STOP RECOVERY FROM STOP3 OSCSTEN = 1 RECOVERY FROM STOP3 OSCSTEN = 0 CHECK FLL LOCK STATUS. LOCK = 1? NO CHECK FLL LOCK STATUS.
Internal Clock Generator (S08ICGV2) ICGC2 = $30 (%00110000) Bit 7 Bit 6:4 Bit 3 Bit 2:0 LOLRE MFD LOCRE RFD 0 Generates an interrupt request on loss of lock 011 Sets the MFD multiplication factor to 10 0 Generates an interrupt request on loss of clock 000 Sets the RFD division factor to ÷1 ICGS1 = $xx This is read only except for clearing interrupt flag ICGS2 = $xx This is read only.
Internal Clock Generator (S08ICGV2) 7.4.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate) reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim function to fine tune the frequency based on an external reference signal.
Internal Clock Generator (S08ICGV2) RECOVERY FROM STOP3 RECOVERY FROM RESET, STOP1, STOP2 INITIALIZE ICG ICG1 = $28 ICG2 = $31 CHECK FLL LOCK STATUS. LOCK = 1? CHECK FLL LOCK STATUS. LOCK = 1? NO YES NO CONTINUE YES CONTINUE NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. Figure 7-10. ICG Initialization and Stop Recovery for Example #3 7.4.
Internal Clock Generator (S08ICGV2) Initial conditions: 1) Clock supplied from ATE has 500 μs duty period 2) ICG configured for internal reference with 4 MHz bus START TRIM PROCEDURE ICGTRM = $80, n = 1 MEASURE INCOMING CLOCK WIDTH (COUNT = # OF BUS CLOCKS / 4) COUNT < EXPECTED = 500 (RUNNING TOO SLOW) .
Internal Clock Generator (S08ICGV2) 7.5.1 ICG Control Register 1 (ICGC1) 7 6 5 HGO RANGE REFS 0 1 0 4 3 2 1 OSCSTEN LOCD 1 0 R 0 0 CLKS W Reset 0 0 0 = Unimplemented or Reserved Figure 7-12. ICG Control Register 1 (ICGC1) Table 7-6. ICGC1 Field Descriptions Field Description 7 HGO High Gain Oscillator Select — The HGO bit is used to select between low-power operation and high-amplitude operation. 0 Oscillator configured for low power operation.
Internal Clock Generator (S08ICGV2) 7.5.2 ICG Control Register 2 (ICGC2) 7 6 5 4 3 2 1 0 R LOLRE MFD LOCRE RFD W Reset 0 0 0 0 0 0 0 0 Figure 7-13. ICG Control Register 2 (ICGC2) Table 7-7. ICGC2 Field Descriptions Field Description 7 LOLRE Loss of Lock Reset Enable — The LOLRE bit determines what type of request is made by the ICG following a loss of lock indication. The LOLRE bit only has an effect when LOLS is set. 0 Generate an interrupt request on loss of lock.
Internal Clock Generator (S08ICGV2) 7.5.3 ICG Status Register 1 (ICGS1) 7 R 6 CLKST 5 4 3 2 1 0 REFST LOLS LOCK LOCS ERCS ICGIF W Reset 1 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-14. ICG Status Register 1 (ICGS1) Table 7-8. ICGS1 Field Descriptions Field Description 7:6 CLKST Clock Mode Status — The CLKST bits indicate the current clock mode.
Internal Clock Generator (S08ICGV2) 7.5.4 R ICG Status Register 2 (ICGS2) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DCOS 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 7-15. ICG Status Register 2 (ICGS2) Table 7-9. ICGS2 Field Descriptions Field Description 0 DCOS DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error has not changed by more than nunlock for two consecutive samples and the DCO clock is not static.
Internal Clock Generator (S08ICGV2) 7 6 5 4 3 2 1 0 0 0 0 0 R FLT W Reset 1 1 0 0 = Unimplemented or Reserved Figure 7-17. ICG Upper Filter Register (ICGFLTL) Table 7-11. ICGFLTL Field Descriptions Field Description 7:0 FLT Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00).
Chapter 8 Central Processor Unit (S08CPUV2) 8.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Chapter 8 Central Processor Unit (S08CPUV2) 8.2 Programmer’s Model and CPU Registers Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map. 0 7 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 0 SP STACK POINTER 15 X 0 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-1. CPU Registers 8.2.
Chapter 8 Central Processor Unit (S08CPUV2) 8.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
Chapter 8 Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-2. Condition Code Register Table 8-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
Chapter 8 Central Processor Unit (S08CPUV2) 8.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
Chapter 8 Central Processor Unit (S08CPUV2) 8.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 8.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 8.3.6.
Chapter 8 Central Processor Unit (S08CPUV2) 8.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
Chapter 8 Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence.
Chapter 8 Central Processor Unit (S08CPUV2) 8.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.
Chapter 8 Central Processor Unit (S08CPUV2) 8.5 HCS08 Instruction Set Summary Instruction Set Summary Nomenclature The nomenclature listed here is used in the instruction descriptions in Table 8-2.
Chapter 8 Central Processor Unit (S08CPUV2) 0 1 Þ U = = = = Bit forced to 0 Bit forced to 1 Bit set or cleared according to results of operation Undefined after the operation Machine coding notation dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00) ee = Upper 8 bits of 16-bit offset ff = Lower 8 bits of 16-bit offset or 8-bit offset ii = One byte of immediate data jj = High-order byte of a 16-bit immediate data value kk = Low-order byte of a 16-bit immediate data val
Chapter 8 Central Processor Unit (S08CPUV2) IX IX+ IX1 IX1+ = = = = IX2 REL SP1 SP2 = = = = 16-bit indexed no offset 16-bit indexed no offset, post increment (CBEQ and MOV only) 16-bit indexed with 8-bit offset from H:X 16-bit indexed with 8-bit offset, post increment (CBEQ only) 16-bit indexed with 16-bit offset from H:X 8-bit relative offset Stack pointer with 8-bit offset Stack pointer with 16-bit offset Operand Operation Opcode Effect on CCR IMM DIR EXT IX2 ¦ IX1 IX SP2 SP1 A9 B9 C9 D9 E9 F9
Chapter 8 Central Processor Unit (S08CPUV2) V H I N Z C DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – – DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd Bus Cycles1 Description Operand Operation Opcode Effect on CCR Source Form Address Mode Table 8-2.
Chapter 8 Central Processor Unit (S08CPUV2) V H I N Z C BRCLR n,opr8a,rel Branch if Bit n in Memory Clear Branch if (Mn) = 0 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – ¦ DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) BRN rel Branch Never Uses 3 Bus Cycles – – – – – – REL 21 rr Branch if (Mn) = 1 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – ¦ DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd dd dd dd dd dd dd dd Mn ← 1 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – – DIR DIR (b4) DIR (b5) DI
Chapter 8 Central Processor Unit (S08CPUV2) Operand IMM DIR EXT IX2 ¦ IX1 IX SP2 SP1 A3 B3 C3 D3 E3 F3 9ED3 9EE3 ii dd hh ll ee ff ff Description V H I N Z C CPX CPX CPX CPX CPX CPX CPX CPX #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP DAA DBNZ opr8a,rel DBNZA rel DBNZX rel DBNZ oprx8,X,rel DBNZ ,X,rel DBNZ oprx8,SP,rel DEC opr8a DECA DECX DEC oprx8,X DEC ,X DEC oprx8,SP DIV EOR EOR EOR EOR EOR EOR EOR EOR #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP INC opr8a INCA INCX
Chapter 8 Central Processor Unit (S08CPUV2) V H I N Z C LDX LDX LDX LDX LDX LDX LDX LDX #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP LSL opr8a LSLA LSLX LSL oprx8,X LSL ,X LSL oprx8,SP Load X (Index Register Low) from Memory Logical Shift Left (Same as ASL) LSR opr8a LSRA LSRX LSR oprx8,X LSR ,X LSR oprx8,SP Logical Shift Right MOV opr8a,opr8a MOV opr8a,X+ MOV #opr8i,opr8a MOV ,X+,opr8a Move MUL Unsigned multiply X ← (M) 0 – – ¦ C 0 b7 C H:X ← (H:X) + 0x0001 in IX+/DIR and DIR
Chapter 8 Central Processor Unit (S08CPUV2) V H I N Z C ROR opr8a RORA RORX ROR oprx8,X ROR ,X ROR oprx8,SP Rotate Right through Carry RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine SBC SBC SBC SBC SBC SBC SBC SBC #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP SEC SEI STA STA STA STA STA STA STA opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Subtract with Carry STOP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP SWI A ← (A) – (M) –
Chapter 8 Central Processor Unit (S08CPUV2) Description V H I N Z C TAP Transfer Accumulator to CCR CCR ← (A) TAX Transfer Accumulator to X (Index Register Low) TPA ¦ INH 84 1 X ← (A) – – – – – – INH 97 1 Transfer CCR to Accumulator A ← (CCR) – – – – – – INH 85 1 TST opr8a TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Test for Negative or Zero (M) – 0x00 (A) – 0x00 (X) – 0x00 (M) – 0x00 (M) – 0x00 (M) – 0x00 DIR INH ¦ – INH IX1 IX SP1 3D dd 4D 5D 6D ff 7D 9E6D ff 4 1 1 4 3 5 TSX Trans
Chapter 8 Central Processor Unit (S08CPUV2) Table 8-3.
Chapter 8 Central Processor Unit (S08CPUV2) Table 8-3.
Chapter 9 Keyboard Interrupt (S08KBIV1) 9.1 Introduction The MC9S08GBxxA/GTxxA has one KBI module with eight keyboard interrupt inputs that share port A pins. See Chapter 2, “Pins and Connections” for more information about the logic and hardware aspects of these pins. 9.1.1 Port A and Keyboard Interrupt Pins MCU Pin: PTA7/ KBI1P7 PTA6/ KBI1P6 PTA5/ KBI1P5 PTA4/ KBI1P4 PTA3/ KBI1P3 PTA2/ KBI1P2 PTA1/ KBI1P1 PTA0/ KBI1P0 Figure 9-1.
Chapter 9 Keyboard Interrupt (S08KBIV1) IRQ RTI COP IRQ LVD USER FLASH (Gx60A = 61,268 BYTES) (Gx32A = 32,768 BYTES) ANALOG-TO-DIGITAL CONVERTER (10-BIT) (ATD1) IIC MODULE (IIC1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 5-CHANNEL TIMER/PWM MODULE (TPM2) USER RAM (Gx60A = 4096 BYTES) (Gx32A = 2048 BYTES) VDDAD VSSAD VREFH VREFL VSS 8 SCL1 SDA1 SCL1 SCL1 5 3 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 PTE3/MISO1 PTE2/SS1
Keyboard Interrupt (S08KBIV1) 9.2.1 KBI Block Diagram Figure 9-3 shows the block diagram for a KBI module. KBI1P0 KBIPE0 VDD KBIPE3 0 S SYNCHRONIZER KBIPE4 KEYBOARD INTERRUPT FF STOP STOP BYPASS KEYBOARD INTERRUPT REQUEST KBIMOD 1 0 KBF CK KBEDG4 KBI1Pn RESET D CLR Q 1 KBI1P4 BUSCLK KBACK KBI1P3 S KBIE KBIPEn KBEDGn Figure 9-3. KBI Block Diagram 9.3 Register Definition This section provides information about all registers and control bits associated with the KBI module.
Keyboard Interrupt (S08KBIV1) 9.3.1 KBI Status and Control Register (KBI1SC) 7 6 5 4 KBEDG7 KBEDG6 KBEDG5 KBEDG4 R 3 2 KBF 0 W Reset 1 0 KBIE KBIMOD 0 0 KBACK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-4. KBI Status and Control Register (KBI1SC) Table 9-1.
Keyboard Interrupt (S08KBIV1) 9.3.2 KBI Pin Enable Register (KBI1PE) 7 6 5 4 3 2 1 0 KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0 0 0 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 9-5. KBI Pin Enable Register (KBI1PE) Table 9-2. KBI1PE Register Field Descriptions Field Description 7:0 KBIPE[7:0] 9.4 9.4.
Keyboard Interrupt (S08KBIV1) 9.4.3 KBI Interrupt Controls The KBF status flag becomes set (1) when an edge event has been detected on any KBI input pin. If KBIE = 1 in the KBI1SC register, a hardware interrupt will be requested whenever KBF = 1. The KBF flag is cleared by writing a 1 to the keyboard acknowledge (KBACK) bit. When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK.
Chapter 10 Timer/PWM (S08TPMV1) 10.1 Introduction The MC9S08GBxxA/GTxxA includes two independent timer/PWM (TPM) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM functions.
Chapter 10 Timer/PWM (S08TPMV1) IRQ RTI COP IRQ LVD USER FLASH (Gx60A = 61,268 BYTES) (Gx32A = 32,768 BYTES) ANALOG-TO-DIGITAL CONVERTER (10-BIT) (ATD1) IIC MODULE (IIC1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 5-CHANNEL TIMER/PWM MODULE (TPM2) USER RAM (Gx60A = 4096 BYTES) (Gx32A = 2048 BYTES) VDDAD VSSAD VREFH VREFL VSS 8 SCL1 SDA1 SCL1 SCL1 5 3 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 PTE3/MISO1 PTE2/SS1 PTE1/RxD
Timer/PWM (TPM) 10.3 TPM Block Diagram The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–4). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and Connections chapter for more information). Figure 10-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various numbers of channels.
Timer/PWM (TPM) counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned PWM functions. The timer counter modulo registers, TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values $0000 or $FFFF effectively make the counter free running.) Software can read the counter value at any time without affecting the counting sequence.
Timer/PWM (TPM) associated TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM mode. The following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM).
Timer/PWM (TPM) Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes are captured into a buffer so when the other byte is read, the value will represent the other byte of the count at the time the first byte was read. The counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read.
Timer/PWM (TPM) register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible. As Figure 10-3 shows, the output compare value in the TPM channel registers determines the pulse width (duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the pulse width.
Timer/PWM (TPM) generation of 100 percent duty cycle is not necessary). This is not a significant limitation because the resulting period is much longer than required for normal applications. TPMxMODH:TPMxMODL = $0000 is a special case that should not be used with center-aligned PWM mode.
Timer/PWM (TPM) 10.6 TPM Interrupts The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel. The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is configured for input capture, the interrupt flag is set each time the selected input capture edge is recognized.
Timer/PWM (TPM) 10.6.4 PWM End-of-Duty-Cycle Events For channels that are configured for PWM operation, there are two possibilities: • When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. • When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice during each PWM cycle.
Timer/PWM (TPM) 10.7.1 Timer x Status and Control Register (TPMxSC) TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module. 7 R 6 5 4 3 2 1 0 TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0 0 0 0 0 0 0 0 TOF W Reset 0 = Unimplemented or Reserved Figure 10-5. Timer x Status and Control Register (TPMxSC) Table 10-1.
Timer/PWM (TPM) Table 10-2. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 0:0 No clock selected (TPM disabled) 0:1 Bus rate clock (BUSCLK) 1:0 Fixed system clock (XCLK) 1:1 External source (TPMx Ext Clk)1,2 1. The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2.
Timer/PWM (TPM) When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 10.7.3 Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL) The read/write TPM modulo registers contain the modulo value for the TPM counter.
Timer/PWM (TPM) 10.7.4 Timer x Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 CHnF CHnIE MSnB MSnA ELSnB ELSnA 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 10-10. Timer x Channel n Status and Control Register (TPMxCnSC) Table 10-4.
Timer/PWM (TPM) Table 10-5.
Timer/PWM (TPM) In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPMxCnSC register is written. In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer.
Chapter 11 Serial Communications Interface (S08SCIV1) 11.1 Introduction The MC9S08GBxxA/GTxxA includes two independent serial communications interface (SCI) modules — sometimes called universal asynchronous receiver/transmitters (UARTs). Typically, these systems are used to connect to the RS232 serial input/output (I/O) port of a personal computer or workstation, and they can also be used to communicate with other embedded controllers.
Chapter 11 Serial Communications Interface (S08SCIV1) IRQ RTI COP IRQ LVD USER FLASH (Gx60A = 61,268 BYTES) (Gx32A = 32,768 BYTES) ANALOG-TO-DIGITAL CONVERTER (10-BIT) (ATD1) IIC MODULE (IIC1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 5-CHANNEL TIMER/PWM MODULE (TPM2) USER RAM (Gx60A = 4096 BYTES) (Gx32A = 2048 BYTES) VDDAD VSSAD VREFH VREFL VSS 8 SCL1 SDA1 SCL1 SCL1 5 3 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 PTE3/M
Serial Communications Interface (S08SCIV1) 11.1.
Serial Communications Interface (S08SCIV1) 11.1.3 Block Diagram Figure 11-2 shows the transmitter portion of the SCI. (Figure 11-3 shows the receiver portion of the SCI.
Serial Communications Interface (S08SCIV1) Figure 11-3 shows the receiver portion of the SCI.
Serial Communications Interface (S08SCIV1) 11.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names.
Serial Communications Interface (S08SCIV1) 11.2.2 SCI Control Register 1 (SCIxC1) This read/write register is used to control various optional features of the SCI system. 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 R W Reset Figure 11-6. SCI Control Register 1 (SCIxC1) Table 11-3. SCIxC1 Register Field Descriptions Field Description 7 LOOPS Loop Mode Select — Selects between loop back modes and normal 2-pin full-duplex modes.
Serial Communications Interface (S08SCIV1) 11.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 R W Reset Figure 11-7. SCI Control Register 2 (SCIxC2) Table 11-4. SCIxC2 Register Field Descriptions Field 7 TIE 6 TCIE Description Transmit Interrupt Enable (for TDRE) 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE flag is 1.
Serial Communications Interface (S08SCIV1) Table 11-4. SCIxC2 Register Field Descriptions (continued) Field Description 1 RWU Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wakeup).
Serial Communications Interface (S08SCIV1) Table 11-5. SCIxS1 Register Field Descriptions (continued) Field Description 5 RDRF Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data register (SCIxD). 0 Receive data register empty. 1 Receive data register full.
Serial Communications Interface (S08SCIV1) 11.2.5 SCI Status Register 2 (SCIxS2) This register has one read-only status flag. Writes have no effect. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RAF 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 11-9. SCI Status Register 2 (SCIxS2) Table 11-6.
Serial Communications Interface (S08SCIV1) Table 11-7. SCIxC3 Register Field Descriptions (continued) Field Description 3 ORIE Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1. 2 NEIE Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. 0 NF interrupts disabled (use polling).
Serial Communications Interface (S08SCIV1) 11.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
Serial Communications Interface (S08SCIV1) the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCIxD.
Serial Communications Interface (S08SCIV1) program has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles receive data. Refer to Section 11.3.
Serial Communications Interface (S08SCIV1) 11.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits).
Serial Communications Interface (S08SCIV1) When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD1 line remains idle for an extended period of time.
Serial Communications Interface (S08SCIV1) 11.3.5.3 Loop Mode When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD1 pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 11.3.5.
Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.1 Introduction The MC9S08GBxxA/GTxxA provides one serial peripheral interface (SPI) module. The four pins associated with SPI functionality are shared with port E pins 2–5. See the Appendix A, “Electrical Characteristics,” appendix for SPI electrical parametric information. When the SPI is enabled, the direction of pins is controlled by module configuration. If the SPI is disabled, all four pins can be used as general-purpose I/O.
Chapter 12 Serial Peripheral Interface (S08SPIV3) IRQ RTI COP IRQ LVD USER FLASH (Gx60A = 61,268 BYTES) (Gx32A = 32,768 BYTES) ANALOG-TO-DIGITAL CONVERTER (10-BIT) (ATD1) IIC MODULE (IIC1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 5-CHANNEL TIMER/PWM MODULE (TPM2) USER RAM (Gx60A = 4096 BYTES) (Gx32A = 2048 BYTES) VDDAD VSSAD VREFH VREFL VSS 8 SCL1 SDA1 SCL1 SCL1 5 3 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 PTE3/MISO1
Serial Peripheral Interface (S08SPIV3) 12.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 12.1.
Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 12-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 12.1.2.
Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPI1D) ENABLE SPI SYSTEM M SHIFT OUT SPI SHIFT REGISTER SHIFT IN MISO (SISO) S SPC0 Rx BUFFER (READ SPI1D) BIDIROE SHIFT DIRECTION LSBFE SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY MASTER CLOCK BUS RATE CLOCK SPIBR CLOCK GENERATOR MSTR CLOCK LOGIC SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODFEN SSOE MODE FAULT DETECTION SPRF SS SPTEF SPTIE MODF SPIE SPI INTERRUPT REQUEST
Serial Peripheral Interface (S08SPIV3) BUS CLOCK PRESCALER CLOCK RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 12-4. SPI Baud Rate Generation 12.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits.
Serial Peripheral Interface (S08SPIV3) 12.3 Modes of Operation 12.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
Serial Peripheral Interface (S08SPIV3) Table 12-1. SPI1C1 Field Descriptions (continued) Field Description 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 12.5.1, “SPI Clock Formats” for more details.
Serial Peripheral Interface (S08SPIV3) Table 12-3. SPI1C2 Register Field Descriptions Field Description 4 MODFEN Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 12-2 for more details).
Serial Peripheral Interface (S08SPIV3) Table 12-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 12-6. SPI Baud Rate Divisor 12.4.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPI1S) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Serial Peripheral Interface (S08SPIV3) Table 12-7. SPI1S Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPI1D). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
Serial Peripheral Interface (S08SPIV3) 12.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPI1D) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
Serial Peripheral Interface (S08SPIV3) MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ...
Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1).
Serial Peripheral Interface (S08SPIV3) 12.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF).
Serial Peripheral Interface (S08SPIV3) MC9S08GB60A Data Sheet, Rev.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1 Introduction The MC9S08GBxxA/GTxxA series of microcontrollers provides one inter-integrated circuit (IIC) module for communication with other integrated circuits. The two pins associated with this module, SDA1 and SCL1 share port C pins 2 and 3, respectively. All functionality as described in this section is available on MC9S08GBxxA/GTxxA. When the IIC is enabled, the direction of pins is controlled by module configuration.
Chapter 13 Inter-Integrated Circuit (S08IICV1) IRQ RTI COP IRQ LVD USER FLASH (Gx60A = 61,268 BYTES) (Gx32A = 32,768 BYTES) ANALOG-TO-DIGITAL CONVERTER (10-BIT) (ATD1) IIC MODULE (IIC1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 5-CHANNEL TIMER/PWM MODULE (TPM2) USER RAM (Gx60A = 4096 BYTES) (Gx32A = 2048 BYTES) VDDAD VSSAD VREFH VREFL VSS 8 SCL1 SDA1 SCL1 SCL1 5 3 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 PTE3/MISO1 PT
Inter-Integrated Circuit (S08IICV1) 13.1.
Inter-Integrated Circuit (S08IICV1) 13.1.3 Block Diagram Figure 13-2 is a block diagram of the IIC. ADDRESS DATA BUS INTERRUPT ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG INPUT SYNC START STOP ARBITRATION CONTROL CLOCK CONTROL IN/OUT DATA SHIFT REGISTER ADDRESS COMPARE SCL SDA Figure 13-2. IIC Functional Block Diagram 13.2 External Signal Description This section describes each user-accessible pin signal. 13.2.
Inter-Integrated Circuit (S08IICV1) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.3.
Inter-Integrated Circuit (S08IICV1) Table 13-2. IIC1F Register Field Descriptions Field Description 7:6 MULT IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved 5:0 ICR IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection.
Inter-Integrated Circuit (S08IICV1) Table 13-3.
Inter-Integrated Circuit (S08IICV1) 13.3.3 IIC Control Register (IIC1C) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-5. IIC Control Register (IIC1C) Table 13-4. IIC1C Register Field Descriptions Field Description 7 IICEN IIC Enable — The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled. 1 IIC is enabled.
Inter-Integrated Circuit (S08IICV1) 13.3.4 IIC Status Register (IIC1S) 7 R 6 TCF 5 4 BUSY IAAS 3 2 0 SRW ARBL 1 0 RXAK IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-6. IIC Status Register (IIC1S) Table 13-5. IIC1S Register Field Descriptions Field Description 7 TCF Transfer Complete Flag — This bit is set on the completion of a byte transfer.
Inter-Integrated Circuit (S08IICV1) 13.3.5 IIC Data I/O Register (IIC1D) 7 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset 0 0 0 0 Figure 13-7. IIC Data I/O Register (IIC1D) Table 13-6. IIC1D Register Field Descriptions Field Description 7:0 DATA Data — In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Inter-Integrated Circuit (S08IICV1) 13.4 Functional Description This section provides a complete functional description of the IIC module. 13.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
Inter-Integrated Circuit (S08IICV1) 13.4.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 13-8, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. 13.4.1.
Inter-Integrated Circuit (S08IICV1) 13.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 13-8).
Inter-Integrated Circuit (S08IICV1) DELAY START COUNTING HIGH PERIOD SCL1 SCL2 SCL INTERNAL COUNTER RESET Figure 13-9. IIC Clock Synchronization 13.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 13.4.1.
Inter-Integrated Circuit (S08IICV1) 13.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of byte transfer. 13.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register), the IAAS bit in the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 13.6.
Inter-Integrated Circuit (S08IICV1) 13.7 1. 2. 3. 4. 1. 2. 3. 4. 5. 6. 7.
Inter-Integrated Circuit (S08IICV1) Clear IICIF Master Mode ? Y TX N Y RX Tx/Rx ? Arbitration Lost ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y N Address Transfer Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 Generate Stop Signal (MST = 0) TX Y Set TX Mode RX TX/RX ? N (Write) N Data Transfer ACK from Receiver ? N Set RX Mode Swit
Inter-Integrated Circuit (S08IICV1) MC9S08GB60A Data Sheet, Rev.
Chapter 14 Analog-to-Digital Converter (S08ATDV3) The MC9S08GBxxA/GTxxA provides one 8-channel analog-to-digital (ATD) module. The eight ATD channels share port B. Each channel individually can be configured for general-purpose I/O or for ATD functionality. All features of the ATD module as described in this section are available on the MC9S08GBxxA/GTxxA. Electrical parametric information for the ATD may be found in Appendix A, “Electrical Characteristics.” MC9S08GB60A Data Sheet, Rev.
Chapter 14 Analog-to-Digital Converter (S08ATDV3) IRQ RTI COP IRQ LVD USER FLASH (Gx60A = 61,268 BYTES) (Gx32A = 32,768 BYTES) ANALOG-TO-DIGITAL CONVERTER (10-BIT) (ATD1) IIC MODULE (IIC1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 5-CHANNEL TIMER/PWM MODULE (TPM2) USER RAM (Gx60A = 4096 BYTES) (Gx32A = 2048 BYTES) VDDAD VSSAD VREFH VREFL VSS 8 SCL1 SDA1 SCL1 SCL1 5 3 SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SPSCK1 MOSI1 MISO1 SS1 RxD1 TxD1 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 PTE3/MISO1
Analog-to-Digital Converter (S08ATDV3) 14.1 Introduction The ATD module is an analog-to-digital converter with a successive approximation register (SAR) architecture with sample and hold. 14.1.1 • • • • • • • Features 8-/10-bit resolution 14.
Analog-to-Digital Converter (S08ATDV3) CONTROL INTERRUPT DATA JUSTIFICATION CONTROL AND STATUS REGISTERS ADDRESS R/W DATA RESULT REGISTERS SAR_REG <9:0> CTL VDD STATUS PRESCALER VSS BUSCLK CONVERSION MODE CLOCK PRESCALER CTL CONTROL BLOCK STATE MACHINE CONVERSION CLOCK DIGITAL ANALOG CTL POWERDOWN VREFH VREFL VSSAD SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER (ATD) BLOCK AD1P0 AD1P1 AD1P2 AD1P3 AD1P4 CONVERSION REGISTER VDDAD INPUT MUX AD1P5 AD1P6 AD1P7 = INTERNAL
Analog-to-Digital Converter (S08ATDV3) Table 14-1. Signal Properties 14.2.1.1 Name Function AD7–AD0 Channel input pins VREFH High reference voltage for ATD converter VREFL Low reference voltage for ATD converter VDDAD ATD power supply voltage VSSAD ATD ground supply voltage Channel Input Pins — AD1P7–AD1P0 The channel pins are used as the analog input pins of the ATD. Each pin is connected to an analog switch which serves as the signal gate into the sample submodule. 14.2.1.
Analog-to-Digital Converter (S08ATDV3) conversion to the mode control unit. For VREFL and VREFH, the SAR machine uses the reference potentials to set the sampled signal level within itself without relying on the S/H machine to deliver them. The mode control unit organizes the conversion, specifies the input sample channel, and moves the digital output data from the SAR register to the result register. The result register consists of a dual-port register.
Analog-to-Digital Converter (S08ATDV3) • • • • • ATD input capacitance (CAIN – maximum value 50 pF) — This is the internal capacitance of the ATD sample and hold circuit. This capacitance varies with temperature, voltage, and process variation but a worst case number is necessary to compute worst case sample error. ATD conversion clock frequency (fATDCLK – maximum value 2 MHz) — This is the frequency of the clock input to the ATD and is dependent on the bus clock frequency and the ATD prescaler.
Analog-to-Digital Converter (S08ATDV3) 14.3.3 Analog Input Multiplexer The analog input multiplexer selects one of the eight external analog input channels to generate an analog sample. The analog input multiplexer includes negative stress protection circuitry which prevents cross-talk between channels when the applied input potentials are within specification. Only analog input signals within the potential range of VREFL to VREFH (ATD reference potentials) will result in valid ATD conversions. 14.3.
Analog-to-Digital Converter (S08ATDV3) • Full scale error (EFS) — This is the difference between the transition voltage to the last valid code and the ideal transition to that code. Normally, it is defined as the difference between the actual and ideal transition to code 0x3FF, but in some cases the last transition may be to a lower code. The ideal transition to any code is: Eqn.
Analog-to-Digital Converter (S08ATDV3) CODE D C TOTAL UNADJUSTED ERROR BOUNDARY B A IDEAL TRANSFER FUNCTION 9 NEGATIVE DNL (CODE WIDTH <1LSB) 8 IDEAL STRAIGHT-LINE 7 TRANSFER FUNCTION QUANTIZATION ERROR 6 INL (ASSUMES EZS = EFS = 0) 5 1 LSB 4 TOTAL UNADJUSTED 3 ERROR AT THIS CODE 2 POSITIVE DNL 1 (CODE WIDTH >1LSB) 0 1 2 3 4 8 12 LSB NOTES: Graph is for example only and may not represent actual performance Figure 14-4. ATD Accuracy Definitions MC9S08GB60A Data Sheet, Rev.
Analog-to-Digital Converter (S08ATDV3) 14.4 Resets The ATD module is reset on system reset. If the system reset signal is activated, the ATD registers are initialized back to their reset state and the ATD module is powered down. This occurs as a function of the register file initialization; the reset definition of the ATDPU bit (power down bit) is zero or disabled. The MCU places the module back into an initialized state.
Analog-to-Digital Converter (S08ATDV3) 14.6.1 ATD Control (ATDC) Writes to the ATD control register will abort the current conversion, but will not start a new conversion. 7 6 5 4 ATDPU DJM RES8 SGN 0 0 0 0 3 2 1 0 0 0 R PRS W Reset 0 0 Figure 14-5. ATD Control Register (ATD1C) Table 14-3. ATD1C Field Descriptions Field Description 7 ATDPU ATD Power Up — This bit provides program on/off control over the ATD, reducing power consumption when the ATD is not being used.
Analog-to-Digital Converter (S08ATDV3) Table 14-4.
Analog-to-Digital Converter (S08ATDV3) Table 14-5.
Analog-to-Digital Converter (S08ATDV3) Table 14-6. ATD1SC Field Descriptions Field Description 7 CCF Conversion Complete Flag — The CCF is a read-only bit which is set each time a conversion is complete. The CCF bit is cleared whenever the ATD1SC register is written. It is also cleared whenever the result registers, ATD1RH or ATD1RL, are read. 0 Current conversion is not complete. 1 Current conversion is complete.
Analog-to-Digital Converter (S08ATDV3) 7 6 5 4 3 9 2 1 0 7 6 5 4 3 2 1 0 0 RESULT ATD1RH ATD1RL Figure 14-7. Left-Justified Mode For right-justified mode, result data bits 9 and 8 map onto bits 1 and 0 of ATD1RH, result data bits 7–0 map onto ATD1RL bits 7–0, where bit 1 of ATD1RH is the most significant bit (MSB). 7 6 5 4 3 2 1 0 7 6 9 5 4 3 2 0 0 RESULT ATD1RH 1 ATD1RL Figure 14-8.
Chapter 15 Development Support 15.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip flash and other nonvolatile memories.
Development Support 15.1.
Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system.
Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this Development Support section).
Development Support Figure 15-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges.
Development Support Figure 15-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles).
Development Support Figure 15-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
Development Support 15.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program.
Development Support Table 15-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
Development Support 15.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture.
Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port.
Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU.
Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match.
Development Support 15.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 15.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue.
Development Support 15.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 15-5.
Development Support Table 15-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 15-6. System Background Debug Force Reset Register (SBDFR) Table 15-3.
Development Support 15.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word.
Development Support 15.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 15-7. Debug Control Register (DBGC) Table 15-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
Development Support 15.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 15-8. Debug Trigger Register (DBGT) Table 15-5.
Development Support 15.4.3.9 Debug Status Register (DBGS) This is a read-only status register. R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 15-9. Debug Status Register (DBGS) Table 15-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming.
Appendix A Electrical Characteristics A.1 Introduction This section contains electrical and timing specifications. A.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section.
Appendix A Electrical Characteristics A.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design.
Appendix A Electrical Characteristics A.4 Electrostatic Discharge (ESD) Protection Characteristics Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
Appendix A Electrical Characteristics Table A-4. DC Characteristics (Sheet 2 of 3) (Temperature Range = –40 to 85°C Ambient) Symbol Min Typical1 Max Unit Low-voltage warning threshold — low range (VDD falling) (VDD rising) VLVWL 2.08 2.16 2.1 2.19 2.2 2.27 V Power on reset (POR) re-arm voltage(2) Mode = stop Mode = run and Wait VRearm 0.20 0.50 0.30 0.80 0.40 1.2 V Input high voltage (VDD > 2.3 V) (all digital inputs) VIH 0.70 × VDD — V Input high voltage (1.8 V ≤ VDD ≤ 2.
Appendix A Electrical Characteristics Table A-4. DC Characteristics (Sheet 3 of 3) (Temperature Range = –40 to 85°C Ambient) 2 3 4 5 6 7 8 Symbol dc injection current4, 5, 6, 7, 8 VIN < VSS , VIN > VDD Single pin limit Total MCU limit, includes sum of all stressed pins |IIC| Input capacitance (all non-supply pins)(2) CIn Typical1 Min Max Unit — — 0.2 5 mA mA — 7 pF Typicals are measured at 25°C. This parameter is characterized and not tested on each device.
Appendix A Electrical Characteristics TYPICAL VOL VS IOL AT VDD = 3.0 V 1.2 1 0.15 0.8 0.1 VOL (V) 0.6 VOL (V) TYPICAL VOL VS VDD 0.2 85°C 25°C –40°C 0.4 85°C, IOL = 2 mA 25°C, IOL = 2 mA –40°C, IOL = 2 mA 0.05 0.2 0 0 0 5 10 IOL (mA) 15 1 20 2 3 VDD (V) 4 Figure A-3. Typical Low-Side Driver (Sink) Characteristics (Ports A, B, D, E, and G) TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 85°C 25°C –40°C 0.6 0.4 0.2 0 0 85°C 25°C –40°C 0.3 VDD – VOH (V) VDD – VOH (V) 0.
Appendix A Electrical Characteristics A.6 Supply Current Characteristics Table A-5. Supply Current Characteristics Parameter Symbol Typical1 Max2 Temp. (°C) 1.1 mA 2.1 mA4 2.1 mA(4) 2.1 mA(4) 55 70 85 0.8 mA 1.8 mA(4) 1.8 mA(4) 1.8 mA(4) 55 70 85 6.5 mA 7.5 mA(4) 7.5 mA(4) 7.5 mA5 55 70 85 4.8 mA 5.8 mA(4) 5.8 mA(4) 5.8 mA(4) 55 70 85 25 nA 0.6 μA(4) 1.8 μA(4) 4.0 μA(5) 55 70 85 20 nA 500 nA(4) 1.5 μA(4) 3.3 μA(4) 55 70 85 550 nA 3.0 μA(4) 5.
Appendix A Electrical Characteristics Table A-5. Supply Current Characteristics (continued) Parameter Symbol VDD (V) Typical1 3 70 μA 55 70 85 2 60 μA 55 70 85 3 5 μA 55 70 85 2 5 μA 55 70 85 3 9 μA 55 70 85 LVI adder to stop3 (LVDSE = LVDE = 1) Adder to stop3 for oscillator enabled7 (OSCSTEN =1) Adder for loss-of-clock enabled 1 2 3 4 5 6 7 Max2 Temp. (°C) Typicals are measured at 25°C. See Table A-6 through Table A-9 for typical curves across voltage/temperature.
Appendix A Electrical Characteristics 18 16 14 12 20 MHz, ATDoff, FEE, 25°C IDD (mA) 10 20 MHz, ATDoff, FBE, 25°C 8 MHz, ATDoff, FEE, 25°C 8 8 MHz, ATDoff, FBE, 25°C 1 MHz, ATDoff, FEE, 25°C 6 1 MHz, ATDoff, FBE, 25°C 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.8 VDD (Vdc) Figure A-6. Typical Run IDD for FBE and FEE Modes, IDD vs VDD 1200 STOP1 IDD (nA) 1000 800 25°C 70°C 600 85°C 400 200 0 1.5 2 2.5 3 3.5 4 VDD (V) NOTES: 1.
Appendix A Electrical Characteristics 4 3.5 STOP2 IDD (μA) 3 2.5 25°C 2 70°C 85°C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 VDD (V) NOTES: 1. Clock sources and LVD are all disabled (OSCSTEN = LVDSE = 0). 2. All I/O are set as outputs and driven to VSS with no load. Figure A-8. Typical Stop 2 IDD 8 7 STOP3 IDD (μA) 6 5 25°C 4 70°C 85°C 3 2 1 0 1.5 2 2.5 3 3.5 4 VDD (V) NOTES: 1. Clock sources and LVD are all disabled (OSCSTEN = LVDSE = 0). 2.
Appendix A Electrical Characteristics A.7 ATD Characteristics Table A-6. ATD Electrical Characteristics (Operating) No. Characteristic 1 ATD supply1 2 ATD supply current Condition Symbol Min Typ Max Unit VDDAD 1.80 — 3.6 V Enabled IDDADrun — 0.7 1.2 mA Disabled (ATDPU = 0 or STOP) IDDADstop — 0.02 0.
Appendix A Electrical Characteristics Table A-7. ATD Timing/Performance Characteristics1 (continued) No. Characteristic Condition Symbol Min Typ Max Unit 9 Zero-scale error8 1.80V < VDDAD < 3.6V EZS — +0.4 +1.0 LSB 10 Full-scale error9 1.80V < VDDAD < 3.6V EFS — +0.4 +1.0 LSB 11 Input leakage error 10 1.80V < VDDAD < 3.6V EIL — +0.05 +5 LSB 12 Total unadjusted error11 1.80V < VDDAD < 3.6V ETU — +1.1 +2.
Appendix A Electrical Characteristics A.8 Internal Clock Generation Module Characteristics ICG EXTAL XTAL RS RF C1 Crystal or Resonator (See Note) C2 NOTE: Use fundamental mode crystal or ceramic resonator only. Table A-8.
Appendix A Electrical Characteristics A.8.1 ICG Frequency Specifications Table A-9. ICG Frequency Specifications (VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 85°C Ambient) Characteristic Symbol Min Typical Max Unit flo 32 — 100 kHz fhi_byp fhi_eng flp_byp flp_eng 1 2 1 2 — — — — 16 10 10 10 MHz MHz MHz MHz flo fhi_eng 32 2 — — 100 10 kHz MHz fExtal 0 — 40 MHz fICGIRCLK 182.25 243 303.
Appendix A Electrical Characteristics 1 2 3 4 5 6 7 8 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it is not in the desired range. Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if an external reference exists) if it is not in the desired range.
Appendix A Electrical Characteristics A.9.1 Control Timing Table A-10. Control Timing Parameter Symbol Min Typical Max Unit Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz Real-time interrupt internal oscillator period tRTI 700 1300 μs External reset pulse width1 textrst 1.
Appendix A Electrical Characteristics tILIH IRQ Figure A-13. IRQ Timing A.9.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-11.
Appendix A Electrical Characteristics A.9.3 SPI Timing Table A-12 and Figure A-16 through Figure A-19 describe the timing requirements for the SPI system. Table A-12. SPI Timing No.
Appendix A Electrical Characteristics SS1 (OUTPUT) 11 1 2 SCK (CPOL = 0) (OUTPUT) 3 4 4 12 SCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN2 BIT 6 . . . 1 LSB IN 10 9 9 MOSI (OUTPUT) MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-16.
Appendix A Electrical Characteristics SS (INPUT) 1 12 11 11 12 3 SCK (CPOL = 0) (INPUT) 2 4 4 SCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) MSB OUT SLAVE BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 6 5 MOSI (INPUT) 10 10 9 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure A-18.
Appendix A Electrical Characteristics A.10 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, “Memory.” Table A-13.
Appendix A Electrical Characteristics MC9S08GB60A Data Sheet, Rev.
Appendix B EB652: Migrating from the GB60 Series to the GB60A Series The following text was taken from Freescale Semiconductor document EB652. It is copied here for your conveninece. Please see EB652 at freescale.com for the must up-to-date information regarding “Migrating from the GB60 series to the GB60A series.” B.
Appendix B EB652: Migrating from the GB60 Series to the GB60A Series improved noise immunity in the oscillator circuit. The low-power oscillator is also available for power-sensitive applications. This new oscillator option available on the GB60A series is selected by a new control bit in the ICG control register 1 (ICGC1): the HGO bit. HGO is bit 7 of the ICGC1 register, formerly an unimplemented bit that always read ‘0’.
Appendix B EB652: Migrating from the GB60 Series to the GB60A Series B.7 System Device Identification Register The system device identification register (SDIR) is a 16-bit value that contains a 12-bit part identification number and a 4-bit mask revision number. Both the GB60 series and the GB60A series have the same part identification number, $002. The mask revision number for the last production version of the GB60 series is $4. The first mask revision number for the GB60A series is $8.
Appendix B EB652: Migrating from the GB60 Series to the GB60A Series MC9S08GB60A Data Sheet, Rev.
Appendix C Ordering Information and Mechanical Drawings C.1 Ordering Information This section contains ordering numbers for MC9S08GB60A, MC9S08GB32A, MC9S08GT60A, and MC9S08GT32A devices. See below for an example of the device numbering system. Table C-1.
Appendix C C.2 Ordering Information and Mechanical Drawings Mechanical Drawings The following pages are mechanical drawings for the packages provided in Table C-2. MC9S08GB60A Data Sheet, Rev.
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