MC9S08GT16A MC9S08GT8A Data Sheet HCS08 Microcontrollers MC9S08GT16A Rev. 1 7/2006 freescale.
MC9S08GT16A/GT8A Features 8-Bit HCS08 Central Processor Unit (CPU) • • • 40-MHz HCS08 CPU HC08 instruction set with added BGND instruction Support for up to 32 interrupt/reset sources • • • Memory Options • • FLASH read/program/erase down to 1.
MC9S08GT16A/GT8A Data Sheet Covers: MC9S08GT16A MC9S08GT8A MC9S08GT16A Rev. 1 7/2006 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006. All rights reserved.
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Revision Number Revision Date 1 07/17/2006 Description of Changes Initial public release © Freescale Semiconductor, Inc., 2006. All rights reserved.
List of Chapters Chapter 1 Device Overview ...................................................................... 19 Chapter 2 Pins and Connections ............................................................. 23 Chapter 3 Modes of Operation ................................................................. 33 Chapter 4 Memory ..................................................................................... 41 Chapter 5 Resets, Interrupts, and System Configuration .....................
Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 Introduction .....................................................................................................................................19 1.1.1 Devices in the MC9S08GT16A/GT8A Series ..................................................................19 1.1.2 MCU Block Diagram ........................................................................................................19 System Clock Distribution ..................
Section Number Title Page Chapter 4 Memory 4.1 4.2 4.3 4.4 4.5 4.6 MC9S08GT16A/GT8A Memory Map ............................................................................................41 4.1.1 Reset and Interrupt Vector Assignments ...........................................................................42 Register Addresses and Bit Assignments ........................................................................................43 RAM ............................................................
Section Number 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6 5.7.7 5.7.8 Title Page Interrupt Pin Request Status and Control Register (IRQSC) ............................................71 System Reset Status Register (SRS) .................................................................................72 System Background Debug Force Reset Register (SBDFR) ............................................73 System Options Register (SOPT) ................................................................................
Section Number 7.3 Title Page 7.2.2 KBI Pin Enable Register (KBIPE) ..................................................................................103 Functional Description ..................................................................................................................103 7.3.1 Pin Enables ......................................................................................................................103 7.3.2 Edge and Level Sensitivity .........................................
Section Number Title Page Chapter 9 Internal Clock Generator (S08ICGV4) 9.1 9.2 9.3 9.4 9.5 Introduction ...................................................................................................................................125 9.1.1 Features ...........................................................................................................................127 9.1.2 Modes of Operation .................................................................................................
Section Number Title Page Chapter 10 Timer/PWM (S08TPMV2) 10.1 Introduction ...................................................................................................................................153 10.1.1 Features ...........................................................................................................................153 10.1.2 Features ...........................................................................................................................155 10.1.
Section Number Title Page 11.3 Functional Description ..................................................................................................................181 11.3.1 Baud Rate Generation .....................................................................................................181 11.3.2 Transmitter Functional Description ................................................................................181 11.3.2.1 Send Break and Queued Idle ..........................................
Section Number Title Page 12.6.1 SPI Module Initialization Example .................................................................................201 12.6.1.1 Initialization Sequence ..................................................................................201 12.6.1.2 Pseudo—Code Example ...............................................................................202 Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1 Introduction ............................................................
Section Number 14.2 14.3 14.4 14.5 14.6 Title Page 14.1.2.2 Power Down Mode .......................................................................................223 14.1.3 Block Diagram ................................................................................................................223 External Signal Description ..........................................................................................................224 14.2.1 ADP7–ADP0 — Channel Input Pins .........................
Section Number 15.4.3.2 15.4.3.3 15.4.3.4 15.4.3.5 15.4.3.6 15.4.3.7 15.4.3.8 15.4.3.9 Title Page Debug Comparator A Low Register (DBGCAL) .........................................254 Debug Comparator B High Register (DBGCBH) .........................................254 Debug Comparator B Low Register (DBGCBL) ..........................................254 Debug FIFO High Register (DBGFH) ..........................................................255 Debug FIFO Low Register (DBGFL) ........................
Chapter 1 Device Overview 1.1 Introduction The MC9S08GT16A/GT8A are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types (see Table 1-1). 1.1.1 Devices in the MC9S08GT16A/GT8A Series Table 1-1 lists the devices available in the MC9S08GT16A/GT8A series and summarizes the differences among them. Table 1-1.
VREFL VREFH VSSAD VDDAD Device Overview BKGD 8 4 4 COP IRQ LVD SCL SDA INTER-IC (IIC) RXD2 TXD2 SERIAL COMMUNICATIONS INTERFACE (SCI2) USER FLASH (GT16A = 16,384 BYTES) (GT8A = 8192 BYTES) USER RAM (GT16A = 2048 BYTES) (GT8A = 1024 BYTES) ON-CHIP ICE DEBUG MODULE (DBG) CH1 CH0 2-CHANNEL TIMER/PWM (TPM2) 3-CHANNEL TIMER/PWM (TPM1) CH0 CH1 CH2 SERIAL PERIPHERAL INTERFACE (SPI) SPSCK MOSI MISO SS SERIAL COMMUNICATIONS INTERFACE (SCI1) RXD1 TXD1 VDD VSS VSS VOLTAGE REGULATOR PTB7/ADP7– P
Device Overview Table 1-2 lists the functional versions of the on-chip modules. Table 1-2. Block Versions 1.
Device Overview Some of the modules inside the MCU have clock source choices. Figure 1-2 shows a simplified clock connection diagram. The ICG supplies the clock sources: • ICGOUT is an output of the ICG module. It is one of the following: — The external crystal oscillator — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module Control bits inside the ICG determine which source is connected.
Chapter 2 Pins and Connections 2.1 Introduction This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. PTA2/KBIP2 37 PTA4/KBIP4 39 38 PTA3/KBIP3 PTA5/KBIP5 40 41 PTA6/KBIP6 42 PTA7/KBIP7 VDDAD 44 VSSAD 45 PTG0/BKGD/MS 46 PTG1/XTAL 43 RESET 1 47 PTG2/EXTAL Device Pin Assignment 48 PTG3 2.
PTA3/KBIP3 PTA2/KBIP2 34 PTA6/KBIP6 38 35 PTA7/KBIP7 39 PTA4/KBIP4 VDDAD 40 36 VSSAD 41 PTA5/KBIP5 PTG0/BKGD/MS 42 37 PTG1/XTAL 43 PTB6/ADP6 PTC5 7 27 PTB5/ADP5 PTC6 8 26 PTB4/ADP4 PTE0/TxD1 9 25 PTB3/ADP3 PTE1/RxD1 10 24 PTB2/ADP2 23 PTB1/ADP1 IRQ 11 22 28 PTB0/ADP0 6 21 PTC4 PTD4/TPM2CH1 PTB7/ADP7 20 29 PTD3/TPM2CLK/TPM2CH0 5 19 PTC3/SCL PTD1/TPM1CH1 VREFH 18 30 PTD0/TPM1CLK/TPM1CH0 4 17 PTC2/SDA VDD VREFL 16 31 VSS 3 15 PTC1/RxD2 PTE5/SPSCK
Pins and Connections VDDAD 1 42 PTA7/KBIP7 VSSAD 2 41 PTA6/KBIP6 PTG0/BKGD/MS 3 40 PTA5/KBIP5 PTG1/XTAL 4 39 PTA4/KBIP4 PTG2/EXTAL 5 38 PTA3/KBIP3 RESET 6 37 PTA2/KBIP2 PTC0/TxD2 7 36 PTA1/KBIP1 PTC1/RXD2 8 35 PTA0/KBIP0 PTC2/SDA 9 34 VREFL PTC3/SCL 10 33 VREFH PTC4 11 32 PTB7/ADP7 PTE0/TxD1 12 31 PTB6/ADP6 PTE1/RxD1 13 30 PTB5/ADP5 IRQ 14 29 PTB4/ADP4 PTE2/SS 15 28 PTB3/ADP3 PTE3/MISO 16 27 PTB2/ADP2 PTE4/MOSI 17 26 PTB1/ADP1 PTE5/SPSCK
PTG2/EXTAL PTG1/XTAL PTG0/BKGD VSSAD VDDAD PTA7/KBIP7 PTA6/KBIP6 PTA5/KBIP5 Pins and Connections 32 31 30 29 28 27 26 25 24 PTA4/KBIP4 RESET 1 PTC0/TxD2 2 23 VREFL PTC1/RxD2 3 22 VREFH PTC2/SDA 4 21 PTB3/ADP3 PTC3/SCL 5 20 PTB2/ADP2 PTE0/TxD1 6 19 PTE1/RxD1 7 18 PTB0/ADP0 PTB1/ADP1 17 PTD3/TPM2CLK/TPM2CH0 9 10 11 12 13 14 15 16 PTE2/SS PTE3/MISO PTE4/MOSI PTE5/SPSCK VSS VDD PTD0/TPM1CLK/TPM1CH0 PTD1/TPM1CH1 IRQ 8 Figure 2-4.
Pins and Connections 2.3 Recommended System Connections Figure 2-5 shows pin connections that are common to almost all MC9S08GT16A application systems. A more detailed discussion of system connections follows. VREFH CBYAD 0.1 µF + 3V CBLK + 10 µF PTA1/KBIP1 MC9S08GT16A PTA2/KBIP2 VSSAD VREFL VDD VDD SYSTEM POWER VDDAD PTA0/KBIP0 PORT A PTA3/KBIP3 PTA4/KBIP4 PTA5/KBIP5 PTA6/KBIP6 CBY 0.
Pins and Connections 2.3.1 VDD, VSS, VDDAD, VSSAD, VREFH, VREFL — Power and Voltage References VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins.
Pins and Connections C1 and C2 are typically in the 5-pF to 25-pF range and are chosen to match the requirements of a specific crystal or resonator. Be sure to take into account printed circuit board (PCB) capacitance and MCU pin capacitance when sizing C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2 which are usually the same size.
Pins and Connections 2.3.5 IRQ — External Interrupt Request Pin IRQ is a dedicated pin with both pullup and pulldown devices built in. This pin has no output capabilities. After a system reset, the IRQ pin is disabled and must be enabled before use. See Section 5.4.2, “IRQ — External Interrupt Request Pin” for more details. For EMC-sensitive applications, an external RC filter is recommended on the IRQ pin. See Figure 2-5 for an example. 2.3.
Pins and Connections When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pin’s output buffer. See Chapter 6, “Parallel Input/Output,” for details.
Pins and Connections Table 2-2.
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08GT16A/GT8A are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.1.1 • • • 3.
Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.
Modes of Operation 3.5 Stop Modes One of three stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system option register is set. In all stop modes, all internal clocks are halted. If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter any of the stop modes and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
Modes of Operation Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped registers they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2, these values can be restored by user software before pin latches are opened. When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the RAM.
Modes of Operation and this 1-kHz source are disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case the real-time interrupt cannot wake the MCU from stop. 3.5.4 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This register is described in the Chapter 15, “Development Support,” section of this data sheet.
Modes of Operation 3.5.6 On-Chip Peripheral Modules in Stop Modes When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.5.1, “Stop1 Mode,” Section 3.5.2, “Stop2 Mode,” and Section 3.5.3, “Stop3 Mode,” for specific information on system behavior in stop modes.
Modes of Operation IIC — When the MCU enters stop mode, the clocks to the IIC module stops. The module halts operation. If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. MC9S08GT16A/GT8A Data Sheet, Rev.
Modes of Operation MC9S08GT16A/GT8A Data Sheet, Rev.
Chapter 4 Memory 4.1 MC9S08GT16A/GT8A Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08GT16A/GT8A series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers.
Memory 4.1.1 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08GT16A/GT8A. For more details about resets, interrupts, interrupt priority, and local interrupt mask controls, refer to Chapter 5, “Resets, Interrupts, and System Configuration.” Table 4-1.
Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08GT16A/GT8A are divided into these three groups: • Direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables.
Memory Table 4-2.
Memory Table 4-2.
Memory Table 4-2.
Memory Table 4-3.
Memory only way to disengage security is by mass erasing the FLASH if needed (normally through the background debug interface) and verifying that FLASH is blank. To avoid returning to secure mode after the next reset, program the security bits (SEC01:SEC00) to the unsecured state (1:0). 4.3 RAM The MC9S08GT16A/GT8A includes static RAM.
Memory • • • 4.4.2 Flexible block protection Security feature for FLASH and RAM Auto power-down for low-frequency read accesses Program and Erase Times Before any program or erase command can be accepted, the FLASH clock divider register (FCDIV) must be written to set the internal clock for the FLASH module to a frequency (fFCLK) between 150 kHz and 200 kHz (see Table 4.6.1). This register can be written only once, so normally this write is done during reset initialization.
Memory NOTE Do not program any byte in the FLASH more than once after a successful erase operation. Reprogramming bits in a byte which is already programmed is not allowed without first erasing the page in which the byte resides or mass erasing the entire FLASH memory. Programming without first erasing may disturb data stored in the FLASH. 2. Write the command code for the desired command to FCMD.
Memory WRITE TO FCDIV (Note 1) Note 1: Required only once after reset. START FACCERR ? 0 1 CLEAR ERROR WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) FPVIOL OR FACCERR ? Note 2: Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NO 0 FCCF ? 1 DONE Figure 4-2. FLASH Program and Erase Flowchart 4.4.
Memory program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. This is because the high voltage to the array must be disabled and then enabled again. If a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. Note 1: Required only once after reset.
Memory 4.4.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
Memory NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xDE must be programmed into NVPROT to protect addresses 0xE000 through 0xFFFF. FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 A15 A14 A13 A12 A11 A10 A9 1 1 1 1 1 1 1 1 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 4-4. Block Protection Mechanism One use for block protection is to block protect an area of FLASH memory for a bootloader program.
Memory makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure.
Memory 4.6 Register Definition The FLASH module has registers in the high-page register space, three locations in the nonvolatile register space in FLASH memory that are copied into three corresponding high-page control registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and Table 4-4 for the absolute address assignments for all FLASH registers. This section refers to registers and control bits only by their names.
Memory Table 4-7. FLASH Clock Divider Settings 4.6.2 fBus PRDIV8 (Binary) DIV5:DIV0 (Decimal) fFCLK Program/Erase Timing Pulse (5 µs Min, 6.7 µs Max) 20 MHz 1 12 192.3 kHz 5.2 µs 10 MHz 0 49 200 kHz 5 µs 8 MHz 0 39 200 kHz 5 µs 4 MHz 0 19 200 kHz 5 µs 2 MHz 0 9 200 kHz 5 µs 1 MHz 0 4 200 kHz 5 µs 200 kHz 0 0 200 kHz 5 µs 150 kHz 0 0 150 kHz 6.
Memory Table 4-8. FOPT Field Descriptions (continued) Field Description 6 FNORED Vector Redirection Disable — When this bit is 1, vector redirection is disabled. 0 Vector redirection enabled. 1 Vector redirection disabled. 1:0 SEC0[1:0] Security State Code — This 2-bit field determines the security state of the MCU as shown below. When the MCU is secure, the contents of RAM and FLASH memory cannot be accessed by instructions from any unsecured source including the background debug interface.
Memory 7 6 5 4 3 2 1 0 R FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS W Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) Note (1) Reset This register is loaded from nonvolatile location NVPROT during reset. Figure 4-8. FLASH Protection Register (FPROT) 1 Background commands can be used to change the contents of these bits in FPROT. Table 4-10.
Memory Table 4-11. FSTAT Field Descriptions (continued) Field Description 5 FPVIOL Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to FPVIOL. 0 No protection violation. 1 An attempt was made to erase or program a protected location.
Memory Table 4-13. FLASH Commands Command FCMD Equate File Label Blank check 0x05 mBlank Byte program 0x20 mByteProg Byte program — burst mode 0x25 mBurstProg Page erase (512 bytes/page) 0x40 mPageErase Mass erase (all FLASH) 0x41 mMassErase All other command codes are illegal and generate an access error. It is not necessary to perform a blank check command after a mass erase operation. Blank check is required only as part of the security unlocking mechanism.
Memory MC9S08GT16A/GT8A Data Sheet, Rev.
Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08GT16A/GT8A. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data manual. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Resets, Interrupts, and System Configuration • • • • • • Computer operating properly (COP) watchdog timer Illegal opcode detect Illegal address detect Background debug forced reset The reset pin (RESET) Clock generator loss of lock and loss of clock reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register.
Resets, Interrupts, and System Configuration If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The CPU will not respond until and unless the local interrupt enable is set to 1 to enable the interrupt. The I bit in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset, which masks (prevents) all maskable interrupt sources.
Resets, Interrupts, and System Configuration UNSTACKING ORDER TOWARD LOWER ADDRESSES 7 0 SP AFTER INTERRUPT STACKING 5 1 CONDITION CODE REGISTER 4 2 ACCUMULATOR 3 3 INDEX REGISTER (LOW BYTE X)* 2 4 PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW STACKING ORDER SP BEFORE THE INTERRUPT TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1.
Resets, Interrupts, and System Configuration 5.4.2.2 Edge and Level Sensitivity The IRQMOD control bit re-configures the detection logic so it detects edge events and pin levels. In this edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level. 5.4.
Resets, Interrupts, and System Configuration Table 5-1.
Resets, Interrupts, and System Configuration 5.5 Low-Voltage Detect (LVD) System The MC9S08GT16A/GT8A includes a system to protect against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system comprises a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (VLVDH) or low (VLVDL). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected by LVDV in SPMSC2.
Resets, Interrupts, and System Configuration When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and configured for low bandwidth operation (RANGE = 0). The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control value (RTIS2:RTIS1:RTIS0) used to select one of seven RTI periods. The RTI has a local interrupt enable, RTIE, to allow masking of the real-time interrupt.
Resets, Interrupts, and System Configuration 5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes two unimplemented bits which always read 0, four read/write bits, one read-only status bit, and one write-only bit. These bits are used to configure the IRQ function, report status, and acknowledge IRQ events. R 7 6 0 0 5 4 IRQEDG IRQPE 3 2 IRQF 0 W Reset 1 0 IRQIE IRQMOD 0 0 IRQACK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-2.
Resets, Interrupts, and System Configuration 5.7.2 System Reset Status Register (SRS) This register includes six read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset.
Resets, Interrupts, and System Configuration Table 5-3. SRS Field Descriptions (continued) Field 3 ILAD Description Illegal Address — Reset was caused by an attempt to access a designated illegal address. 0 Reset not caused by an illegal address access. 1 Reset caused by an illegal address access.
Resets, Interrupts, and System Configuration 5.7.4 System Options Register (SOPT) This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings.
Resets, Interrupts, and System Configuration 5.7.5 System Device Identification Register (SDIDH, SDIDL) This read-only register is included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU. 7 6 5 4 R 3 2 1 0 ID11 ID10 ID9 ID8 0 0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 5-6.
Resets, Interrupts, and System Configuration 5.7.6 System Real-Time Interrupt Status and Control Register (SRTISC) This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay selects, and three unimplemented bits, which always read 0. R 7 6 RTIF 0 W 5 4 RTICLKS RTIE 0 0 3 2 1 0 RTIS2 RTIS1 RTIS0 0 0 0 0 RTIACK Reset 0 0 0 = Unimplemented or Reserved Figure 5-8. System RTI Status and Control Register (SRTISC) Table 5-8.
Resets, Interrupts, and System Configuration 5.7.7 R System Power Management Status and Control 1 Register (SPMSC1) 7 6 LVDF 0 W Reset 5 4 3 2 1 0 LVDRE Note (1) LVDSE Note (1) LVDE Note (1) 0 0 LVDIE 0 1 1 1 0 0 LVDACK 0 0 = Unimplemented or Reserved 1 This bit can be written only one time after reset. Additional writes are ignored. Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1) Table 5-10.
Resets, Interrupts, and System Configuration 5.7.8 System Power Management Status and Control 2 Register (SPMSC2) This register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the MCU.
Chapter 6 Parallel Input/Output 6.1 Introduction This section explains software controls related to parallel input/output (I/O). The MC9S08GT16A/GT8A has six I/O ports which include a total of up to 39 general-purpose I/O pins (one pin, PTG0, is output only). See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins. Many of these pins are shared with on-chip peripherals such as timer systems, external interrupts, or keyboard interrupts.
Parallel Input/Output • • • • • Eight port B pins shared with ATD Eight high-current port C pins shared with SCI2 and IIC Five port D pins shared with TPM1 and TPM2 Six port E pins shared with SCI1 and SPI Four port G pins shared with EXTAL, XTAL, and BKGD/MS MC9S08GT16A/GT8A Data Sheet, Rev.
Parallel Input/Output Block Diagram VREFL VREFH VSSAD VDDAD 6.1.
Parallel Input/Output 6.2 External Signal Description The MC9S08GT16A/GT8A has a total of 39 parallel I/O pins (one is output only) in six 8-bit ports (PTA–PTE, PTG). Not all pins are bonded out in all packages. Consult the pin assignment in Chapter 2, “Pins and Connections,” for available parallel I/O pins. All of these pins are available for general-purpose I/O when they are not used by other on-chip peripheral systems.
Parallel Input/Output 6.2.3 Port C and SCI2, IIC, and High-Current Drivers Port C MCU Pin: Bit 7 6 5 3 3 2 1 Bit 0 PTC7 PTC6 PTC5 PTC4 PTC3/ SCL PTC2/ SDA PTC1/ RxD2 PTC0/ TxD2 Figure 6-4. Port C Pin Names Port C is an 8-bit port which is shared among the SCI2 and IIC modules, and general-purpose I/O. When SCI2 or IIC modules are enabled, the pin direction will be controlled by the module or function. Port C has high current output drivers.
Parallel Input/Output 6.2.5 Port E, SCI1, and SPI Port E MCU Pin: Bit 7 6 5 4 3 2 1 Bit 0 0 0 PTE5/ SPSCK PTE4/ MOSI PTE3/ MISO PTE2/ SS PTE1/ RxD1 PTE0/ TxD1 Figure 6-6. Port E Pin Names Port E is an 6-bit port shared with the SCI1 module, SPI1 module, and general-purpose I/O. When the SCI or SPI modules are enabled, the pin direction will be controlled by the module function.
Parallel Input/Output Refer to Chapter 9, “Internal Clock Generator (S08ICGV4),” for more information about using these pins as oscillator pins. 6.3 Parallel I/O Controls Provided no on-chip peripheral is controlling a port pin, the pins operate as general-purpose I/O pins that are accessed and controlled by a data register (PTxD), a data direction register (PTxDD), a pullup enable register (PTxPE), and a slew rate control register (PTxSE) where x is A, B, C, D, E, or G.
Parallel Input/Output 6.4 Stop Modes Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An explanation of I/O behavior for the various stop modes follows: • When the MCU enters stop1 mode, all internal registers including general-purpose I/O control and data registers are powered down. All of the general-purpose I/O pins assume their reset state: output buffers and pullups turned off.
Parallel Input/Output 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-8. Port A Data Register (PTAD) Table 6-1. PTAD Field Descriptions Field Description 7:0 PTAD[7:0] Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register.
Parallel Input/Output 7 6 5 4 3 2 1 0 PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-10. Slew Rate Control Enable for Port A (PTASE) Table 6-3. PTASE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits PTASE[7:0] determine whether the slew rate controlled outputs are enabled.
Parallel Input/Output 6.5.2 Port B Registers (PTBD, PTBPE, PTBSE, and PTBDD) Port B includes eight general-purpose I/O pins that share with the ATD function. Port B pins used as general-purpose I/O pins are controlled by the port B data (PTBD), data direction (PTBDD), pullup enable (PTBPE), and slew rate control (PTBSE) registers. If the ATD takes control of a port B pin, the corresponding PTBDD, PTBSE, and PTBPE bits are ignored.
Parallel Input/Output 7 6 5 4 3 2 1 0 PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-14. Data Direction for Port A (PTBSE) Table 6-7. PTBSE Field Descriptions Field Description 7:0 Slew Rate Control Enable for Port B Bits — For port B pins that are outputs, these read/write control bits PTBSE[7:0] determine whether the slew rate controlled outputs are enabled. For port B pins that are configured as inputs, these bits are ignored.
Parallel Input/Output 6.5.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD) Port C includes eight general-purpose I/O pins that share with the SCI2 and IIC modules. Port C pins used as general-purpose I/O pins are controlled by the port C data (PTCD), data direction (PTCDD), pullup enable (PTCPE), and slew rate control (PTCSE) registers. If the SCI2 takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to provide slew rate on the SCI2 transmit pin, TxD2.
Parallel Input/Output 7 6 5 4 3 2 1 0 PTCPE7 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-17. Pullup Enable for Port C (PTCPE) Table 6-10. PTCPE Field Descriptions Field Description 7:0 Pullup Enable for Port C Bits — For port C pins that are inputs, these read/write control bits determine whether PTCPE[7:0] internal pullup devices are enabled.
Parallel Input/Output 6.5.4 Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) Port D includes five pins shared between general-purpose I/O, TPM1, and TPM2. Port D pins used as general-purpose I/O pins are controlled by the port D data (PTDD), data direction (PTDDD), pullup enable (PTDPE), and slew rate control (PTDSE) registers. If a TPM takes control of a port D pin, the corresponding PTDDD bit is ignored.
Parallel Input/Output R 7 6 5 0 0 0 4 3 2 1 0 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 0 0 0 0 0 W Reset 0 0 0 Figure 6-22. Slew Rate Control Enable for Port D (PTDSE) Table 6-15. PTDSE Field Descriptions Field Description 4:0 Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits PTDSE[4:0] determine whether the slew rate controlled outputs are enabled. For port D pins that are configured as inputs, these bits are ignored.
Parallel Input/Output 6.5.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) Port E includes six general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. If the SCI1 takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to provide slew rate on the SCI1 transmit pin, TxD1.
Parallel Input/Output R 7 6 0 0 5 4 3 2 1 0 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 0 0 0 0 0 0 W Reset 0 0 Figure 6-25. Pullup Enable for Port E (PTEPE) Table 6-18. PTEPE Field Descriptions Field Description 5:0 Pullup Enable for Port E Bits — For port E pins that are inputs, these read/write control bits determine whether PTEPE[5:0] internal pullup devices are enabled.
Parallel Input/Output 6.5.6 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) Port G includes four general-purpose I/O pins that are shared with BKGD/MS function and the oscillator or external clock pins. Port G pins used as general-purpose I/O pins are controlled by the port G data (PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers. Port pin PTG0, while in reset, defaults to the BKGD/MS pin.
Parallel Input/Output R 7 6 5 4 0 0 0 0 3 2 1 0 PTGSE3 PTGSE2 PTGSE1 PTGSE0 0 0 0 0 W Reset 0 0 0 0 Figure 6-30. Slew Rate Control Enable for Port G (PTGSE) Table 6-23. PTGSE Field Descriptions Field Description 3:0 Slew Rate Control Enable for Port G Bits — For port G pins that are outputs, these read/write control bits PTGSE[3:0] determine whether the slew rate controlled outputs are enabled. For port G pins that are configured as inputs, these bits are ignored.
Chapter 7 Keyboard Interrupt (S08KBIV1) 7.1 Introduction The MC9S08GT16A/GT8A has one KBI module with eight keyboard interrupt inputs that share port A pins. See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins. 7.1.1 Port A and Keyboard Interrupt Pins MCU Pin: PTA7/ KBIP7 PTA6/ KBIP6 PTA5/ KBIP5 PTA4/ KBIP4 PTA3/ KBIP3 PTA2/ KBIP2 PTA1/ KBIP1 PTA0/ KBIP0 Figure 7-1.
VREFL VREFH VSSAD VDDAD Keyboard Interrupt (S08KBIV1) BKGD 8 4 4 COP IRQ LVD INTER-IC (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) USER FLASH (GT16A = 16,384 BYTES) (GT8A = 8192 BYTES) USER RAM (GT16A = 2048 BYTES) (GT8A = 1024 BYTES) ON-CHIP ICE DEBUG MODULE (DBG) 2-CHANNEL TIMER/PWM (TPM2) SCL SDA RXD2 TXD2 CH1 CH0 3-CHANNEL TIMER/PWM (TPM1) CH0 CH1 CH2 SERIAL PERIPHERAL INTERFACE (SPI) SPSCK MOSI MISO SS SERIAL COMMUNICATIONS INTERFACE (SCI1) RXD1 TXD1 VDD VSS VSS VOLTAGE REGULATOR
Keyboard Interrupt (S08KBIV1) 7.1.3 KBI Block Diagram Figure 7-3 shows the block diagram for a KBI module. KBIP0 KBIPE0 VDD KBIPE3 0 SYNCHRONIZER S KBIPE4 KEYBOARD INTERRUPT FF STOP STOP BYPASS KEYBOARD INTERRUPT REQUEST KBIMOD 1 0 KBF CK KBEDG4 KBIPn RESET D CLR Q 1 KBIP4 BUSCLK KBACK KBIP3 KBIE S KBIPEn KBEDGn Figure 7-3. KBI Block Diagram 7.2 Register Definition This section provides information about all registers and control bits associated with the KBI module.
Keyboard Interrupt (S08KBIV1) 7.2.1 KBI Status and Control Register (KBISC) 7 6 5 4 KBEDG7 KBEDG6 KBEDG5 KBEDG4 R 3 2 KBF 0 W Reset 1 0 KBIE KBIMOD 0 0 KBACK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-4. KBI Status and Control Register (KBISC) Table 7-1.
Keyboard Interrupt (S08KBIV1) 7.2.2 KBI Pin Enable Register (KBIPE) 7 6 5 4 3 2 1 0 KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0 0 0 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 7-5. KBI Pin Enable Register (KBIPE) Table 7-2. KBIPE Register Field Descriptions Field Description 7:0 KBIPE[7:0] 7.3 7.3.
Keyboard Interrupt (S08KBIV1) 7.3.3 KBI Interrupt Controls The KBF status flag becomes set (1) when an edge event has been detected on any KBI input pin. If KBIE = 1 in the KBISC register, a hardware interrupt will be requested whenever KBF = 1. The KBF flag is cleared by writing a 1 to the keyboard acknowledge (KBACK) bit. When KBIMOD = 0 (selecting edge-only operation), KBF is always cleared by writing 1 to KBACK.
Chapter 8 Central Processor Unit (S08CPUV2) 8.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Central Processor Unit (S08CPUV2) 8.2 Programmer’s Model and CPU Registers Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 X 0 SP STACK POINTER 0 15 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-1. CPU Registers 8.2.
Central Processor Unit (S08CPUV2) 8.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-2. Condition Code Register Table 8-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
Central Processor Unit (S08CPUV2) 8.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
Central Processor Unit (S08CPUV2) 8.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 8.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 8.3.6.
Central Processor Unit (S08CPUV2) 8.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence.
Central Processor Unit (S08CPUV2) 8.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.
Central Processor Unit (S08CPUV2) 8.5 HCS08 Instruction Set Summary Instruction Set Summary Nomenclature The nomenclature listed here is used in the instruction descriptions in Table 8-2.
Central Processor Unit (S08CPUV2) 0 1 U = = = = Bit forced to 0 Bit forced to 1 Bit set or cleared according to results of operation Undefined after the operation Machine coding notation dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00) ee = Upper 8 bits of 16-bit offset ff = Lower 8 bits of 16-bit offset or 8-bit offset ii = One byte of immediate data jj = High-order byte of a 16-bit immediate data value kk = Low-order byte of a 16-bit immediate data value hh = High
Central Processor Unit (S08CPUV2) IX IX+ IX1 IX1+ = = = = IX2 REL SP1 SP2 = = = = 16-bit indexed no offset 16-bit indexed no offset, post increment (CBEQ and MOV only) 16-bit indexed with 8-bit offset from H:X 16-bit indexed with 8-bit offset, post increment (CBEQ only) 16-bit indexed with 16-bit offset from H:X 8-bit relative offset Stack pointer with 8-bit offset Stack pointer with 16-bit offset Description V H I N Z C ADC ADC ADC ADC ADC ADC ADC ADC ADD ADD ADD ADD ADD ADD ADD ADD #opr8i opr8a op
Central Processor Unit (S08CPUV2) V H I N Z C DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – – DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd Bus Cycles1 Description Operand Operation Opcode Effect on CCR Source Form Address Mode Table 8-2.
Central Processor Unit (S08CPUV2) V H I N Z C BRCLR n,opr8a,rel Branch if Bit n in Memory Clear Branch if (Mn) = 0 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – ↕ DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) BRN rel Branch Never Uses 3 Bus Cycles – – – – – – REL 21 rr DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – ↕ DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – – DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E – – – – – – REL AD rr
Central Processor Unit (S08CPUV2) V H I N Z C CPX CPX CPX CPX CPX CPX CPX CPX #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP DAA DBNZ opr8a,rel DBNZA rel DBNZX rel DBNZ oprx8,X,rel DBNZ ,X,rel DBNZ oprx8,SP,rel DEC opr8a DECA DECX DEC oprx8,X DEC ,X DEC oprx8,SP DIV EOR #opr8i EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP JMP opr8a JMP opr16a JMP oprx16,X JMP oprx8,X JMP ,X JSR opr8a JSR opr16a JSR oprx16,X
Central Processor Unit (S08CPUV2) V H I N Z C LDX #opr8i LDX opr8a LDX opr16a LDX oprx16,X LDX oprx8,X LDX ,X LDX oprx16,SP LDX oprx8,SP LSL opr8a LSLA LSLX LSL oprx8,X LSL ,X LSL oprx8,SP LSR opr8a LSRA LSRX LSR oprx8,X LSR ,X LSR oprx8,SP MOV opr8a,opr8a MOV opr8a,X+ MOV #opr8i,opr8a MOV ,X+,opr8a MUL Load X (Index Register Low) from Memory X ← (M) Logical Shift Left (Same as ASL) 0 – – ↕ C 0 b7 b0 0 Logical Shift Right C b7 b0 (M)destination ← (M)source Move H:X ← (H:X) + 0x0001 in IX+/DIR
Central Processor Unit (S08CPUV2) V H I N Z C ROR opr8a RORA RORX ROR oprx8,X ROR ,X ROR oprx8,SP Rotate Right through Carry RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine SBC SBC SBC SBC SBC SBC SBC SBC #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Subtract with Carry C b7 SP ← 0xFF (High Byte Not Affected) SP ← (SP) + 0x0001; Pull (CCR) SP ← (SP) + 0x0001; Pull (A) SP ← (SP) + 0x0001; Pull (X) SP ← (SP) + 0x0001; Pull (PCH) SP ← (SP) + 0x0001; Pull (
Central Processor Unit (S08CPUV2) Description V H I N Z C TAP TAX TPA Transfer Accumulator to CCR Transfer Accumulator to X (Index Register Low) Transfer CCR to Accumulator CCR ← (A) ↕ ↕ ↕ ↕ ↕ Bus Cycles1 Operation Operand Effect on CCR Opcode Source Form Address Mode Table 8-2.
Central Processor Unit (S08CPUV2) Table 8-3.
Central Processor Unit (S08CPUV2) Table 8-3.
Chapter 9 Internal Clock Generator (S08ICGV4) 9.1 Introduction The MC9S08GT16A/GT8A microcontroller provides one internal clock generation (ICG) module to create the system bus frequency. All functions described in this section are available on the MC9S08GT16A/GT8A microcontroller. The EXTAL and XTAL pins share port G bits 2 and 1, respectively. Analog supply lines VDDA and VSSA are internally derived from the MCU’s VDD and VSS pins.
VREFL VREFH VSSAD VDDAD Internal Clock Generator (S08ICGV4) BKGD 8 4 4 COP IRQ LVD INTER-IC (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) USER FLASH (GT16A = 16,384 BYTES) (GT8A = 8192 BYTES) USER RAM (GT16A = 2048 BYTES) (GT8A = 1024 BYTES) ON-CHIP ICE DEBUG MODULE (DBG) 2-CHANNEL TIMER/PWM (TPM2) SCL SDA RXD2 TXD2 CH1 CH0 3-CHANNEL TIMER/PWM (TPM1) CH0 CH1 CH2 SERIAL PERIPHERAL INTERFACE (SPI) SPSCK MOSI MISO SS SERIAL COMMUNICATIONS INTERFACE (SCI1) RXD1 TXD1 VDD VSS VSS VOLTAGE REGUL
Internal Clock Generator (S08ICGV4) The ICG provides multiple options for clock sources. This offers a user great flexibility when making choices between cost, precision, current draw, and performance. The ICG consists of four functional blocks. Each of these is briefly described here and then in more detail in a later section. • Oscillator block — The oscillator block provides means for connecting an external crystal or resonator.
Internal Clock Generator (S08ICGV4) • • • • • • • 9.1.
Internal Clock Generator (S08ICGV4) 9.1.3 Block Diagram Figure 9-3 is a top-level diagram that shows the functional organization of the internal clock generation (ICG) module. This section includes a general description and a feature list.
Internal Clock Generator (S08ICGV4) selected, this pin is not used by the ICG. The oscillator is capable of being configured to provide a higher amplitude output for improved noise immunity. This mode of operation is selected by HGO = 1. 9.2.3 External Clock Connections If an external clock is used, then the pins are connected as shown Figure 9-4. ICG EXTAL XTAL VSS NOT CONNECTED CLOCK INPUT Figure 9-4. External Clock Connections 9.2.
Internal Clock Generator (S08ICGV4) 9.3 Register Definition Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all ICG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 9.3.
Internal Clock Generator (S08ICGV4) Table 9-1. ICGC1 Register Field Descriptions (continued) Field 2 OSCSTEN 1 LOCD Description Enable Oscillator in Off Mode — The OSCSTEN bit controls whether or not the oscillator circuit remains enabled when the ICG enters off mode. This bit has no effect if HGO = 1 and RANGE = 1. 0 Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1. 1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1.
Internal Clock Generator (S08ICGV4) 9.3.2 ICG Control Register 2 (ICGC2) 7 6 5 4 3 2 1 0 R LOLRE MFD LOCRE RFD W Reset 0 0 0 0 0 0 0 0 Figure 9-7. ICG Control Register 2 (ICGC2) Table 9-2. ICGC2 Register Field Descriptions Field Description 7 LOLRE Loss of Lock Reset Enable — The LOLRE bit determines what type of request is made by the ICG following a loss of lock indication. The LOLRE bit only has an effect when LOLS is set. 0 Generate an interrupt request on loss of lock.
Internal Clock Generator (S08ICGV4) 9.3.3 ICG Status Register 1 (ICGS1) 7 R 6 CLKST 5 4 3 2 1 0 REFST LOLS LOCK LOCS ERCS ICGIF W Reset 1 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 9-8. ICG Status Register 1 (ICGS1) Table 9-3. ICGS1 Register Field Descriptions Field Description 7:6 CLKST Clock Mode Status — The CLKST bits indicate the current clock mode.
Internal Clock Generator (S08ICGV4) 9.3.4 R ICG Status Register 2 (ICGS2) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DCOS 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 9-9. ICG Status Register 2 (ICGS2) Table 9-4. ICGS2 Register Field Descriptions Field Description 0 DCOS DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error has not changed by more than nunlock for two consecutive samples and the DCO clock is not static.
Internal Clock Generator (S08ICGV4) 7 6 5 4 3 2 1 0 0 0 0 0 R FLT W Reset 1 1 0 0 Figure 9-11. ICG Lower Filter Register (ICGFLTL) Table 9-6. ICGFLTL Register Field Descriptions Field Description 7:0 FLT Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode, any write to ICGFLTU updates the current 12-bit filter value.
Internal Clock Generator (S08ICGV4) 9.4.1 Off Mode (Off) Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state. However there are two cases to consider when clock activity continues while the CPU is in stop mode, 9.4.1.1 BDM Active When the BDM is enabled, the ICG continues activity as originally programmed. This allows access to memory and control registers via the BDC controller. 9.4.1.
Internal Clock Generator (S08ICGV4) entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS bits.
Internal Clock Generator (S08ICGV4) 9.4.4 FLL Engaged Internal Unlocked FEI unlocked is a temporary state that is entered when FEI is entered and the count error (∆n) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition.
Internal Clock Generator (S08ICGV4) 9.4.7.1 FLL Engaged External Unlocked FEE unlocked is entered when FEE is entered and the count error (∆n) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition. The ICG will remain in this state while the count error (∆n) is greater than the maximum nlock or less than the minimum nlock, as required by the lock detector to detect the lock condition.
Internal Clock Generator (S08ICGV4) 9.4.9 FLL Loss-of-Clock Detection The reference clock and the DCO clock are monitored under different conditions (see Table 9-8). Provided the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls below a certain frequency, fLOR and fLOD, respectively, the LOCS status bit will be set to indicate the error.
Internal Clock Generator (S08ICGV4) 9.4.10 Clock Mode Requirements A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should be the same as the requested mode in CLKS1:CLKS0. Table 9-9 shows the relationship between CLKS, CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS ≠ CLKST.
Internal Clock Generator (S08ICGV4) 9.4.11 Fixed Frequency Clock The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is equal to the internal bus clock, BUSCLK, in all modes except FEE. In FEE mode, XCLK is equal to ICGERCLK ÷ 2 when the following conditions are met: • (P × N) ÷ R ≥ 4 where P is determined by RANGE (see Table 9-11), N and R are determined by MFD and RFD respectively (see Table 9-12). • LOCK = 1.
Internal Clock Generator (S08ICGV4) Table 9-10. ICG Configuration Consideration Clock Reference Source = Internal 1 Clock Reference Source = External FLL Engaged FEI 4 MHz < fBus < 20 MHz. Medium power (will be less than FEE if oscillator range = high) Good clock accuracy (After IRG is trimmed) Lowest system cost (no external components required) IRG is on. DCO is on.
Internal Clock Generator (S08ICGV4) Table 9-12. MFD and RFD Decode Table 101 110 111 9.5.2 14 16 18 101 110 111 ÷32 ÷64 ÷128 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to 8.38 MHz to achieve 4.19 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT, which corresponds to a 4 MHz bus frequency (fBus).
Internal Clock Generator (S08ICGV4) Bits 11:0 FLT No need for user initialization ICGTRM = $xx Bits 7:0 TRIM Only need to write when trimming internal oscillator; not used when external crystal is clock source Figure 9-14 shows flow charts for three conditions requiring ICG initialization. RESET INITIALIZE ICG ICGC1 = $38 ICGC2 = $00 CHECK FLL LOCK STATUS.
Internal Clock Generator (S08ICGV4) 9.5.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 4 MHz oscillator up to 40-MHz to achieve 20 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus).
Internal Clock Generator (S08ICGV4) RECOVERY FROM STOP RESET INITIALIZE ICG ICGC1 = $7A ICGC2 = $30 CHECK FLL LOCK STATUS LOCK = 1? YES SERVICE INTERRUPT SOURCE (fBus = 4 MHz) NO CHECK FLL LOCK STATUS LOCK = 1? NO YES CONTINUE CONTINUE Figure 9-15. ICG Initialization and Stop Recovery for Example #2 MC9S08GT16A/GT8A Data Sheet, Rev.
Internal Clock Generator (S08ICGV4) 9.5.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate) reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim function to fine tune the frequency based on an external reference signal.
Internal Clock Generator (S08ICGV4) ICGTRM = $xx Bit 7:0 TRIM Only need to write when trimming internal oscillator; done in separate operation (see example #4) RECOVERY FROM STOP RESET INITIALIZE ICG ICGC1 = $28 ICGC2 = $31 CHECK FLL LOCK STATUS. LOCK = 1? CHECK FLL LOCK STATUS. LOCK = 1? NO YES NO CONTINUE YES CONTINUE NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. Figure 9-16. ICG Initialization and Stop Recovery for Example #3 MC9S08GT16A/GT8A Data Sheet, Rev.
Internal Clock Generator (S08ICGV4) 9.5.5 Example #4: Internal Clock Generator Trim The internally generated clock source is guaranteed to have a period ± 25% of the nominal value. In some cases, this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate source. This section outlines one example of trimming the internal oscillator. Many other possible trimming procedures are valid and can be used.
Internal Clock Generator (S08ICGV4) MC9S08GT16A/GT8A Data Sheet, Rev.
Chapter 10 Timer/PWM (S08TPMV2) 10.1 Introduction The MC9S08GT16A/GT8A includes two independent timer/PWM (TPM) modules which support traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on each channel. A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM functions.
VREFL VREFH VSSAD VDDAD Timer/PWM (S08TPMV2) BKGD 8 4 4 COP IRQ LVD INTER-IC (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) USER FLASH (GT16A = 16,384 BYTES) (GT8A = 8192 BYTES) USER RAM (GT16A = 2048 BYTES) (GT8A = 1024 BYTES) ON-CHIP ICE DEBUG MODULE (DBG) 2-CHANNEL TIMER/PWM (TPM2) SCL SDA RXD2 TXD2 CH1 CH0 3-CHANNEL TIMER/PWM (TPM1) CH0 CH1 CH2 SERIAL PERIPHERAL INTERFACE (SPI) SPSCK MOSI MISO SS SERIAL COMMUNICATIONS INTERFACE (SCI1) RXD1 TXD1 VDD VSS VSS VOLTAGE REGULATOR PTB7/ADP7
Timer/Pulse-Width Modulator (S08TPMV2) 10.1.
Timer/Pulse-Width Modulator (S08TPMV2) BUSCLK XCLK TPMxCLK SYNC CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT CLKSB PRESCALE AND SELECT DIVIDE BY 1, 2, 4, 8, 16, 32, 64, or 128 PS2 CLKSA PS1 PS0 CPWMS MAIN 16-BIT COUNTER TOF COUNTER RESET INTERRUPT LOGIC TOIE 16-BIT COMPARATOR TPMxMODH:TPMxMODL CHANNEL 0 ELS0B ELS0A PORT LOGIC 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERRUPT LOGIC 16-BIT LATCH INTERNAL BUS CHANNEL 1 MS0B MS0A ELS1B ELS1A CH0IE TPMxCH1 PORT LOGIC 16-BIT COMPARATOR CH
Timer/Pulse-Width Modulator (S08TPMV2) All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. 10.2 External Signal Description When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 10.2.
Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some MCU systems have more than one TPM, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n and TPM1C2SC is the status and control register for timer 1, channel 2. 10.3.
Timer/Pulse-Width Modulator (S08TPMV2) Table 10-2. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 0:0 No clock selected (TPMx disabled) 0:1 Bus rate clock (BUSCLK) 1:0 Fixed system clock (XCLK) 1:1 External source (TPMxCLK)1,2 1 The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency.
Timer/Pulse-Width Modulator (S08TPMV2) R 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 W Reset Any write to TPMxCNTL clears the 16-bit counter. 0 0 0 0 0 0 Figure 10-5. Timer x Counter Register Low (TPMxCNTL) When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 10.
Timer/Pulse-Width Modulator (S08TPMV2) 10.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 CHnF CHnIE MSnB MSnA ELSnB ELSnA 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 10-8. Timer x Channel n Status and Control Register (TPMxCnSC) Table 10-4.
Timer/Pulse-Width Modulator (S08TPMV2) Table 10-5.
Timer/Pulse-Width Modulator (S08TPMV2) In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 10.
Timer/Pulse-Width Modulator (S08TPMV2) When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock period long). An interrupt flag and enable are associated with the main 16-bit counter.
Timer/Pulse-Width Modulator (S08TPMV2) 10.4.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set, clear, or toggle the channel pin.
Timer/Pulse-Width Modulator (S08TPMV2) 10.4.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
Timer/Pulse-Width Modulator (S08TPMV2) transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to PWM channels, not output compares. Optionally, when TPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL, the TPM can generate a TOF interrupt at the end of this count.
Timer/Pulse-Width Modulator (S08TPMV2) 10.5.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is set.
Chapter 11 Serial Communications Interface (S08SCIV1) 11.1 Introduction The MC9S08GT16A/GT8A includes two independent serial communications interface (SCI) modules — sometimes called universal asynchronous receiver/transmitters (UARTs). Typically, these systems are used to connect to the RS232 serial input/output (I/O) port of a personal computer or workstation, and they can also be used to communicate with other embedded controllers.
VREFL VREFH VSSAD VDDAD Serial Communications Interface (S08SCIV1) BKGD 8 4 4 COP IRQ LVD INTER-IC (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) USER FLASH (GT16A = 16,384 BYTES) (GT8A = 8192 BYTES) USER RAM (GT16A = 2048 BYTES) (GT8A = 1024 BYTES) ON-CHIP ICE DEBUG MODULE (DBG) 2-CHANNEL TIMER/PWM (TPM2) SCL SDA RXD2 TXD2 CH1 CH0 3-CHANNEL TIMER/PWM (TPM1) CH0 CH1 CH2 SERIAL PERIPHERAL INTERFACE (SPI) SPSCK MOSI MISO SS SERIAL COMMUNICATIONS INTERFACE (SCI1) RXD1 TXD1 VDD VSS VSS VOLTAG
Serial Communications Interface (S08SCIV1) 11.1.
Serial Communications Interface (S08SCIV1) 11.1.3 Block Diagram Figure 11-2 shows the transmitter portion of the SCI. (Figure 11-3 shows the receiver portion of the SCI.
Serial Communications Interface (S08SCIV1) Figure 11-3 shows the receiver portion of the SCI.
Serial Communications Interface (S08SCIV1) 11.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names.
Serial Communications Interface (S08SCIV1) 11.2.2 SCI Control Register 1 (SCIxC1) This read/write register is used to control various optional features of the SCI system. 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 R W Reset Figure 11-6. SCI Control Register 1 (SCIxC1) Table 11-3.
Serial Communications Interface (S08SCIV1) 11.2.3 SCI Control Register 2 (SCIxC2) This register can be read or written at any time. 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 R W Reset Figure 11-7. SCI Control Register 2 (SCIxC2) Table 11-4. SCIxC2 Register Field Descriptions Field 7 TIE 6 TCIE Description Transmit Interrupt Enable (for TDRE) 0 Hardware interrupts from TDRE disabled (use polling). 1 Hardware interrupt requested when TDRE flag is 1.
Serial Communications Interface (S08SCIV1) Table 11-4. SCIxC2 Register Field Descriptions (continued) Field Description 1 RWU Receiver Wakeup Control — This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is either an idle line between messages (WAKE = 0, idle-line wakeup), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wakeup).
Serial Communications Interface (S08SCIV1) Table 11-5. SCIxS1 Register Field Descriptions (continued) Field Description 5 RDRF Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCIxD). To clear RDRF, read SCIxS1 with RDRF = 1 and then read the SCI data register (SCIxD). 0 Receive data register empty. 1 Receive data register full.
Serial Communications Interface (S08SCIV1) 11.2.5 SCI Status Register 2 (SCIxS2) This register has one read-only status flag. Writes have no effect. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 RAF 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 11-9. SCI Status Register 2 (SCIxS2) Table 11-6.
Serial Communications Interface (S08SCIV1) Table 11-7. SCIxC3 Register Field Descriptions (continued) Field Description 3 ORIE Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests. 0 OR interrupts disabled (use polling). 1 Hardware interrupt requested when OR = 1. 2 NEIE Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests. 0 NF interrupts disabled (use polling).
Serial Communications Interface (S08SCIV1) 11.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
Serial Communications Interface (S08SCIV1) the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (TDRE) status flag is set to indicate another character may be written to the transmit data buffer at SCIxD.
Serial Communications Interface (S08SCIV1) has one full character time after RDRF is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is normally satisfied in the course of the user’s program that handles receive data. Refer to Section 11.3.
Serial Communications Interface (S08SCIV1) 11.3.3.2.1 Idle-Line Wakeup When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared automatically when the receiver detects a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits).
Serial Communications Interface (S08SCIV1) When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied. The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD1 line remains idle for an extended period of time.
Serial Communications Interface (S08SCIV1) 11.3.5.3 Loop Mode When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD1 pin is not used by the SCI, so it reverts to a general-purpose port I/O pin. 11.3.5.
Chapter 12 Serial Peripheral Interface (S08SPIV3) 12.1 Introduction The MC9S08GT16A/GT8A provides one serial peripheral interface (SPI) module. The four pins associated with SPI functionality are shared with port E pins 2–5. See the Appendix A, “Electrical Characteristics,” appendix for SPI electrical parametric information. When the SPI is enabled, the direction of pins is controlled by module configuration. If the SPI is disabled, all four pins can be used as general-purpose I/O.
VREFL VREFH VSSAD VDDAD Serial Peripheral Interface (S08SPIV3) BKGD 8 4 4 COP IRQ LVD INTER-IC (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) USER FLASH (GT16A = 16,384 BYTES) (GT8A = 8192 BYTES) USER RAM (GT16A = 2048 BYTES) (GT8A = 1024 BYTES) ON-CHIP ICE DEBUG MODULE (DBG) 2-CHANNEL TIMER/PWM (TPM2) SCL SDA RXD2 TXD2 CH1 CH0 3-CHANNEL TIMER/PWM (TPM1) CH0 CH1 CH2 SERIAL PERIPHERAL INTERFACE (SPI) SPSCK MOSI MISO SS SERIAL COMMUNICATIONS INTERFACE (SCI1) RXD1 TXD1 VDD VSS VSS VOLTAGE RE
Serial Peripheral Interface (S08SPIV3) Module Initialization (Slave): Write: SPIC1 to configure interrupts, set primary SPI options, slave mode select, and system enable. Write: SPIC2 to configure optional SPI features Module Initialization (Master): Write: SPIC1 to configure interrupts, set primary SPI options, master mode select, and system enable.
Serial Peripheral Interface (S08SPIV3) 12.1.2 Block Diagrams This section includes block diagrams showing SPI system connections, the internal organization of the SPI module, and the SPI clock dividers that control the master mode bit rate. 12.1.2.1 SPI System Block Diagram Figure 12-3 shows the SPI modules of two MCUs connected in a master-slave arrangement. The master device initiates all SPI data transfers.
Serial Peripheral Interface (S08SPIV3) When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is routed to MOSI, and the shifter input is routed from the MISO pin. When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI pin.
Serial Peripheral Interface (S08SPIV3) BUS CLOCK PRESCALER CLOCK RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 12-5. SPI Baud Rate Generation 12.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits.
Serial Peripheral Interface (S08SPIV3) 12.3 Modes of Operation 12.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
Serial Peripheral Interface (S08SPIV3) Table 12-1. SPIC1 Field Descriptions (continued) Field Description 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 12.5.1, “SPI Clock Formats” for more details.
Serial Peripheral Interface (S08SPIV3) Table 12-3. SPIC2 Register Field Descriptions Field Description 4 MODFEN Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 12-2 for more details).
Serial Peripheral Interface (S08SPIV3) Table 12-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 12-6. SPI Baud Rate Divisor 12.4.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPIS) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Serial Peripheral Interface (S08SPIV3) Table 12-7. SPIS Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
Serial Peripheral Interface (S08SPIV3) 12.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
Serial Peripheral Interface (S08SPIV3) pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ...
Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1).
Serial Peripheral Interface (S08SPIV3) 12.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF).
Serial Peripheral Interface (S08SPIV3) 12.6.1.2 Pseudo—Code Example In this example, the SPI module will be set up for master mode with only transmit interrupts enabled to run at a maximum baud rate of bus clock divided by 2. Clock phase and polarity will be set for an active-high SPI clock where the first edge on SPSCK occurs at the start of the first cycle of a data transfer.
Serial Peripheral Interface (S08SPIV3) RESET INITIALIZE SPI SPIC1 = 0x74 SPIC2 = 0x00 SPIBR = 0x00 SPTEF = 1 ? NO YES READ SPIS WITH SPTEF SET TO CLEAR FLAG, THEN WRITE DATA TO SPID CONTINUE Figure 12-13. Initialization Flowchart Example for SPI Master Device MC9S08GT16A/GT8A Data Sheet, Rev.
Serial Peripheral Interface (S08SPIV3) MC9S08GT16A/GT8A Data Sheet, Rev.
Chapter 13 Inter-Integrated Circuit (S08IICV1) 13.1 Introduction The MC9S08GT16A/GT8A series of microcontrollers provides one inter-integrated circuit (IIC) module for communication with other integrated circuits. The two pins associated with this module, SDA and SCL share port C pins 2 and 3, respectively. All functionality as described in this section is available on MC9S08GT16A/GT8A. When the IIC is enabled, the direction of pins is controlled by module configuration.
VREFL VREFH VSSAD VDDAD Inter-Integrated Circuit (S08IICV1) BKGD 8 4 4 COP IRQ LVD INTER-IC (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) USER FLASH (GT16A = 16,384 BYTES) (GT8A = 8192 BYTES) USER RAM (GT16A = 2048 BYTES) (GT8A = 1024 BYTES) ON-CHIP ICE DEBUG MODULE (DBG) 2-CHANNEL TIMER/PWM (TPM2) SCL SDA RXD2 TXD2 CH1 CH0 3-CHANNEL TIMER/PWM (TPM1) CH0 CH1 CH2 SERIAL PERIPHERAL INTERFACE (SPI) SPSCK MOSI MISO SS SERIAL COMMUNICATIONS INTERFACE (SCI1) RXD1 TXD1 VDD VSS VSS VOLTAGE REGUL
Inter-Integrated Circuit (S08IICV1) 13.1.
Inter-Integrated Circuit (S08IICV1) 13.1.3 Block Diagram Figure 13-2 is a block diagram of the IIC. ADDRESS DATA BUS INTERRUPT ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG INPUT SYNC START STOP ARBITRATION CONTROL CLOCK CONTROL IN/OUT DATA SHIFT REGISTER ADDRESS COMPARE SCL SDA Figure 13-2. IIC Functional Block Diagram 13.2 External Signal Description This section describes each user-accessible pin signal. 13.2.
Inter-Integrated Circuit (S08IICV1) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 13.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 0 0 R ADDR W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-3.
Inter-Integrated Circuit (S08IICV1) Table 13-2. IICA Register Field Descriptions Field Description 7:6 MULT IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved 5:0 ICR IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection.
Inter-Integrated Circuit (S08IICV1) Table 13-3.
Inter-Integrated Circuit (S08IICV1) 13.3.3 IIC Control Register (IICC) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-5. IIC Control Register (IICC) Table 13-4. IICC Register Field Descriptions Field Description 7 IICEN IIC Enable — The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled. 1 IIC is enabled.
Inter-Integrated Circuit (S08IICV1) 13.3.4 IIC Status Register (IICS) 7 R 6 TCF 5 4 BUSY IAAS 3 2 0 SRW ARBL 1 0 RXAK IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-6. IIC Status Register (IICS) Table 13-5. IICS Register Field Descriptions Field Description 7 TCF Transfer Complete Flag — This bit is set on the completion of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.
Inter-Integrated Circuit (S08IICV1) 13.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset 0 0 0 0 Figure 13-7. IIC Data I/O Register (IICD) Table 13-6. IICD Register Field Descriptions Field Description 7:0 DATA Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Inter-Integrated Circuit (S08IICV1) 13.4 Functional Description This section provides a complete functional description of the IIC module. 13.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
Inter-Integrated Circuit (S08IICV1) 13.4.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 13-8, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. 13.4.1.
Inter-Integrated Circuit (S08IICV1) 13.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 13-8).
Inter-Integrated Circuit (S08IICV1) DELAY START COUNTING HIGH PERIOD SCL1 SCL2 SCL INTERNAL COUNTER RESET Figure 13-9. IIC Clock Synchronization 13.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 13.4.1.
Inter-Integrated Circuit (S08IICV1) 13.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of byte transfer. 13.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register), the IAAS bit in the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 13.6.
Inter-Integrated Circuit (S08IICV1) MC9S08GT16A/GT8A Data Sheet, Rev.
Chapter 14 Analog-to-Digital Converter (S08ATDV3) The MC9S08GT16A/GT8A provides one 8-channel analog-to-digital (ATD) module. The eight ATD channels share port B. Each channel individually can be configured for general-purpose I/O or for ATD functionality. All features of the ATD module as described in this section are available on the MC9S08GT16A/GT8A. Electrical parametric information for the ATD may be found in Appendix A, “Electrical Characteristics.” MC9S08GT16A/GT8A Data Sheet, Rev.
VREFL VREFH VSSAD VDDAD Analog-to-Digital Converter (S08ATDV3) BKGD 8 4 4 COP IRQ LVD INTER-IC (IIC) SERIAL COMMUNICATIONS INTERFACE (SCI2) USER FLASH (GT16A = 16,384 BYTES) (GT8A = 8192 BYTES) USER RAM (GT16A = 2048 BYTES) (GT8A = 1024 BYTES) ON-CHIP ICE DEBUG MODULE (DBG) 2-CHANNEL TIMER/PWM (TPM2) SCL SDA RXD2 TXD2 CH1 CH0 3-CHANNEL TIMER/PWM (TPM1) CH0 CH1 CH2 SERIAL PERIPHERAL INTERFACE (SPI) SPSCK MOSI MISO SS SERIAL COMMUNICATIONS INTERFACE (SCI1) RXD1 TXD1 VDD VSS VSS VOLTAGE RE
Analog-to-Digital Converter (S08ATDV3) 14.1 Introduction The ATD module is an analog-to-digital converter with a successive approximation register (SAR) architecture with sample and hold. 14.1.1 • • • • • • • Features 8-/10-bit resolution 14.
Analog-to-Digital Converter (S08ATDV3) CONTROL INTERRUPT DATA JUSTIFICATION CONTROL AND STATUS REGISTERS ADDRESS R/W DATA RESULT REGISTERS SAR_REG <9:0> CTL VDD STATUS PRESCALER VSS CTL BUSCLK CONVERSION MODE CLOCK PRESCALER CONTROL BLOCK STATE MACHINE CONVERSION CLOCK DIGITAL ANALOG CTL POWERDOWN VREFH VREFL VSSAD SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER (ATD) BLOCK ADP0 ADP1 ADP2 ADP3 ADP4 CONVERSION REGISTER VDDAD INPUT MUX ADP5 ADP6 ADP7 = INTERNAL PINS = CH
Analog-to-Digital Converter (S08ATDV3) Table 14-1. Signal Properties 14.2.1 Name Function AD7–AD0 Channel input pins VREFH High reference voltage for ATD converter VREFL Low reference voltage for ATD converter VDDAD ATD power supply voltage VSSAD ATD ground supply voltage ADP7–ADP0 — Channel Input Pins The channel pins are used as the analog input pins of the ATD. Each pin is connected to an analog switch which serves as the signal gate into the sample submodule. 14.2.
Analog-to-Digital Converter (S08ATDV3) R W Reset 7 6 5 4 ATDPU DJM RES8 SGN 0 0 0 0 3 2 1 0 0 0 PRS 0 0 Figure 14-3. ATD Control Register (ATDC) Table 14-2. ATDC Field Descriptions Field Description 7 ATDPU ATD Power Up — This bit provides program on/off control over the ATD, reducing power consumption when the ATD is not being used. When cleared, the ATDPU bit aborts any conversion in progress. 0 Disable the ATD and enter a low-power state. 1 ATD functionality.
Analog-to-Digital Converter (S08ATDV3) Table 14-3.
Analog-to-Digital Converter (S08ATDV3) 14.3.2 ATD Status and Control (ATDSC) Writes to the ATD status and control register clears the CCF flag, cancels any pending interrupts, and initiates a new conversion. 7 R CCF 6 5 ATDIE ATDCO 0 0 4 3 2 1 0 0 1 ATDCH W Reset 0 0 0 0 = Unimplemented or Reserved Figure 14-6. ATD Status and Control Register (ATDSC) Table 14-5.
Analog-to-Digital Converter (S08ATDV3) 14.3.3 ATD Result Data (ATDRH, ATDRL) For left-justified mode, result data bits 9–2 map onto bits 7–0 of ATDRH, result data bits 1 and 0 map onto ATDRL bits 7 and 6, where bit 7 of ATDRH is the most significant bit (MSB). 7 6 5 4 3 9 2 1 0 7 6 5 4 3 2 1 0 0 RESULT ATD1RH ATD1RL Figure 14-7.
Analog-to-Digital Converter (S08ATDV3) 14.4 Functional Description The ATD uses a successive approximation register (SAR) architecture. The ATD contains all the necessary elements to perform a single analog-to-digital conversion. A write to the ATDSC register initiates a new conversion. A write to the ATDC register will interrupt the current conversion but it will not initiate a new conversion. A write to the ATDPE register will also abort the current conversion but will not initiate a new conversion.
Analog-to-Digital Converter (S08ATDV3) When the S/H machine is not sampling, it disables its own internal clocks.The input analog signals are unipolar. The signals must fall within the potential range of VSSAD to VDDAD. The S/H machine is not required to perform special conversions (i.e., convert VREFL and VREFH).
Analog-to-Digital Converter (S08ATDV3) ES = 2N * (∆VSAMP / (VREFH – VREFL)) * (CAIN / (CAIN + CAS)) Eqn. 14-3 In the case of a 0.1 µF CAS, a worst case sampling error of 0.5 LSB is achieved regardless of RAS. However, in the case of repeated conversions at a rate of fSAMP, RAS must re-charge CAS.
Analog-to-Digital Converter (S08ATDV3) of how straight the line is (how far it deviates from a straight line). The adjusted ideal transition voltage is: Eqn. 14-6 Adjusted Ideal Trans. V = (Current Code - 1/2) * ((VREFH + EFS) - (VREFL + EZS)) 2N • Zero scale error (EZS) — This is the difference between the transition voltage to the first valid code and the ideal transition to that code.
Analog-to-Digital Converter (S08ATDV3) CODE D C TOTAL UNADJUSTED ERROR BOUNDARY B A IDEAL TRANSFER FUNCTION 9 NEGATIVE DNL (CODE WIDTH <1LSB) 8 IDEAL STRAIGHT-LINE 7 TRANSFER FUNCTION QUANTIZATION ERROR 6 INL (ASSUMES EZS = EFS = 0) 5 1 LSB 4 TOTAL UNADJUSTED 3 ERROR AT THIS CODE 2 POSITIVE DNL 1 (CODE WIDTH >1LSB) 0 1 2 3 4 8 12 LSB NOTES: Graph is for example only and may not represent actual performance Figure 14-11. ATD Accuracy Definitions MC9S08GT16A/GT8A Data Sheet, Rev.
Analog-to-Digital Converter (S08ATDV3) 14.5 Resets The ATD module is reset on system reset. If the system reset signal is activated, the ATD registers are initialized back to their reset state and the ATD module is powered down. This occurs as a function of the register file initialization; the reset definition of the ATDPU bit (power down bit) is zero or disabled. The MCU places the module back into an initialized state.
Analog-to-Digital Converter (S08ATDV3) MC9S08GT16A/GT8A Data Sheet, Rev.
Chapter 15 Development Support 15.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories.
Development Support 15.1.
Development Support • Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller. Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system.
Development Support When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a development system is connected, it can pull both BKGD and RESET low, release RESET to select active background mode rather than normal operating mode, then release BKGD. It is not necessary to reset the target MCU to communicate with it through the background debug interface. 15.2.
Development Support Figure 15-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges.
Development Support Figure 15-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles).
Development Support Figure 15-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
Development Support 15.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program.
Development Support Table 15-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
Development Support 15.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture.
Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port.
Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU.
Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match.
Development Support 15.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 15.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue.
Development Support 15.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 15-5.
Development Support Table 15-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 15-6. System Background Debug Force Reset Register (SBDFR) Table 15-3.
Development Support 15.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word.
Development Support 15.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 15-7. Debug Control Register (DBGC) Table 15-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
Development Support 15.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 15-8. Debug Trigger Register (DBGT) Table 15-5.
Development Support 15.4.3.9 Debug Status Register (DBGS) This is a read-only status register. R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 15-9. Debug Status Register (DBGS) Table 15-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming.
Appendix A Electrical Characteristics A.1 Introduction This section contains electrical and timing specifications. A.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table A-1.
Electrical Characteristics Table A-2. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to +3.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID ± 25 mA Tstg –55 to 150 °C TJ 150 °C Storage temperature range Maximum junction temperature 1 Input must be current limited to the value specified.
Electrical Characteristics Table A-3.
Electrical Characteristics A.5 Electrostatic Discharge (ESD) Protection Characteristics Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
Electrical Characteristics Table A-6. DC Characteristics (Sheet 1 of 2) (Temperature Range = –40 to 125°C Ambient) C P P P P P Parameter Symbol Min Minimum RAM retention supply voltage applied to VDD VRAM 1.02 Low-voltage detection threshold — high range (VDD falling) (VDD rising) VLVDH Low-voltage detection threshold — low range (VDD falling) (VDD rising) VLVDL Low-voltage warning threshold — high range (VDD falling) (VDD rising) VLVWH Typical1 Max Unit — V V 2.08 2.16 2.1 2.19 2.
Electrical Characteristics Table A-6. DC Characteristics (Sheet 2 of 2) (Temperature Range = –40 to 125°C Ambient) C D D D C 2 3 4 5 6 7 Symbol Typical1 Max Unit — 0.5 V — — — 0.5 0.5 0.5 60 mA Min Output low voltage (VDD ≥ 1.8 V) IOL = 2.0 mA (ports A, B, D, E, and G) Output low voltage (port C) IOL = 10.0 mA (VDD ≥ 2.7 V) IOL = 6 mA (VDD ≥ 2.3 V) IOL = 3 mA (VDD ≥ 1.
Electrical Characteristics TYPICAL VOL VS VDD TYPICAL VOL VS IOL AT VDD = 3.0 V 1 0.4 85°C 25°C –40°C 0.8 85°C 25°C –40°C 0.3 VOL (V) VOL (V) 0.6 0.4 0.2 IOL = 10 mA IOL = 6 mA 0.1 0.2 IOL = 3 mA 0 0 0 10 20 30 1 2 3 4 VDD (V) IOL (mA) Figure A-2. Typical Low-Side Driver (Sink) Characteristics (Port C) TYPICAL VOL VS IOL AT VDD = 3.0 V 1.2 85°C 25°C –40°C 1 0.15 VOL (V) 0.8 VOL (V) TYPICAL VOL VS VDD 0.2 0.6 0.4 0.1 85°C, IOL = 2 mA 25°C, IOL = 2 mA –40°C, IOL = 2 mA 0.
Electrical Characteristics TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 1.2 85°C 25°C –40°C 85°C, IOH = 2 mA 25°C, IOH = 2 mA –40°C, IOH = 2 mA 0.2 VDD – VOH (V) 1 VDD – VOH (V) TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.25 0.8 0.6 0.4 0.15 0.1 0.05 0.2 0 0 0 –5 –10 IOH (mA) –15 –20 1 2 VDD (V) 3 4 Figure A-5. Typical High-Side (Source) Characteristics (Ports A, B, D, E, and G) A.7 Supply Current Characteristics Table A-7.
Electrical Characteristics Table A-7. Supply Current Characteristics (continued) Typical1 Max2 Temp. (°C) 675 nA 4.3 µA(4) 7.2 µA(4) 17.0 µA(5) 45 µA(5) 55 70 85 125 2 500 nA 3.5 µA(4) 6.2 µA(4) 15.
Electrical Characteristics 14 = FEI mode, ATD off, 20 MHz 12 = FBE mode, ATD off, 20 MHz = FEI mode, ATD off, 16 MHz 10 8 IDD (mA) = FBE mode, all modules enabled, 8 MHz = FEI mode, ATD off, 8 MHz 6 4 2 = FEI mode, ATD off, 1 MHz = FBE mode, ATD off, 1 MHz 0 0 3.6 0 3.5 0 3.4 0 3.3 0 3.2 0 3.1 0 3.0 0 2.9 0 2.8 0 2.7 0 2.6 0 2.5 0 2.4 0 2.3 0 2.2 0 2.1 0 2.0 0 1.9 0 1.8 VDD (Vdc) Figure A-6. Typical Run IDD for FBE and FEE Modes, IDD vs VDD MC9S08GT16A/GT8A Data Sheet, Rev.
Electrical Characteristics 1.4 1.2 1 IDD (µA) 0.8 25°C 75°C 85°C 105°C 125°C 0.6 0.4 0.2 0 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VDD (Vdc) Figure A-7. Typical Stop1 IDD MC9S08GT16A/GT8A Data Sheet, Rev.
Electrical Characteristics Figure A-8. Typical Stop 2 IDD MC9S08GT16A/GT8A Data Sheet, Rev.
Electrical Characteristics Figure A-9. Typical Stop3 IDD MC9S08GT16A/GT8A Data Sheet, Rev.
Electrical Characteristics A.8 ATD Characteristics Table A-8. ATD Electrical Characteristics (Operating) No. Characteristic 1 ATD supply1 2 ATD supply current Condition Symbol Min Typ Max Unit VDDAD 1.80 — 3.6 V Enabled IDDADrun — 0.7 1.2 mA Disabled (ATDPU = 0 or STOP) IDDADstop — 0.02 0.
Electrical Characteristics Table A-9. ATD Timing/Performance Characteristics1 (continued) No. Characteristic Ideal resolution (1 LSB)5 7 Condition Symbol Min Typ Max Unit 2.08V < VDDAD < 3.6V RES 2.031 — 3.516 mV 1.758 — 2.031 1.80V < VDDAD < 2.08V 8 Differential non-linearity6 1.80V < VDDAD < 3.6V DNL — +0.5 +1.0 LSB 9 Integral non-linearity7 1.80 V < VDDAD < 3.6V INL — +0.5 +1.0 LSB 10 Zero-scale error8 1.80V < VDDAD < 3.6V EZS — +0.4 +1.
Electrical Characteristics A.9 Internal Clock Generation Module Characteristics ICG EXTAL XTAL RS RF C1 Crystal or Resonator (See Note) C2 NOTE: Use fundamental mode crystal or ceramic resonator only. Table A-10.
Electrical Characteristics A.9.1 ICG Frequency Specifications Table A-11. ICG Frequency Specifications (VDDA = VDDA (min) to VDDA (max), Temperature Range = –40 to 125°C Ambient) Characteristic Symbol Min Typical Max Unit flo 32 — 100 kHz fhi_byp fhi_eng flp_byp flp_eng 1 2 1 2 — — — — 16 10 8 8 MHz MHz MHz MHz flo fhi_eng 32 2 — — 100 10 kHz MHz fExtal 0 — 40 MHz fICGIRCLK 182.25 243 303.
Electrical Characteristics 1 2 3 4 5 6 7 8 Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop. Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it is not in the desired range. Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if an external reference exists) if it is not in the desired range.
Electrical Characteristics A.10.1 Control Timing Table A-12. Control Timing Parameter Symbol Min Typical Max Unit fBus 0 0 — 20 8 MHz tRTI 750 1150 1550 µs External reset pulse width1 textrst 1.5 x fSelf_reset — ns Reset low drive2 trstdrv 34 x fSelf_reset — ns Active background debug mode latch setup time tMSSU 25 — ns Active background debug mode latch hold time tMSH 25 — ns IRQ pulse width3 tILIH 1.
Electrical Characteristics textrst RESET PIN Figure A-12. Reset Timing BKGD/MS RESET tMSH tMSSU Figure A-13. Active Background Debug Mode Latch Timing tILIH IRQ Figure A-14. IRQ Timing A.10.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-13.
Electrical Characteristics tText tclkh TPMxCHn tclkl Figure A-15. Timer External Clock tICPW TPMxCHn TPMxCHn tICPW Figure A-16. Timer Input Capture Pulse MC9S08GT16A/GT8A Data Sheet, Rev.
Electrical Characteristics A.10.3 SPI Timing Table A-14 and Figure A-17 through Figure A-20 describe the timing requirements for the SPI system. Table A-14. SPI Timing No.
Electrical Characteristics SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 11 3 4 4 12 SCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN2 BIT 6 . . . 1 9 LSB IN 9 MOSI (OUTPUT) MSB OUT2 10 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-17.
Electrical Characteristics SS (INPUT) 1 12 11 11 12 3 SCK (CPOL = 0) (INPUT) 2 4 4 SCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) 9 SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 6 5 MOSI (INPUT) 10 10 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure A-19.
Electrical Characteristics A.11 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, “Memory.” Table A-15.
Electrical Characteristics MC9S08GT16A/GT8A Data Sheet, Rev.
Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering information for MC9S08GT16A and MC9S08GT8A devices. Table 15-7. Devices in the MC9S08GT16A/GT8A Series 1 B.1.1 Device FLASH RAM Packages1 MC9S08GT16A 16K 2K MC9S08GT8A 8K 1K 48 QFN 44 QFP 42 SDIP 32 QFN See Table B-1 for package information.
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