MC9S08LC60 MC9S08LC36 Data Sheet: Technical Data HCS08 Microcontrollers MC9S08LC60 Rev. 4 07/2007 freescale.
MC9S08LC60 Series Features 8-Bit HCS08 Central Processor Unit (CPU) • • • • • • 40-MHz HCS08 CPU HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) In-Circuit Emulator (ICE) debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data.
MC9S08LC60 Series Data Sheet Covers MC9S08LC60 MC9S08LC36 MC9S08LC60 Rev. 4 07/2007 This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007. All rights reserved.
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com The following revision history table summarizes changes contained in this document. Revision Number Revision Date 1 02/2007 Initial advance information release.
List of Chapters Chapter Title Page Chapter 1 Device Overview .............................................................................. 21 Chapter 2 Pins and Connections ..................................................................... 25 Chapter 3 Modes of Operation ......................................................................... 33 Chapter 4 Memory .............................................................................................
Table of Contents Section Number Title Page Chapter 1 Device Overview 1.1 1.2 1.3 1.4 Introduction .....................................................................................................................................21 Devices in the MC9S08LC60 Series ...............................................................................................21 MCU Block Diagram ......................................................................................................................
Section Number Title Page Chapter 4 Memory 4.1 4.2 4.3 4.4 4.5 4.6 MC9S08LC60 Series Memory Map ...............................................................................................39 4.1.1 Reset and Interrupt Vector Assignments ........................................................................40 Register Addresses and Bit Assignments ........................................................................................42 RAM ...........................................................
Section Number 5.8.3 5.8.4 5.8.5 5.8.6 5.8.7 5.8.8 5.8.9 5.8.10 Title Page System Background Debug Force Reset Register (SBDFR) ..........................................73 System Options Register (SOPT1) .................................................................................73 System Options Register (SOPT2) .................................................................................74 System Device Identification Register (SDIDH, SDIDL) ..............................................
Section Number 7.2 7.3 7.4 Title Page External Signal Description ............................................................................................................98 Register Definition ..........................................................................................................................99 7.3.1 KBIx Status and Control Register (KBIxSC) .................................................................99 7.3.2 KBIx Pin Enable Register (KBIxPE) ..............................
Section Number Title Page Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.1 9.2 9.3 9.4 9.5 Introduction ...................................................................................................................................123 9.1.1 Features .........................................................................................................................125 9.1.2 Modes of Operation ..............................................................................................
Section Number 9.6 Title Page 9.5.2.1 Initialization Example 1 ................................................................................158 9.5.2.2 Initialization Example 2 ................................................................................159 9.5.2.3 Initialization Example 3 ................................................................................161 9.5.2.4 Initialization Example 4 ................................................................................
Section Number Title Page 10.5.8 FLL Lock and Loss-of-Lock Detection ........................................................................184 10.5.9 FLL Loss-of-Clock Detection ......................................................................................185 10.5.10 Clock Mode Requirements ...........................................................................................186 10.5.11 Fixed Frequency Clock ..................................................................................
Section Number Title Page 12.1.3 Block Diagram ..............................................................................................................217 12.2 Register Definition ........................................................................................................................219 12.2.1 SCI Baud Rate Registers (SCIBDH, SCIBHL) ............................................................219 12.2.2 SCI Control Register 1 (SCIC1) .................................................
Section Number Title Page 13.5 Functional Description ..................................................................................................................244 13.5.1 SPI Clock Formats ........................................................................................................244 13.5.2 SPI Interrupts ................................................................................................................247 13.5.3 Mode Fault Detection ......................................
Section Number 15.2 15.3 15.4 15.5 15.6 Title Page 15.1.1.3 Hardware Trigger ..........................................................................................268 15.1.1.4 Analog Pin Enables .......................................................................................268 15.1.1.5 Temperature Sensor ......................................................................................268 15.1.1.6 Low-Power Mode Operation ..............................................................
Section Number 15.6.1 15.6.2 Title Page External Pins and Routing ............................................................................................288 15.6.1.1 Analog Supply Pins ......................................................................................288 15.6.1.2 Analog Reference Pins ..................................................................................289 15.6.1.3 Analog Input Pins ....................................................................................
Section Number Title Page 17.4 Register Definition ........................................................................................................................314 17.4.1 BDC Registers and Control Bits ...................................................................................314 17.4.1.1 BDC Status and Control Register (BDCSCR) ..............................................315 17.4.1.2 BDC Breakpoint Match Register (BDCBKPT) ............................................316 17.4.
Chapter 1 Device Overview 1.1 Introduction MC9S08LC60 Series MCUs are members of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. 1.2 Devices in the MC9S08LC60 Series Table 1-1 lists the devices available in the MC9S08LC60 Series and summarizes the differences among them. Table 1-1.
Chapter 1 Device Overview 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC9S08LC60 Series MCUs.
Chapter 1 Device Overview Table 1-3 lists the functional versions of the on-chip modules. Table 1-3. Module Versions Module 1.
Chapter 1 Device Overview Control bits inside the ICG determine which source is connected. • FFE is a control signal generated inside the ICG. If the frequency of ICGOUT > 4 × the frequency of ICGERCLK, this signal is a logic 1 and the fixed-frequency clock will be the ICGERCLK. Otherwise the fixed-frequency clock will be BUSCLK. • ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow.
Chapter 2 Pins and Connections 2.1 Introduction This section describes signals that connect to package pins. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 2.2 Device Pin Assignment Figure 2-1 and Figure 2-2 show the pin assignments for the MC9S08LC60 Series devices in its available packages. MC9S08LC60 Series Data Sheet: Technical Data, Rev.
MC9S08LC60 Series 80-Pin LQFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 FP27 FP28 FP29 FP30 FP31 FP32 FP33 FP34 FP35 FP36 FP37 FP38 FP39 PTC7/KBI2P7/IRQ/TPMCLK PTC6/ BKGD/MS PTC5/KBI2P6/TPM2CH1 PTC4/KBI2P5/TPM2CH0 PTC3/SS2/TPM1CH1 PTC2/SPSCK2/TPM1CH0 PTC1/MOSI2/TxD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PTA3/KBI1P3/ADP3/ACMP– PTA4/KBI1P4/ADP4 PTA5/KBI1P5/ADP5 PTA6/KBI1P6/ADP6 PTA7/KBI1P7/ADP7 VSSAD VREFL VREFH VDD
MC9S08LC60 Series 64-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FP22 FP23 FP24 FP25 FP26 FP27 FP28 FP29 FP30 FP31 PTC7/KBI2P7/IRQ/TPMCLK PTC6 /BKGD/MS PTC5/KBI2P6/TPM2CH1 PTC4/KBI2P5/TPM2CH0 PTC3/SS2/TPM1CH1 PTC2/SPSCK2/TPM1CH0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PTA2/KBI1P2/ADP2/ACMP+ PTA3/KBI1P3/ADP3/ACMP– VSSAD/VREFL VDDAD/VREFH PTB0/KBI2P0/EXTAL PTB1/KBI2P1/XTAL VDD VSS PTB2/RESET PTB3/KBI2P2 PTB4/MISO1/SDA PTB5/MOSI1/SCL PTB6/KBI2P3/
Chapter 2 Pins and Connections CBYAD 0.1 μF CBLK + 10 μF CBY 0.
Chapter 2 Pins and Connections 2.3.1 Power (VDD, VSS, VDDAD, VSSAD) VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU. Typically, application systems have two separate capacitors across the power pins.
Chapter 2 Pins and Connections 2.3.4 RESET Pin After POR, the configuration of the PTB2/RESET pin defaults to RESET. Clearing the RSTPE bit in SOPT1 register configures the pin to be the PTB2 general-purpose, output only pin. After configured as PTB2, the pin will remain PTB2 until the next reset. The RESET pin can be used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET pin (RSTPE = 1), an internal pullup device is automatically enabled.
Chapter 2 Pins and Connections 2.3.6 2.3.6.1 LCD Pins LCD Power Pins The VLCD, VLL1, VLL2, VLL3, Vcap1, and Vcap2 pins are dedicated to providing power to the LCD module. For detailed information about these pins see the LCD chapter. 2.3.6.2 LCD Frontplane and Backplane Driver Pins 44 pins are dedicated to frontplane and backplane drivers; on the 64-pin package, 36 pins are dedicated. Immediately after reset, the LCD driver pins are high-impedance.
Chapter 2 Pins and Connections Table 2-1.
Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08LC60 Series are described in this section. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 • • • 3.
Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.
Chapter 3 Modes of Operation 3.6 Stop Modes One of three stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set. In any stop mode, the bus and CPU clocks are halted. The ICG module can be configured to leave the reference clocks running. see Chapter 10, “Internal Clock Generator (S08ICGV4)” for more information. Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions.
Chapter 3 Modes of Operation 3.6.1.1 LVD Enabled in Stop Mode The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. For the ADC to operate the LVD must be left enabled when entering stop3. 3.6.1.
Chapter 3 Modes of Operation before writing to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the pins will switch to their reset states when PPDACK is written. For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before writing to the PPDACK bit.
Chapter 3 Modes of Operation Table 3-2.
Chapter 4 Memory 4.1 MC9S08LC60 Series Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08LC60 Series consists of RAM, FLASH program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: • Direct-page registers (0x0000 through 0x005F) • High-page registers (0x1800 through 0x186F) • Nonvolatile registers (0xFFB0 through 0xFFBF) MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 4 Memory 0x0000 0x0000 DIRECT PAGE REGISTERS DIRECT PAGE REGISTERS 0x005F 0x0060 0x005F 0x0060 RAM 2560 BYTES RAM 4096 BYTES 0x0A5F 0x0A60 0x105F 0x1060 UNIMPLEMENTED FLASH B 1952 BYTES 0x17FF 0x1800 0x17FF 0x1800 HIGH PAGE REGISTERS HIGH PAGE REGISTERS 0x186F 0x1870 0x186F 0x1870 FLASH B 26,512 BYTES FLASH B 12,288 BYTES 0x486F 0x4870 UNIMPLEMENTED 0x7FFF 0x8000 0x9FFF 0xA000 FLASH A 32,768 BYTES FLASH A 24,576 BYTES 0xFFFF 0xFFFF MC9S08LC36 MC9S08LC60 Figure 4-1.
Chapter 4 Memory Table 4-1.
Chapter 4 Memory 4.2 Register Addresses and Bit Assignments The registers in the MC9S08LC60 Series are divided into these three groups: • Direct-page registers are located in the first 128 locations in the memory map, so they are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves more room in the direct page for more frequently used registers and variables.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-2.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory Table 4-3.
Chapter 4 Memory The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF.
Chapter 4 Memory 4.4.
Chapter 4 Memory 4.4.3 Program and Erase Command Execution The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are: 1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into the FLASH interface. This write is a required first step in any command sequence.
Chapter 4 Memory WRITE TO FCDIV (Note 1) FLASH PROGRAM AND ERASE FLOW Note 1: Required only once after reset. START FACCERR ? 0 1 CLEAR ERROR WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) FPVIOL OR FACCERR ? Note 2: Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NO 0 FCCF ? 1 DONE Figure 4-2. FLASH Program and Erase Flowchart 4.4.
Chapter 4 Memory The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time.
Chapter 4 Memory 4.4.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
Chapter 4 Memory NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xDE must be programmed into NVPROT to protect addresses 0xE000 through 0xFFFF. FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 A15 A14 A13 A12 A11 A10 A9 1 1 1 1 1 1 1 1 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 4-4. Block Protection Mechanism One use for block protection is to block protect an area of FLASH memory for a bootloader program.
Chapter 4 Memory makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure.
Chapter 4 Memory 4.6 FLASH Registers and Control Bits The FLASH module consists of high-page including nonvolatile registers that are copied into corresponding high-page control registers at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and Table 4-4 for the absolute address assignments for all FLASH registers. This section refers to registers and control bits only by their names.
Chapter 4 Memory Table 4-7. FLASH Clock Divider Settings fBus PRDIV8 (Binary) DIV5:DIV0 (Decimal) fFCLK Program/Erase Timing Pulse (5 μs Min, 6.7 μs Max) 20 MHz 1 12 192.3 kHz 5.2 μs 10 MHz 0 49 200 kHz 5 μs 8 MHz 0 39 200 kHz 5 μs 4 MHz 0 19 200 kHz 5 μs 2 MHz 0 9 200 kHz 5 μs 1 MHz 0 4 200 kHz 5 μs 200 kHz 0 0 200 kHz 5 μs 150 kHz 0 0 150 kHz 6.7 μs 4.6.
Chapter 4 Memory Table 4-9. Security States 1 4.6.3 SEC01:SEC00 Description 0:0 secure 1 0:1 secure 1:0 unsecured 1:1 secure The 0:1 bit pattern is the recommended value to be used since it requires two bit changes before going to the unsecured state. FLASH Configuration Register (FCNFG) Bits 7 through 5 may be read or written at any time. Bits 4 through 0 always read 0 and cannot be written.
Chapter 4 Memory FLASH block must first be unprotected, then 0xFFBD in the flash configuration field must be reprogrammed. 7 6 5 4 3 2 1 0 R FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1 FPDIS W (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Reset This register is loaded from nonvolatile location NVPROT during reset. = Unimplemented or Reserved Figure 4-8. FLASH Protection Register (FPROT) 1 If FPDIS is set, these bits are writeable in user mode.
Chapter 4 Memory 4.6.5 FLASH Status Register (FSTAT) Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits that can be read at any time. Writes to these bits have special meanings that are discussed in the bit descriptions. 7 R 6 5 4 FPVIOL FACCERR 0 0 FCCF FCBEF 3 2 1 0 0 FBLANK 0 0 0 0 0 0 W Reset 1 1 = Unimplemented or Reserved Figure 4-9. FLASH Status Register (FSTAT) Table 4-12.
Chapter 4 Memory 4.6.6 FLASH Command Register (FCMD) Only five command codes are recognized in normal user modes as shown in Table 4-14. Refer to Section 4.4.3, “Program and Erase Command Execution” for a detailed discussion of FLASH programming and erase operations. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FCMD7 FCMD6 FCMD5 FCMD4 FCMD3 FCMD2 FCMD1 FCMD0 0 0 0 0 0 0 0 0 Reset Figure 4-10. FLASH Command Register (FCMD) Table 4-13.
Chapter 4 Memory MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 5 Resets, Interrupts, and System Configuration 5.1 Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08LC60 Series. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data manual. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
Chapter 5 Resets, Interrupts, and System Configuration • • • • Illegal opcode detect Background debug forced reset External pin reset (PIN) — can be disabled using RSTPE in SOPT2 Clock generator loss of lock and loss of clock reset Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register.
Chapter 5 Resets, Interrupts, and System Configuration Even if the application will use the reset default settings of COPE, COPCLKS and COPT, the user must write to the write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings. That way, they cannot be changed accidentally if the application program gets lost. The initial writes to SOPT1 and SOPT2 will reset the COP counter.
Chapter 5 Resets, Interrupts, and System Configuration The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the stack. NOTE For compatibility with the M68HC08, the H register is not automatically saved and restored.
Chapter 5 Resets, Interrupts, and System Configuration 5.5.2 External Interrupt Request (IRQ) Pin External interrupts are managed by the IRQSC status and control register. When the IRQ function is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled) can wake the MCU. 5.5.2.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-2.
Chapter 5 Resets, Interrupts, and System Configuration 5.6 Low-Voltage Detect (LVD) System The MC9S08LC60 Series includes a system to protect against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system comprises a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (VLVDH) or low (VLVDL).
Chapter 5 Resets, Interrupts, and System Configuration The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control value (RTIS) used to select one of seven wakeup periods. The RTI has a local interrupt enable, RTIE, to allow masking of the real-time interrupt. The RTI can be disabled by writing each bit of RTIS to zeroes, and no interrupts will be generated. See Section 5.8.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-3. IRQSC Field Descriptions (continued) Field Description 4 IRQPE IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set, the IRQ pin can be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down resistor is enabled depending on the state of the IRQMOD bit. 0 IRQ pin function is disabled. 1 IRQ pin function is enabled.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.2 System Reset Status Register (SRS) This register includes six read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.3 System Background Debug Force Reset Register (SBDFR) This register contains a single write-only control bit. A serial background command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x0000.
Chapter 5 Resets, Interrupts, and System Configuration Table 5-6. SOPT1 Field Descriptions Field Description 7 COPE COP Watchdog Enable — This write-once bit defaults to 1 after reset. 0 COP watchdog timer disabled. 1 COP watchdog timer enabled (force reset on timeout). 6 COPT COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. COPT along with COPCLKS in SOPT2 defines the COP timeout period. 0 Short timeout period selected. 1 Long timeout period selected.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.6 System Device Identification Register (SDIDH, SDIDL) This read-only register is included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.7 System Real-Time Interrupt Status and Control Register (SRTISC) This register contains one read-only status flag, one write-only acknowledge bit, three read/write delay selects, and one unimplemented bit, which always reads 0. R 7 6 RTIF 0 W 5 4 RTICLKS RTIE 0 0 3 2 1 0 RTIS2 RTIS1 RTIS0 0 0 0 0 RTIACK Reset 0 0 0 = Unimplemented or Reserved Figure 5-9. System RTI Status and Control Register (SRTISC) Table 5-10.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.8 System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip voltage, see Table 5-14 for the LVDV bit description in SPMSC3.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.9 System Power Management Status and Control 2 Register (SPMSC2) This register is used to configure the stop mode behavior of the MCU. For more information concerning partial power down mode, see Section 3.6, “Stop Modes.” R 7 6 5 4 3 2 0 0 0 PDF PPDF 0 W Reset 1 0 PDC1 PPDC1 0 0 PPDACK 0 0 0 0 0 0 = Unimplemented or Reserved 1 This bit can be written only one time after reset. Additional writes are ignored.
Chapter 5 Resets, Interrupts, and System Configuration 5.8.10 System Power Management Status and Control 3 Register (SPMSC3) This register is used to report the status of the low voltage warning function behavior of the MCU.
Chapter 5 Resets, Interrupts, and System Configuration MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 6 Parallel Input/Output This section explains software controls related to parallel input/output (I/O). The MC9S08LC60 Series has three I/O ports which include a total of up to 24 general-purpose I/O pins (pin availability depends on device and package option, see Table 1-2 for details). See Chapter 2, “Pins and Connections,” for more information about the logic and hardware aspects of these pins.
Chapter 6 Parallel Input/Output PTxDDn D OUTPUT ENABLE Q PTxDn D Q OUTPUT DATA 1 PORT READ DATA 0 SYNCHRONIZER INPUT DATA BUSCLK Figure 6-1. Parallel I/O Block Diagram The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output-only pin.
Chapter 6 Parallel Input/Output 6.1 Pin Behavior in Stop Modes Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An explanation of pin behavior for the various stop modes follows: • In stop1 mode, all internal registers including parallel I/O control and data registers are powered off. Each of the pins assumes its default reset state (output buffer and internal pullup disabled).
Chapter 6 Parallel Input/Output 6.2.1.1 Port A Data Registers (PTAD) Port A parallel I/O function is controlled by the data and data direction registers in this section. 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-2. Port A Data Register (PTAD) Table 6-1. PTAD Field Descriptions Field Description 7:0 PTAD[7:0] Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin.
Chapter 6 Parallel Input/Output 6.2.2 Port A Control Registers Associated with the parallel I/O ports is a set of registers located in the high page register space that operate independently of the parallel I/O registers. These registers are used to control pullups, slew rate, and drive strength for the associated pins and may be used in conjunction with the peripheral functions on these pins for most modules. The pins associated with port A are controlled by the registers in this section.
Chapter 6 Parallel Input/Output 6.2.2.2 Output Slew Rate Control Enable (PTASE) Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control register (PTASEn). When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
Chapter 6 Parallel Input/Output 6.2.3 Port B Registers This section provides information about all registers and control bits associated with the parallel I/O ports. The parallel I/O registers are located in page zero of the memory map. Refer to tables in Chapter 4, “Memory” for the absolute address assignments for all parallel I/O registers. This section refers to registers and control bits only by their names.
Chapter 6 Parallel Input/Output 6.2.3.2 Port B Data Direction Registers (PTBDD) 7 6 5 4 3 2 1 0 PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD21 PTBDD1 PTBDD0 0 0 0 0 0 0 0 0 R W Reset Figure 6-13. Data Direction for Port B (PTBDD) 1 PTBDD2 has no effect on the output-only PTB2 pin. Table 6-7. PTBDD Field Descriptions Field Description 7:0 Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for PTBDD[7:0] PTBD reads.
Chapter 6 Parallel Input/Output 7 6 5 4 3 2 1 0 PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0 0 0 0 0 0 0 0 R W Reset Figure 6-15. Pullup Enable for Port B (PTBPE) Table 6-8. PTBPE Field Descriptions Field Description 7:0 Pullup Enable for Port B Bits — For port B pins that are inputs, these read/write control bits determine whether PTBPE[7:0] internal pullup devices are enabled provided the corresponding PTBDDn is 0.
Chapter 6 Parallel Input/Output 6.2.4.3 Output Drive Strength Select (PTBDS) An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (PTBDSn). When high drive is selected a pin is capable of sourcing and sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that the total current source and sink limits for the chip are not exceeded.
Chapter 6 Parallel Input/Output 6.2.5.1 Port C Data Registers (PTCD) Port C parallel I/O function is controlled by the data and data direction registers in this section. R 7 6 5 4 3 2 1 0 PTCD71 PTCD62 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0 0 0 0 0 0 0 0 0 W Reset Figure 6-18.
Chapter 6 Parallel Input/Output strength for the associated pins and may be used in conjunction with the peripheral functions on these pins for most modules. The pins associated with Port C are controlled by the registers in this section. These registers control the pin pullup, slew rate and drive strength of the Port C pins independent of the parallel I/O registers. 6.2.6.
Chapter 6 Parallel Input/Output 6.2.6.2 Output Slew Rate Control Enable (PTCSE) Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control register (PTCSEn). When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
Chapter 6 Parallel Input/Output R 7 6 5 4 3 2 1 0 PTCDS71 PTCDS62 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0 0 0 0 0 0 0 0 0 W Reset Figure 6-25. Drive Strength Selection for Port C (PTCDS) 1 2 PTCDS7 has no effect on the input-only PTC7 pin. PTCDD6 has no effect on the output-only PTC6 pin. Table 6-15.
Chapter 7 Keyboard Interrupt (S08KBIV2) 7.1 Introduction This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was designed to simplify the connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external interrupt inputs and as an external means of waking up the MCU from stop or wait low-power modes. The KBI module allows up to eight pins to act as additional interrupt sources.
Chapter 7 Keyboard Interrupt (S08KBIV2) HCS08 CORE INT ADP[7:4] ADP3 ADP2 ADP1 ADP0 4 BKGD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) BKP HCS08 SYSTEM CONTROL RTI COP IRQ LVD ANALOG COMPARATOR (ACMP) 8-BIT KEYBOARD INTERRUPT (KBI1) USER FLASH A (LC60 = 32,768 BYTES) (LC36 = 24,576 BYTES) SERIAL PERIPHERAL INTERFACE (SPI1) PTA3/KBI1P3/ADP3/ACMP– ACMP+ PTA2/KBI1P2/ADP2/ACMP+ 8 PTA[1:0]/KBI1P[1:0]/ADP[1:0] SS1 SPSCK1 MISO1 PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 MOSI1 SCL IIC MODULE (IIC) USER
Chapter 7 Keyboard Interrupt (S08KBIV2) 7.1.1 Features The KBI features include: • Up to eight keyboard interrupt pins with individual pin enable bits. • Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. • One software enabled keyboard interrupt. • Exit from low-power modes. 7.1.
Chapter 7 Keyboard Interrupt (S08KBIV2) BUSCLK KBACK VDD 1 KBIxP0 0 S RESET KBF D CLR Q KBIPE0 SYNCHRONIZER CK KBEDG0 KEYBOARD INTERRUPT FF 1 KBIxPn 0 S STOP STOP BYPASS KBIx INTERRUPT REQUEST KBMOD KBIPEn KBIE KBEDGn Figure 7-2. Keyboard Interrupt (KBI) Block Diagram 7.2 External Signal Description The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests.
Chapter 7 Keyboard Interrupt (S08KBIV2) 7.3 Register Definition The KBI includes three registers: • An 8-bit pin status and control register. • An 8-bit pin enable register. • An 8-bit edge select register. Refer to the direct-page register summary in the Memory chapter for the absolute address assignments for all KBI registers. This section refers to registers and control bits only by their names and relative address offsets.
Chapter 7 Keyboard Interrupt (S08KBIV2) 7 6 5 4 3 2 1 0 KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0 0 0 0 0 0 0 0 0 R W Reset: Figure 7-4. KBIx Pin Enable Register Table 7-3. KBIxPE Register Field Descriptions Field Description 7:0 KBIPEn 7.3.3 Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin. 0 Pin not enabled as keyboard interrupt. 1 Pin enabled as keyboard interrupt.
Chapter 7 Keyboard Interrupt (S08KBIV2) Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs must be at the deasserted logic level. A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. 7.4.
Chapter 7 Keyboard Interrupt (S08KBIV2) MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 8 Central Processor Unit (S08CPUV2) 8.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Chapter 8 Central Processor Unit (S08CPUV2) 8.2 Programmer’s Model and CPU Registers Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 X 0 SP STACK POINTER 0 15 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-1. CPU Registers 8.2.
Chapter 8 Central Processor Unit (S08CPUV2) 8.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
Chapter 8 Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-2. Condition Code Register Table 8-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
Chapter 8 Central Processor Unit (S08CPUV2) 8.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
Chapter 8 Central Processor Unit (S08CPUV2) 8.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 8.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 8.3.6.
Chapter 8 Central Processor Unit (S08CPUV2) 8.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 8.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
Chapter 8 Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence.
Chapter 8 Central Processor Unit (S08CPUV2) 8.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.
Chapter 8 Central Processor Unit (S08CPUV2) 8.5 HCS08 Instruction Set Summary Instruction Set Summary Nomenclature The nomenclature listed here is used in the instruction descriptions in Table 8-2.
Chapter 8 Central Processor Unit (S08CPUV2) 0 1 U = = = = Bit forced to 0 Bit forced to 1 Bit set or cleared according to results of operation Undefined after the operation Machine coding notation dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00) ee = Upper 8 bits of 16-bit offset ff = Lower 8 bits of 16-bit offset or 8-bit offset ii = One byte of immediate data jj = High-order byte of a 16-bit immediate data value kk = Low-order byte of a 16-bit immediate data value
Chapter 8 Central Processor Unit (S08CPUV2) IX IX+ IX1 IX1+ = = = = IX2 REL SP1 SP2 = = = = 16-bit indexed no offset 16-bit indexed no offset, post increment (CBEQ and MOV only) 16-bit indexed with 8-bit offset from H:X 16-bit indexed with 8-bit offset, post increment (CBEQ only) 16-bit indexed with 16-bit offset from H:X 8-bit relative offset Stack pointer with 8-bit offset Stack pointer with 16-bit offset Description V H I N Z C ADC ADC ADC ADC ADC ADC ADC ADC ADD ADD ADD ADD ADD ADD ADD ADD #opr8
Chapter 8 Central Processor Unit (S08CPUV2) V H I N Z C DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – – DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd Bus Cycles1 Description Operand Operation Opcode Effect on CCR Source Form Address Mode Table 8-2.
Chapter 8 Central Processor Unit (S08CPUV2) V H I N Z C BRCLR n,opr8a,rel Branch if Bit n in Memory Clear Branch if (Mn) = 0 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – ↕ DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) BRN rel Branch Never Uses 3 Bus Cycles – – – – – – REL 21 rr Branch if (Mn) = 1 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – ↕ DIR DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd dd dd dd dd dd dd dd Mn ← 1 DIR (b0) DIR (b1) DIR (b2) (b3) – – – – – – DIR DIR (b4) DIR (b5) DI
Chapter 8 Central Processor Unit (S08CPUV2) V H I N Z C CPX CPX CPX CPX CPX CPX CPX CPX #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP DAA DBNZ opr8a,rel DBNZA rel DBNZX rel DBNZ oprx8,X,rel DBNZ ,X,rel DBNZ oprx8,SP,rel DEC opr8a DECA DECX DEC oprx8,X DEC ,X DEC oprx8,SP DIV EOR #opr8i EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP JMP opr8a JMP opr16a JMP oprx16,X JMP oprx8,X JMP ,X JSR opr8a JSR opr16a JSR
Chapter 8 Central Processor Unit (S08CPUV2) V H I N Z C LDX #opr8i LDX opr8a LDX opr16a LDX oprx16,X LDX oprx8,X LDX ,X LDX oprx16,SP LDX oprx8,SP LSL opr8a LSLA LSLX LSL oprx8,X LSL ,X LSL oprx8,SP LSR opr8a LSRA LSRX LSR oprx8,X LSR ,X LSR oprx8,SP Load X (Index Register Low) from Memory Logical Shift Left (Same as ASL) Logical Shift Right X ← (M) 0 – – ↕ C 0 b7 0 C b7 b0 (M)destination ← (M)source MOV opr8a,opr8a MOV opr8a,X+ MOV #opr8i,opr8a MOV ,X+,opr8a Move MUL Unsigned multiply ↕ –
Chapter 8 Central Processor Unit (S08CPUV2) V H I N Z C ROR opr8a RORA RORX ROR oprx8,X ROR ,X ROR oprx8,SP Rotate Right through Carry RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine SBC SBC SBC SBC SBC SBC SBC SBC #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP SEC SEI STA STA STA STA STA STA STA opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Subtract with Carry I←1 STOP Enable Interrupts: Stop Processing Refer to MCU Documentation SWI A ← (A)
Chapter 8 Central Processor Unit (S08CPUV2) Description V H I N Z C TAP TAX TPA Transfer Accumulator to CCR Transfer Accumulator to X (Index Register Low) Transfer CCR to Accumulator CCR ← (A) ↕ ↕ ↕ ↕ ↕ Bus Cycles1 Operation Operand Effect on CCR Opcode Source Form Address Mode Table 8-2.
Chapter 8 Central Processor Unit (S08CPUV2) Table 8-3.
Chapter 8 Central Processor Unit (S08CPUV2) Table 8-3.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.1 Introduction The LCD driver module is a CMOS charge pump voltage inverter that is designed for low-voltage, low-power operation. The LCD driver module is designed to generate the appropriate waveforms to drive multiplexed numeric, alpha-numeric, or custom LCD panels. Depending on LCD module hardware and software configuration, the LCD panels can be either 3 V or 5 V and be driven by different waveform modes.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) HCS08 CORE INT ADP[7:4] ADP3 ADP2 ADP1 ADP0 4 BKGD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) BKP HCS08 SYSTEM CONTROL RTI COP IRQ LVD ANALOG COMPARATOR (ACMP) 8-BIT KEYBOARD INTERRUPT (KBI1) USER FLASH A (LC60 = 32,768 BYTES) (LC36 = 24,576 BYTES) SERIAL PERIPHERAL INTERFACE (SPI1) PTA3/KBI1P3/ADP3/ACMP– ACMP+ PTA2/KBI1P2/ADP2/ACMP+ 8 PTA[1:0]/KBI1P[1:0]/ADP[1:0] SS1 SPSCK1 MISO1 PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 MOSI1 SCL IIC MODULE
Chapter 9 Liquid Crystal Display (S08LCDV1) 9.1.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-2. Modes of Operation (continued) Mode Operation Stop3 Depending on the state of the LCDSTP3 bit, the LCD module can operate an LCD panel in stop3 mode. If LCDSTP3 = 1, LCD module clock generation is turned off and the LCD module enters a power conservation state.If LCDSTP3 = 0, the LCD module can operate an LCD panel in stop3, and the LCD module continues to display the current LCD panel contents base on the LCDRAM registers.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.2 External Signal Description The LCD module has several external pins dedicated to power supply and also LCD frontplane/backplane signaling. Table 9-3 itemizes all the LCD external pins. See the Pins and Connections chapter for device-specific pin configurations. Table 9-3.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.2.6 Vcap1, Vcap2 The charge pump capacitor is used to transfer charge from the input supply to the regulated output. It is recommended that a low equivalent series resistance (ESR) capacitor be used. Proper orientation is imperative when using a polarized capacitor. 9.3 Register Definition This section consists of register descriptions. Each description includes a standard register diagram.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-4. LCDCR0 Field Descriptions (continued) Field Description 5:3 LCLK[2:0] LCD Clock Prescaler — The LCD module clock prescaler bits are used as a clock divider to generate the LCD waveform base clock as shown in Equation 9-1. The waveform base clock is used, with the LCD module duty cycle configuration to determine the LCD module frame frequency.LCD module frame frequency calculations are provided in 9.4.1.3/p.139. Eqn.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.3.3 LCD Frontplane Enable Registers 0–5 (FPENR0–FPENR5) When LCDEN = 1, these bits enable the frontplane output waveform on the corresponding frontplane pin.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.3.4 LCDRAM Registers (LCDRAM) The LCDRAM registers control the on/off state for frontplane drivers or the blink enables/disables for each individual LCD segment depending on the state of the LCDDRMS bit in the LCDCMD register. After reset the LCDRAM contents will be indeterminate (I), as indicated by Figure 9-5.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) R FP23BP3 FP23BP2 FP23BP1 FP23BP0 FP22BP3 FP22BP2 FP22BP1 FP22BP0 I I I I I I I I FP25BP3 FP25BP2 FP25BP1 FP25BP0 FP24BP3 FP24BP2 FP24BP1 FP24BP0 I I I I I I I I FP27BP3 FP27BP2 FP27BP1 FP27BP0 FP26BP3 FP26BP2 FP26BP1 FP26BP0 I I I I I I I I FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP2 FP28BP1 FP28BP0 I I I I I I I I FP31BP3 FP31BP2 FP31BP1 FP31BP0 FP30BP3 FP30BP2 FP30BP1 FP30BP0 I
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.3.4.1 LCDRAM Registers as On/Off Selector (LCDDRMS = 0) If LCDDRMS bit in the LCDCMD register is deasserted, the LCDRAM register accesses a register bank that controls the on/off state for frontplane drivers. Table 9-7.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-9. LCDCLKS Field Descriptions Field Description 7 SOURCE LCD Clock Source Select — The LCD module has two possible clock sources. This bit is used to select which clock source is the basis for LCDCLK. 0 Selects the ICGERCLK (external clock reference) as the LCD clock source. 1 Selects the ICGOUT/2 (bus clock) as the LCD clock source. 6 DIV16 LCD Clock Prescaler Enable— Enable prescaler by 16. 0 LCD clock prescaler is disabled.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-10. LCDSUPPLY Field Descriptions (continued) Field Description 5:4 CPCADJ[1:0] LCD Module Charge Pump Clock Adjust- Adjust the clock source for the charge pump Charge Pump Clock Rate = LCDCLK / (6 × 2(CPADJ[1:0] +1) ) 00 01 10 11 Eqn. 9-3 Configures for 2728 Hz charge pump frequency (LCDCLK = 32.768khz) Configures for 1364 Hz charge pump frequency (LCDCLK = 32.768khz) Configures for 682 Hz charge pump frequency (LCDCLK = 32.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-11. LCDBCTL Field Descriptions Field Description 7 BLINK Blink Command — Starts or stops LCD module blinking.The blink command takes effect at the beginning of the next LCD frame cycle. 0 Disables blinking. 1 Starts blinking at blinking frequency specified by LCD blink rate calculation (see Equation 9-4).
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-12. LCDCMD Field Descriptions Field Description 1 LCDCLR LCD Data Register Clear Command — Deasserts all accessible bits in the LCDRAM registers. To clear all LCD segment blink enables in the LCDRAM registers, the LCDCLR bit must be asserted only while LCDDRMS = 1.To clear the entire LCD display, the LCDCLR bit must be asserted only while LCDDRMS = 0. 0 Contents of LCD data register are not deasserted by hardware.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.1 LCD Driver Description The LCD module driver has three modes of operation: • 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels) • 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels) • 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels) Note all modes are 1/3 bias. These modes of operation are described in more detail in the following sections. 9.4.1.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.1.2 LCD Bias Because a single frontplane driver is configured to drive more and more individual LCD segments, more voltage levels are required to generate the appropriate waveforms to drive the segment. The LCD module is designed to operate using the 1/3 bias mode. Defined by Equation 9-5, the bias indicates the number of voltage levels used to power the LCD display. 1 / (voltage level – 1) 9.4.1.3 Eqn.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-14. LCDCLK Calculations (only bold/unshaded values are valid) Selected Clock Frequencies in kHz (NOTE: DIV16 = 0) CLKADJ[5:0] +1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Selected Clock Frequencies in kHz (NOTE: DIV16 = 1) 32.8 100 200 300 400 500 2000 4000 9980 16000 18886 20000 32.8 16.4 10.9 8.2 6.6 5.5 4.7 4.1 3.6 3.3 3.0 2.7 2.5 2.3 2.2 2.0 1.9 1.8 1.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) The value of LCDCLK is important because it is used to generate the LCD module waveform base clock frequency. Equation 9-1 provides an expression for the LCD module waveform base clock frequency calculation. Equation 9-1 illustrates that the LCD module waveform base clock frequency also depends on the LCLK[2:0] bit field. The LCD module waveform base clock is the basis for the calculation of the LCD module frame frequency.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-16. Configurations for Example LCD Waveforms Bias Mode DUTY[1:0] Duty Cycle LPWAVE bit Example 1 01 1/2 0 Example 2 01 1/2 1 10 1/3 0 Example 4 10 1/3 1 Example 5 11 1/4 0 Example 6 11 1/4 1 Example 3 1/3 MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.1.4.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.1.4.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.1.4.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.1.4.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.1.4.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.1.4.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.2 LCDRAM Registers For a segment on the LCD panel to be displayed, data must be written to the LCDRAM registers. Each bit in the LCDRAM registers correspond to a segment on the LCD panel. The LCDRAM registers provide access to two different register groups depending on the state of the LCDDRMS bit in the LCDCMD register. If LCDDRMS = 0, the LCDRAM register accesses a register bank that controls the on/off state for frontplane drivers.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.3.1 LCD Segment Blinking To configure all LCD segments to blink regardless of the contents of the LCDRAM bits while LCDDRMS = 1, the BLKMODE bit in the LCDBCTL control register must to set to 1. To configure individual LCD segments to blink, the BLKMODE bit in the LCDBCTL control register must be deasserted.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) VDD powersw1 VLCD powersw2 LCDCPMS (BBYPASS & powersw3) R1 + ~(LCDCPMS) R1 VLL1 – (~(BBYPASS) & powersw3) R1 (~(LCDCPMS) & powersw3) VOLTAGE DIVIDER BLOCK VSUPPLY[1:0] powersw1 powersw2 powersw3 00 1 0 0 01 0 1 0 10 0 0 1 11 0 0 0 VLL1 CHARGE PUMP VLL2 VLL3 Figure 9-17. LCD Charge Pump and VLCD Voltage Divider Block Diagram Figure 9-17 also illustrates a buffer, a voltage follower with an ideal op amp.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.4.1 LCD Charge Pump and Voltage Divider The LCD charge pump is a voltage tripler. Using the voltage divider and the charge pump, the LCD module can effectively double or triple VLCD. This LCD module configurability makes the LCD module compatible with both 3-V or 5-V LCD glass. The LCD module charge pump mode select bit (LCDCPMS) in the LCDSUPPLY register configures the LCD module operational mode as a voltage doubler or a voltage tripler.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.4.4.2 LCD Power Supply and Voltage Buffer Configuration The LCD power supply can be internally derived from VDD or it can be externally derived from a voltage source in the range between 0.9 to 1.8 Volts that is applied to the VLCD pin. The Table below provides a more detailed description of the power state of the LCD module which depends on the configuration of the VSUPPLY[1:0], LCDCPMS, BBYPASS, and LCDCPEN bits.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) The output of the voltage divider block is VLL1. VLL1 is connected to the internal charge pump via the Vref. Using the charge pump, the value of VLL1 is tripled and outputted as VLL3. VLL3, a LCD bias voltage, is equal to the voltage required to energize the LCD panel, VLCDON. For 3-V LCD glass, VLL3 should be approximately 3-V; while for 5-V LCD glass, VLL3 should be approximately 5-V.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-20. VDD Switch Option VSUPPLY[1:0] 9.4.5 VDD Switch Option Recommend Use for 3-V Recommend Use for 5-V LCD Panels LCD Panels 00 VLL2 is generated from VDD • VLL1 = 1v • VDD = VLL2 = 2v • VLL3 = 3v • VLL1 = 1.67v • VDD = VLL2 = 3.3v • VLL3 = 5v 01 VLL3 is generated from VDD • VLL1 = 1v • VLL2 = 2v • VDD = VLL3 = 3v Invalid LCD power configuration Resets During a reset, the LCD module system is configured in the default mode.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.5.1 Initialization Sequence The list below provides a recommended initialization sequence for the LCD module. 1. LCDCLKS register a) Configure LCD clock source (SOURCE bit) b) Adjust the clock source to achieve a value for LCDCLK of ~ 32 kHz (CLKADJ[5:0] & DIV16) 2.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.5.2 Initialization Examples This section provides initialization information for configuration of the LCD. Each example details the register and bit field values required in order to achieve the appropriate LCD configuration for a given LCD application scenario. Table 9-21 lists each example and the setup requirements. Table 9-21.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.5.2.1 Initialization Example 1 Example 1 LCD setup requirements are reiterated in the following table: Example 1 LCD Glass Operating LCD Clock Operating Voltage, Source Voltage VDD 1.8-V External 32.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.5.2.2 Initialization Example 2 Example 2 LCD setup requirements are reiterated in the following table: Example 2 LCD Glass Operating LCD Clock Operating Voltage, Source Voltage VDD 3.6-V Internal 100 kHz 3-V Required LCD segments 99 LCD Frame Rate Blinking Mode/Rate 80 Hz Individual segment 0.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) Table 9-23. Initialization Register Values for Example 2 (continued) Register Bit/bit field Binary Value LCDBCTL 0XXX0100 BLKMODE 0 BRATE[2:0] 100 FPENR[5:0] FPENR0 FPENR1 FPENR2 FPENR3 FPENR4 FPENR5 Comment Blink individual segments; Blink Segments = 0; Blink All = 1 Using the LCD base frequency for the selected LCD frame frequency, select 0.5 Hz blink frequency (see table 9-15). 11111111 Only 33 Frontplanes need to be enabled.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.5.2.3 Initialization Example 3 Example 3 LCD setup requirements are reiterated in the table below: Example 3 LCD Glass Operating LCD Clock Operating Voltage, Source Voltage VDD 3.6-V Internal 18886 kHz 5-V Required LCD segments 160 LCD Frame Rate Blinking Mode/Rate 60 Hz Individual segment 2.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.5.2.4 Initialization Example 4 Example 3 LCD setup requirements are reiterated in the table below: Example 4 LCD Glass Operating LCD Clock Operating Voltage, Source Voltage VDD 1.8-V External 32.768 kHz 5-V Required LCD segments LCD Frame Rate 123 30 Hz Blinking Mode/Rate Behavior in STOP3 and WAIT modes LCD Power Input all segment 2.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.6 Application Information Figure 9-18 is a programmer’s model of the LCD module. The programmer’s model groups the LCD module register bit and bit field into functional groups. The model is a very high level illustration of the LCD module showing the module’s functional hierarchy including initialization and runtime control.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) FP CONNECTION a f e g d BP CONNECTION a b f c e BP0 (a, b COMMONED) b g BP1 (c, f, g COMMONED) c d BP2 (d, e COMMONED) FP2 (b, c COMMONED) FP1 (a, d, g COMMONED) FP0 (e, f COMMONED) The segment assignments for each bit in the data registers are: LDAT1 0x0052 F1B3 F1B2 F1B1 F1B0 F0B3 F0B2 F0B1 F0B0 — d g a — e f — FP1 LDAT2 0x0053 FP0 F3B3 F3B2 F3B1 F3B0 F2B3 F2B2 F2B1 F2B0 — — — — — — c b FP2 To display the
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.6.1.1 LCD Module Waveforms DUTY = 1/3 1FRAME BP0 V3 V2 V1 V0 — — — F0B2 F0B1 F0B0 0 1 0 F1B2 F1B1 F1B0 0 1 0 F2B2 F2B1 F2B0 0 1 1 BP1 V3 V2 V1 V0 BP2 V3 V2 V1 V0 FP0 V3 V2 V1 V0 FP1 V3 V2 V1 V0 FP2 V3 V2 V1 V0 Figure 9-20. LCD Waveforms (LPWAVE = 0) MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) 9.6.1.2 Segment On Driving Waveform The voltage waveform across the “f” segment of the LCD (between BP1 and FP0) is illustrated in Figure 9-21. As shown in the waveform, the voltage level reaches the value V3 therefore the segment will be on. +V3 +V2 +V1 BP1–FP0 V0 –V1 –V2 –V3 Figure 9-21. “f” Segment Voltage Waveform 9.6.1.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) NOTE: Contrast control configuration when LCD is powered using external VLCD LCD GLASS PANEL FP[40:0] This is the recommended configuration for contrast control. BP[3:0] LCD Power Supply 9S08LC60 VLCD specified between 0.9 and 1.8 volts. VLCD VLL3 R LCD Power Pins VLL2 VLL1 CBYLCD Vcap1 Vcap2 CLCD LCD charge pump capacitance Figure 9-23. Power Connections for Contrast Control 9.6.
Chapter 9 Liquid Crystal Display Driver (S08LCDV1) MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 10 Internal Clock Generator (S08ICGV4) Chapter 10 Internal Clock Generator (S08ICGV4) 10.1 Introduction The ICG module is used to generate the system clocks for the MC9S08LC60/36/20 MCU. Figure 10-1 shows the clock distribution for the MC9S08LC60/36/20 MCU. Electrical parametric data for the ICG may be found in Appendix.
Chapter 10 Internal Clock Generator (S08ICGV4) HCS08 CORE INT ADP[7:4] ADP3 ADP2 ADP1 ADP0 4 BKGD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) BKP HCS08 SYSTEM CONTROL RTI COP IRQ LVD ANALOG COMPARATOR (ACMP) 8-BIT KEYBOARD INTERRUPT (KBI1) USER FLASH A (LC60 = 32,768 BYTES) (LC36 = 24,576 BYTES) SERIAL PERIPHERAL INTERFACE (SPI1) PTA3/KBI1P3/ADP3/ACMP– ACMP+ PTA2/KBI1P2/ADP2/ACMP+ 8 PTA[1:0]/KBI1P[1:0]/ADP[1:0] SS1 SPSCK1 MISO1 PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 MOSI1 SCL IIC MODULE (IIC
Chapter 10 Internal Clock Generator (S08ICGV4) 10.2 Introduction The ICG provides multiple options for clock sources. This offers a user great flexibility when making choices between cost, precision, current draw, and performance. As seen in Figure 10-3, the ICG consists of four functional blocks. Each of these is briefly described here and then in more detail in a later section. • Oscillator block — The oscillator block provides means for connecting an external crystal or resonator.
Chapter 10 Internal Clock Generator (S08ICGV4) • • • • • • • Digitally-controlled oscillator (DCO) preserves previous frequency settings, allowing fast frequency lock when recovering from stop3 mode DCO will maintain operating frequency during a loss or removal of reference clock Post-FLL divider selects 1 of 8 bus rate divisors (/1 through /128) Separate self-clocked source for real-time interrupt Trimmable internal clock source supports SCI communications without additional external components Automatic
Chapter 10 Internal Clock Generator (S08ICGV4) 10.2.3 Block Diagram Figure 10-3 is a top-level diagram that shows the functional organization of the internal clock generation (ICG) module. This section includes a general description and a feature list.
Chapter 10 Internal Clock Generator (S08ICGV4) selected, this pin is not used by the ICG. The oscillator is capable of being configured to provide a higher amplitude output for improved noise immunity. This mode of operation is selected by HGO = 1. 10.3.3 External Clock Connections If an external clock is used, then the pins are connected as shown Figure 10-4. ICG EXTAL XTAL VSS NOT CONNECTED CLOCK INPUT Figure 10-4. External Clock Connections 10.3.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.4 Register Definition Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all ICG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 10.4.
Chapter 10 Internal Clock Generator (S08ICGV4) Table 10-1. ICGC1 Register Field Descriptions (continued) Field 2 OSCSTEN 1 LOCD Description Enable Oscillator in Off Mode — The OSCSTEN bit controls whether or not the oscillator circuit remains enabled when the ICG enters off mode. This bit has no effect if HGO = 1 and RANGE = 1. 0 Oscillator disabled when ICG is in off mode unless ENABLE is high, CLKS = 10, and REFST = 1. 1 Oscillator enabled when ICG is in off mode, CLKS = 1X and REFST = 1.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.4.2 ICG Control Register 2 (ICGC2) 7 6 5 4 3 2 1 0 R LOLRE MFD LOCRE RFD W Reset 0 0 0 0 0 0 0 0 Figure 10-7. ICG Control Register 2 (ICGC2) Table 10-2. ICGC2 Register Field Descriptions Field Description 7 LOLRE Loss of Lock Reset Enable — The LOLRE bit determines what type of request is made by the ICG following a loss of lock indication. The LOLRE bit only has an effect when LOLS is set.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.4.3 ICG Status Register 1 (ICGS1) 7 R 6 CLKST 5 4 3 2 1 0 REFST LOLS LOCK LOCS ERCS ICGIF W Reset 1 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 10-8. ICG Status Register 1 (ICGS1) Table 10-3. ICGS1 Register Field Descriptions Field Description 7:6 CLKST Clock Mode Status — The CLKST bits indicate the current clock mode.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.4.4 R ICG Status Register 2 (ICGS2) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 DCOS 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 10-9. ICG Status Register 2 (ICGS2) Table 10-4.
Chapter 10 Internal Clock Generator (S08ICGV4) 7 6 5 4 3 2 1 0 0 0 0 0 R FLT W Reset 1 1 0 0 Figure 10-11. ICG Lower Filter Register (ICGFLTL) Table 10-6. ICGFLTL Register Field Descriptions Field Description 7:0 FLT Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00).
Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.1 Off Mode (Off) Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state. However there are two cases to consider when clock activity continues while the CPU is in stop mode, 10.5.1.1 BDM Active When the BDM is enabled, the ICG continues activity as originally programmed. This allows access to memory and control registers via the BDC controller. 10.5.1.
Chapter 10 Internal Clock Generator (S08ICGV4) entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS bits.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.4 FLL Engaged Internal Unlocked FEI unlocked is a temporary state that is entered when FEI is entered and the count error (Δn) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.7.1 FLL Engaged External Unlocked FEE unlocked is entered when FEE is entered and the count error (Δn) output from the subtractor is greater than the maximum nunlock or less than the minimum nunlock, as required by the lock detector to detect the unlock condition. The ICG will remain in this state while the count error (Δn) is greater than the maximum nlock or less than the minimum nlock, as required by the lock detector to detect the lock condition.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.9 FLL Loss-of-Clock Detection The reference clock and the DCO clock are monitored under different conditions (see Table 10-8). Provided the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls below a certain frequency, fLOR and fLOD, respectively, the LOCS status bit will be set to indicate the error.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.10 Clock Mode Requirements A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should be the same as the requested mode in CLKS1:CLKS0. Table 10-9 shows the relationship between CLKS, CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS ≠ CLKST.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.5.11 Fixed Frequency Clock The ICG provides a fixed frequency clock output, XCLK, for use by on-chip peripherals. This output is equal to the internal bus clock, BUSCLK, in all modes except FEE. In FEE mode, XCLK is equal to ICGERCLK ÷ 2 when the following conditions are met: • (P × N) ÷ R ≥ 4 where P is determined by RANGE (see Table 10-11), N and R are determined by MFD and RFD respectively (see Table 10-12). • LOCK = 1.
Chapter 10 Internal Clock Generator (S08ICGV4) Table 10-10. ICG Configuration Consideration Clock Reference Source = Internal 1 Clock Reference Source = External FLL Engaged FEI 4 MHz < fBus < 20 MHz. Medium power (will be less than FEE if oscillator range = high) Good clock accuracy (After IRG is trimmed) Lowest system cost (no external components required) IRG is on. DCO is on.
Chapter 10 Internal Clock Generator (S08ICGV4) Table 10-12. MFD and RFD Decode Table 101 110 111 10.6.2 14 16 18 101 110 111 ÷32 ÷64 ÷128 Example #1: External Crystal = 32 kHz, Bus Frequency = 4.19 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 32 kHz oscillator up to 8.38 MHz to achieve 4.19 MHz bus frequency.
Chapter 10 Internal Clock Generator (S08ICGV4) Bits 11:0 FLT No need for user initialization ICGTRM = $xx Bits 7:0 TRIM Only need to write when trimming internal oscillator; not used when external crystal is clock source Figure 10-14 shows flow charts for three conditions requiring ICG initialization. RESET INITIALIZE ICG ICGC1 = $38 ICGC2 = $00 CHECK FLL LOCK STATUS.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.6.3 Example #2: External Crystal = 4 MHz, Bus Frequency = 20 MHz In this example, the FLL will be used (in FEE mode) to multiply the external 4 MHz oscillator up to 40-MHz to achieve 20 MHz bus frequency. After the MCU is released from reset, the ICG is in self-clocked mode (SCM) and supplies approximately 8 MHz on ICGOUT which corresponds to a 4 MHz bus frequency (fBus).
Chapter 10 Internal Clock Generator (S08ICGV4) RECOVERY FROM STOP RESET INITIALIZE ICG ICGC1 = $7A ICGC2 = $30 CHECK FLL LOCK STATUS LOCK = 1? YES SERVICE INTERRUPT SOURCE (fBus = 4 MHz) NO CHECK FLL LOCK STATUS LOCK = 1? NO YES CONTINUE CONTINUE Figure 10-15. ICG Initialization and Stop Recovery for Example #2 MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.6.4 Example #3: No External Crystal Connection, 5.4 MHz Bus Frequency In this example, the FLL will be used (in FEI mode) to multiply the internal 243 kHz (approximate) reference clock up to 10.8 MHz to achieve 5.4 MHz bus frequency. This system will also use the trim function to fine tune the frequency based on an external reference signal.
Chapter 10 Internal Clock Generator (S08ICGV4) ICGTRM = $xx Bit 7:0 TRIM Only need to write when trimming internal oscillator; done in separate operation (see example #4) RECOVERY FROM STOP RESET INITIALIZE ICG ICGC1 = $28 ICGC2 = $31 CHECK FLL LOCK STATUS. LOCK = 1? CHECK FLL LOCK STATUS. LOCK = 1? NO YES NO CONTINUE YES CONTINUE NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. Figure 10-16.
Chapter 10 Internal Clock Generator (S08ICGV4) 10.6.5 Example #4: Internal Clock Generator Trim The internally generated clock source is guaranteed to have a period ± 25% of the nominal value. In some cases, this may be sufficient accuracy. For other applications that require a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate source. This section outlines one example of trimming the internal oscillator.
Chapter 10 Internal Clock Generator (S08ICGV4) MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 11 Timer Pulse-Width Modulator (S08TPMV2) 11.1 Introduction The TPM uses one input/output (I/O) pin per channel, TPMxCHn where x is the TPM number (for example, 1 or 2) and n is the channel number (for example, 0–4). The TPM shares its I/O pins with general-purpose I/O port pins (refer to the Pins and Connections chapter for more information). The MC9S08LC60 Series has two TPM modules Figure 11-1 shows the MC9S08LC60 Series block diagram with the TPMs highlighted.
Chapter 11 Timer Pulse-Width Modulator (S08TPMV2) HCS08 CORE INT ADP[7:4] ADP3 ADP2 ADP1 ADP0 4 BKGD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) BKP HCS08 SYSTEM CONTROL RTI COP IRQ LVD ANALOG COMPARATOR (ACMP) 8-BIT KEYBOARD INTERRUPT (KBI1) USER FLASH A (LC60 = 32,768 BYTES) (LC36 = 24,576 BYTES) SERIAL PERIPHERAL INTERFACE (SPI1) PTA3/KBI1P3/ADP3/ACMP– ACMP+ PTA2/KBI1P2/ADP2/ACMP+ 8 PTA[1:0]/KBI1P[1:0]/ADP[1:0] SS1 SPSCK1 MISO1 PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 MOSI1 SCL IIC MODULE (
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) 11.1.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) BUSCLK XCLK TPMxCLK SYNC CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT CLKSB PRESCALE AND SELECT DIVIDE BY 1, 2, 4, 8, 16, 32, 64, or 128 PS2 CLKSA PS1 PS0 CPWMS MAIN 16-BIT COUNTER TOF COUNTER RESET INTERRUPT LOGIC TOIE 16-BIT COMPARATOR TPMxMODH:TPMxMODL ELS0B CHANNEL 0 ELS0A PORT LOGIC 16-BIT COMPARATOR TPMxC0VH:TPMxC0VL CH0F INTERRUPT LOGIC 16-BIT LATCH INTERNAL BUS CHANNEL 1 MS0B MS0A ELS1B ELS1A CH0IE TPMxCH1 PORT LOGIC 16-BIT CO
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. 11.2 External Signal Description When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 11.2.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Some MCU systems have more than one TPM, so register names include placeholder characters to identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n and TPM1C2SC is the status and control register for timer 1, channel 2. 11.3.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) Table 11-2. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 0:0 No clock selected (TPMx disabled) 0:1 Bus rate clock (BUSCLK) 1:0 Fixed system clock (XCLK) 1:1 External source (TPMxCLK)1,2 1 The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) R 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 W Reset Any write to TPMxCNTL clears the 16-bit counter. 0 0 0 0 0 0 Figure 11-5.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) 11.3.4 Timer x Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 CHnF CHnIE MSnB MSnA ELSnB ELSnA 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 11-8. Timer x Channel n Status and Control Register (TPMxCnSC) Table 11-4.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) Table 11-5.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 11.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock period long). An interrupt flag and enable are associated with the main 16-bit counter.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) 11.4.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set, clear, or toggle the channel pin.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) 11.4.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMxMODH:TPMxMODL. TPMxMODH:TPMxMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to PWM channels, not output compares.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) 11.5.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is set.
Chapter 12 Serial Communications Interface (S08SCIV3) 12.1 Introduction Figure 12-1 shows the MC9S08LC60 Series block diagram with the SCI highlighted. MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 12 Serial Communications Interface (S08SCIV3) HCS08 CORE INT ADP[7:4] ADP3 ADP2 ADP1 ADP0 4 BKGD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) BKP HCS08 SYSTEM CONTROL RTI COP IRQ LVD ANALOG COMPARATOR (ACMP) 8-BIT KEYBOARD INTERRUPT (KBI1) USER FLASH A (LC60 = 32,768 BYTES) (LC36 = 24,576 BYTES) SERIAL PERIPHERAL INTERFACE (SPI1) PTA3/KBI1P3/ADP3/ACMP– ACMP+ PTA2/KBI1P2/ADP2/ACMP+ 8 PTA[1:0]/KBI1P[1:0]/ADP[1:0] SS1 SPSCK1 MISO1 PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 MOSI1 SCL IIC MODU
Chapter 12 Serial Communications Interface (S08SCIV3) Module Initialization: Write: SCIBDH:SCIBDL to set baud rate Write: SCFC1 to configure 1-wire/2-wire, 9/8-bit data, wakeup, and parity, if used. Write; SCIC2 to configure interrupts, enable Rx and Tx, RWU Enable Rx wakeup, SBK sends break character Write: SCIC3 to enable Rx error interrupt sources. Also controls pin direction in 1-wire modes. R8 and T8 only used in 9-bit data modes.
Chapter 12 Serial Communications Interface (S08SCIV3) 12.1.
Chapter 12 Serial Communications Interface (S08SCIV3) 12.1.3 Block Diagram Figure 12-3 shows the transmitter portion of the SCI. (Figure 12-4 shows the receiver portion of the SCI.
Chapter 12 Serial Communications Interface (S08SCIV3) Figure 12-4 shows the receiver portion of the SCI.
Chapter 12 Serial Communications Interface (S08SCIV3) 12.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names.
Chapter 12 Serial Communications Interface (S08SCIV3) Table 12-2. SCIBDL Register Field Descriptions Field Description 7:0 SBR[7:0] Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 12-1. 12.2.
Chapter 12 Serial Communications Interface (S08SCIV3) Table 12-3. SCIC1 Register Field Descriptions (continued) Field Description 1 PE Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. 0 PT Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity.
Chapter 12 Serial Communications Interface (S08SCIV3) Table 12-4. SCIC2 Register Field Descriptions (continued) Field Description 2 RE Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1, the RxD pin reverts to being a general-purpose I/O pin even if RE = 1. 0 Receiver off. 1 Receiver on.
Chapter 12 Serial Communications Interface (S08SCIV3) Table 12-5. SCIS1 Register Field Descriptions (continued) Field Description 5 RDRF Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCID). To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register (SCID). 0 Receive data register empty. 1 Receive data register full.
Chapter 12 Serial Communications Interface (S08SCIV3) 12.2.5 SCI Status Register 2 (SCIS2) This register has one read-only status flag. Writes have no effect. R 7 6 5 4 3 0 0 0 0 0 2 1 0 0 RAF 0 0 BRK13 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 12-10. SCI Status Register 2 (SCIS2) Table 12-6. SCIS2 Register Field Descriptions Field 2 BRK13 0 RAF 12.2.6 Description Break Character Length — BRK13 is used to select a longer break character length.
Chapter 12 Serial Communications Interface (S08SCIV3) Table 12-7. SCIC3 Register Field Descriptions (continued) Field 1 Description 5 TXDIR TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode.
Chapter 12 Serial Communications Interface (S08SCIV3) 12.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
Chapter 12 Serial Communications Interface (S08SCIV3) selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit.
Chapter 12 Serial Communications Interface (S08SCIV3) 12.3.3 Receiver Functional Description In this section, the receiver block diagram (Figure 12-4) is used as a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained. The receiver is enabled by setting the RE bit in SCIC2.
Chapter 12 Serial Communications Interface (S08SCIV3) In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set. 12.3.3.
Chapter 12 Serial Communications Interface (S08SCIV3) masked by local interrupt enable masks. The flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCID.
Chapter 12 Serial Communications Interface (S08SCIV3) If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCID to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit.
Chapter 12 Serial Communications Interface (S08SCIV3) MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1 Introduction The MC9S08LC60 Series contains two SPI modules. Figure 13-1 shows the MC9S08LC60 Series block diagram with the SPIs highlighted. MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 13 Serial Peripheral Interface (S08SPIV3) HCS08 CORE INT ADP[7:4] ADP3 ADP2 ADP1 ADP0 4 BKGD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) BKP HCS08 SYSTEM CONTROL RTI COP IRQ LVD ANALOG COMPARATOR (ACMP) 8-BIT KEYBOARD INTERRUPT (KBI1) USER FLASH A (LC60 = 32,768 BYTES) (LC36 = 24,576 BYTES) SERIAL PERIPHERAL INTERFACE (SPI1) PTA3/KBI1P3/ADP3/ACMP– ACMP+ PTA2/KBI1P2/ADP2/ACMP+ 8 PTA[1:0]/KBI1P[1:0]/ADP[1:0] SS1 SPSCK1 MISO1 PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 MOSI1 SCL IIC MODULE (
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 13.1.
Chapter 13 Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 13-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 13.1.2.
Chapter 13 Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPIxD) ENABLE SPI SYSTEM M SHIFT OUT SPI SHIFT REGISTER SHIFT IN MISO (SISO) S SPC0 Rx BUFFER (READ SPIxD) BIDIROE SHIFT DIRECTION LSBFE SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY MASTER CLOCK BUS RATE CLOCK CLOCK LOGIC SPIBR CLOCK GENERATOR MSTR SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODFEN SSOE MODE FAULT DETECTION SS SPRF SPTEF SPTIE MODF SPIE SPI INTERRUPT
Chapter 13 Serial Peripheral Interface (S08SPIV3) BUS CLOCK PRESCALER CLOCK RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 13-4. SPI Baud Rate Generation 13.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits.
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.3 Modes of Operation 13.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
Chapter 13 Serial Peripheral Interface (S08SPIV3) Table 13-1. SPIxC1 Field Descriptions (continued) Field Description 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 13.5.1, “SPI Clock Formats” for more details.
Chapter 13 Serial Peripheral Interface (S08SPIV3) Table 13-3. SPIxC2 Register Field Descriptions Field Description 4 MODFEN Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 13-2 for more details).
Chapter 13 Serial Peripheral Interface (S08SPIV3) Table 13-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 13-6. SPI Baud Rate Divisor 13.4.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPIxS) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
Chapter 13 Serial Peripheral Interface (S08SPIV3) Table 13-7. SPIxS Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPIxD). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPIxD) in the master SPI device.
Chapter 13 Serial Peripheral Interface (S08SPIV3) pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ...
Chapter 13 Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave.
Chapter 13 Serial Peripheral Interface (S08SPIV3) 13.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF).
Chapter 13 Serial Peripheral Interface (S08SPIV3) MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
Chapter 14 Inter-Integrated Circuit (S08IICV1) HCS08 CORE INT ADP[7:4] ADP3 ADP2 ADP1 ADP0 4 BKGD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) BKP HCS08 SYSTEM CONTROL RTI COP IRQ LVD ANALOG COMPARATOR (ACMP) 8-BIT KEYBOARD INTERRUPT (KBI1) USER FLASH A (LC60 = 32,768 BYTES) (LC36 = 24,576 BYTES) SERIAL PERIPHERAL INTERFACE (SPI1) PTA3/KBI1P3/ADP3/ACMP– ACMP+ PTA2/KBI1P2/ADP2/ACMP+ 8 PTA[1:0]/KBI1P[1:0]/ADP[1:0] SS1 SPSCK1 MISO1 PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 MOSI1 SCL IIC MODULE (IIC
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.1.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.1.3 Block Diagram Figure 14-2 is a block diagram of the IIC. ADDRESS DATA BUS INTERRUPT ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG INPUT SYNC START STOP ARBITRATION CONTROL CLOCK CONTROL IN/OUT DATA SHIFT REGISTER ADDRESS COMPARE SCL SDA Figure 14-2. IIC Functional Block Diagram 14.2 External Signal Description This section describes each user-accessible pin signal. 14.2.
Chapter 14 Inter-Integrated Circuit (S08IICV1) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 14.3.
Chapter 14 Inter-Integrated Circuit (S08IICV1) Table 14-2. IICA Register Field Descriptions Field Description 7:6 MULT IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved 5:0 ICR IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection.
Chapter 14 Inter-Integrated Circuit (S08IICV1) Table 14-3.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.3.3 IIC Control Register (IICC) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-5. IIC Control Register (IICC) Table 14-4. IICC Register Field Descriptions Field Description 7 IICEN IIC Enable — The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled. 1 IIC is enabled.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.3.4 IIC Status Register (IICS) 7 R 6 5 TCF 4 BUSY IAAS 3 2 0 SRW ARBL 1 0 RXAK IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-6. IIC Status Register (IICS) Table 14-5. IICS Register Field Descriptions Field Description 7 TCF Transfer Complete Flag — This bit is set on the completion of a byte transfer.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset 0 0 0 0 Figure 14-7. IIC Data I/O Register (IICD) Table 14-6. IICD Register Field Descriptions Field Description 7:0 DATA Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.4 Functional Description This section provides a complete functional description of the IIC module. 14.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.4.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 14-8, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 14-8).
Chapter 14 Inter-Integrated Circuit (S08IICV1) DELAY START COUNTING HIGH PERIOD SCL1 SCL2 SCL INTERNAL COUNTER RESET Figure 14-9. IIC Clock Synchronization 14.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 14.4.1.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of byte transfer. 14.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register), the IAAS bit in the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 14.6.
Chapter 14 Inter-Integrated Circuit (S08IICV1) 14.7 1. 2. 3. 4. 1. 2. 3. 4. 5. 6. 7.
Chapter 14 Inter-Integrated Circuit (S08IICV1) Clear IICIF Master Mode ? Y TX N Y RX Tx/Rx ? Arbitration Lost ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y N Address Transfer Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 Generate Stop Signal (MST = 0) Switch to Rx Mode Dummy Read from IICD Generate Stop Signal (MST = 0) TX Y Set TX Mode
Chapter 14 Inter-Integrated Circuit (S08IICV1) MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.1 Introduction The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. 15.1.1 ADC Configuration Information The ADC channel assignments, alternate clock function, and hardware trigger function are configured as described in this section for the MC9S08LC60/36/20 Family of devices. 15.1.1.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.1.1.2 Alternate Clock The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two, or the local asynchronous clock (ADACK) within the module. The alternate clock, ALTCLK, input for the MC9S08LC60/36/20 MCU devices is not implemented. 15.1.1.3 Hardware Trigger The ADC hardware trigger, ADHWT, is output from the real-time interrupt (RTI) counter.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.1.1.6 Low-Power Mode Operation The ADC is capable of running in stop3 mode but requires LVDSE in SPMSC1 to be set.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.1.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) ADIV ADLPC MODE ADLSMP ADTRG 2 ADCO ADCH 1 ADCCFG complete COCO ADCSC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK ÷2 ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 Interrupt COCO 2 ADVIN SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 Compare Value Registers ACFGT Value Compare Logic ADCSC2 Figure 15-2.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.2.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 15.2.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 7 R 6 5 4 AIEN ADCO 0 0 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 = Unimplemented or Reserved Figure 15-3. Status and Control Register (ADCSC1) Table 15-3. ADCSC1 Register Field Descriptions Field Description 7 COCO Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (ACFE = 0).
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) Figure 15-4. Input Channel Select (continued) 15.3.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) Table 15-4. ADCSC2 Register Field Descriptions (continued) Field 5 ACFE 4 ACFGT 15.3.3 Description Compare Function Enable — ACFE is used to enable the compare function. 0 Compare function disabled 1 Compare function enabled Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) R 7 6 5 4 3 2 1 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented or Reserved Figure 15-7. Data Result Low Register (ADCRL) 15.3.5 Compare Value High Register (ADCCVH) In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. These bits are compared to the upper four bits of the result following a conversion in 12-bit mode when the compare function is enabled.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 0 0 0 0 0 0 0 0 Figure 15-10. Configuration Register (ADCCFG) Table 15-5. ADCCFG Register Field Descriptions Field Description 7 ADLPC Low Power Configuration — ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) Table 15-8. Input Clock Select ADICLK 15.3.8 Selected Clock Source 00 Bus clock 01 Bus clock divided by 2 10 Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK) Pin Control 1 Register (APCTL1) The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0–7 of the ADC module.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) Table 15-9. APCTL1 Register Field Descriptions (continued) Field Description 1 ADPC1 ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1. 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled 0 ADPC0 ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0. 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 15.3.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) Table 15-10. APCTL2 Register Field Descriptions (continued) Field Description 1 ADPC9 ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9. 0 AD9 pin I/O control enabled 1 AD9 pin I/O control disabled 0 ADPC8 ADC Pin Control 8 — ADPC8 is used to control the pin associated with channel AD8. 0 AD8 pin I/O control enabled 1 AD8 pin I/O control disabled 15.3.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) Table 15-11. APCTL3 Register Field Descriptions (continued) Field Description 1 ADPC17 ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17. 0 AD17 pin I/O control enabled 1 AD17 pin I/O control disabled 0 ADPC16 ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16. 0 AD16 pin I/O control enabled 1 AD16 pin I/O control disabled 15.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1, 2, 4, or 8. 15.4.2 Input Select and Pin Control The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the pins used as analog inputs.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.4.4.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high at the time that COCO is set.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) digital value of the analog signal. The result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm. If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (ADLSMP=0).
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.4.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 15.5.1.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? NO YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE Figure 15-14. Initialization Flowchart for Example 15.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 15.6.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 15.6.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 15.6.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 12-bit resolution) can be achieved within the minimum sample window (3.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 15.6.2.
Chapter 15 Analog-to-Digital Converter (S08ADC12V1) 15.6.2.6 Code Jitter, Non-Monotonicity and Missing Codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the converter yields the lower code (and vice-versa).
Chapter 16 Analog Comparator (S08ACMPV2) 16.1 Introduction The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail to rail operation). 16.1.
Chapter 16 Analog Comparator (S08ACMPV2) HCS08 CORE INT ADP[7:4] ADP3 ADP2 ADP1 ADP0 4 BKGD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) BKP HCS08 SYSTEM CONTROL RTI COP IRQ LVD ANALOG COMPARATOR (ACMP) 8-BIT KEYBOARD INTERRUPT (KBI1) USER FLASH A (LC60 = 32,768 BYTES) (LC36 = 24,576 BYTES) SERIAL PERIPHERAL INTERFACE (SPI1) PTA3/KBI1P3/ADP3/ACMP– ACMP+ PTA2/KBI1P2/ADP2/ACMP+ 8 PTA[1:0]/KBI1P[1:0]/ADP[1:0] SS1 SPSCK1 MISO1 PTB7/KBI2P4/SS1 PTB6/KBI2P3/SPSCK1 MOSI1 SCL IIC MODULE (IIC) USER
Chapter 16 Analog Comparator (S08ACMPV2) 16.1.3 Features The ACMP has the following features: • Full rail-to-rail supply operation. • Less than 40 mV of input offset. • Less than 15 mV of hysteresis. • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. • Option to compare to fixed internal bandgap reference voltage. • Option to allow comparator output to be visible on a pin, ACMPO. 16.1.
Chapter 16 Analog Comparator (S08ACMPV2) Internal Bus Internal Reference ACIE ACBGS ACME ACMP INTERRUPT REQUEST Status & Control Register ACF ACMP+ + – ACMP– set ACF ACMOD ACOPE Interrupt Control Comparator ACMPO Figure 16-2. Analog Comparator (ACMP) Block Diagram MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 16 Analog Comparator (S08ACMPV2) 16.2 External Signal Description The ACMP has two analog input pins, ACMP+ and ACMP– and one digital output pin ACMPO. Each of these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As shown in Figure 16-2, the ACMP– pin is connected to the inverting input of the comparator, and the ACMP+ pin is connected to the comparator non-inverting input if ACBGS is a 0.
Chapter 16 Analog Comparator (S08ACMPV2) 16.3.1 ACMP Status and Control Register (ACMPSC) ACMPSC contains the status flag and control bits which are used to enable and configure the ACMP. 7 6 5 4 3 ACME ACBGS ACF ACIE 0 0 0 0 R 2 1 0 ACO ACOPE ACMOD W Reset: 0 0 0 0 = Unimplemented Figure 16-3. ACMP Status and Control Register Table 16-2. ACMP Status and Control Register Field Descriptions Field 7 ACME Description Analog Comparator Module Enable — ACME enables the ACMP module.
Chapter 16 Analog Comparator (S08ACMPV2) 16.4 Functional Description The analog comparator can be used to compare two analog input voltages applied to ACMP+ and ACMP–; or it can be used to compare an analog input voltage applied to ACMP– with an internal bandgap reference voltage. ACBGS is used to select between the bandgap reference voltage or the ACMP+ pin as the input to the non-inverting input of the analog comparator.
Chapter 16 Analog Comparator (S08ACMPV2) MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Chapter 17 Development Support 17.1 Introduction This chapter describes the single-wire background debug mode (BDM), which uses the on-chip background debug controller (BDC) module, and the independent on-chip real-time in-circuit emulation (ICE) system, which uses the on-chip debug (DBG) module. 17.1.
Chapter 17 Development Support 17.2 Background Debug Controller (BDC) All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources. It does not use any user memory or locations in the memory map and does not share any on-chip peripherals.
Chapter 17 Development Support first (MSB first). For a detailed description of the communications protocol, refer to Section 17.2.2, “Communication Details.” If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed. BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required.
Chapter 17 Development Support Figure 17-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin.
Chapter 17 Development Support Figure 17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target BDC cycles).
Chapter 17 Development Support Figure 17-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
Chapter 17 Development Support 17.2.3 BDC Commands BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All commands and data are sent MSB-first using a custom BDC communications protocol. Active background mode commands require that the target MCU is currently in the active background mode while non-intrusive commands may be issued at any time whether the target MCU is in active background mode or running a user application program.
Chapter 17 Development Support Table 17-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
Chapter 17 Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
Chapter 17 Development Support 17.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture.
Chapter 17 Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port.
Chapter 17 Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU.
Chapter 17 Development Support A-Only — Trigger when the address matches the value in comparator A A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match.
Chapter 17 Development Support 17.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 17.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue.
Chapter 17 Development Support 17.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 6 R 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 17-5.
Chapter 17 Development Support Table 17-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
Chapter 17 Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 17-6. System Background Debug Force Reset Register (SBDFR) Table 17-3.
Chapter 17 Development Support 17.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word.
Chapter 17 Development Support 17.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 17-7. Debug Control Register (DBGC) Table 17-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
Chapter 17 Development Support 17.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 17-8. Debug Trigger Register (DBGT) Table 17-5.
Chapter 17 Development Support 17.4.3.9 Debug Status Register (DBGS) This is a read-only status register. R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-9. Debug Status Register (DBGS) Table 17-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming.
Chapter 17 Development Support MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Appendix A Electrical Characteristics A.1 Introduction This section contains electrical and timing specifications. A.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section.
Appendix A Electrical Characteristics A.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the MCU design.
Appendix A Electrical Characteristics K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. A-3 where K is a constant pertaining to the particular part. K can be determined from Equation A-3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA. A.
Appendix A Electrical Characteristics A.5 DC Characteristics This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various operating modes. Table A-5. DC Characteristics (Sheet 1 of 2) (Temperature Range = -40 to 85°C Ambient) Symbol Min Typical(1) Max Unit VDD 1.8 — 3.6 V Minimum RAM retention supply voltage applied to VDD VRAM 1.0(2) — — V Low-voltage detection threshold — high range (VDD falling) (VDD rising) VLVDH 2.
Appendix A Electrical Characteristics Table A-5. DC Characteristics (Sheet 2 of 2) (Temperature Range = -40 to 85°C Ambient) Parameter Output high voltage (VDD ≥ 1.8 V) IOH = –2 mA (ports A, B, and C) Symbol Min VOH VDD – 0.5 3 4 5 6 7 8 Unit — V — — — Maximum total IOH for all port pins |IOHT| Output low voltage (VDD ≥ 1.8 V) IOL = 2.0 mA (ports A, B, and C) VOL Output low voltage (all port pins) IOL = 10.0 mA (VDD ≥ 2.7 V) IOL = 6 mA (VDD ≥ 2.3 V) IOL = 3 mA (VDD ≥ 1.8 V) 2 Max VDD – 0.
Appendix A Electrical Characteristics Pull Up Resistance Pull Down Resistance 36 34 32 32 Resistance (kOhm) Resistance (kOhm) 34 -40C 30 25C 28 70C 26 85C 24 22 30 -40C 28 25C 26 70C 85C 24 22 20 20 1.8 2 2.3 2.7 3 3.6 1.8 2 2.3 VDD (V) 2.7 3 3.6 VDD (V) Figure A-1. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V) IOL at Vdd = 2.7V -40C IOL (mA) 40 25C 30 70C 20 85C 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VOL (V) Figure A-2.
Appendix A Electrical Characteristics VOL vs VDD 350.00 -40C (3mA) 300.00 10mA -40C (6mA) VOL (mV) 250.00 -40C (10mA) 6mA 25C (3mA) 200.00 25C (6mA) 25C (10mA) 150.00 3mA 70C (3mA) 100.00 70C (6mA) 70C (10mA) 50.00 85C (3mA) 85C (6mA) 0.00 1.8 2.3 85C (10mA) 2.7 VDD (V) Figure A-3. Typical Low-Side Driver (Sink) Characteristics (Ports A, B, and C) Typical VOL vs. VDD IOH at Vdd =2.7V -35 IOH (mA) -30 -25 -40C -20 25C -15 70C -10 85C -5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.
Appendix A Electrical Characteristics VOH vs VDD -40C (3mA) -40C (6mA) -40C (10mA) 25C (3mA) 25C (6mA) 25C (10mA) 70C (3mA) 70C (6mA) 70C (10mA) 85C (3mA) 85C (6mA) 85C (10mA) 2.700 VOH (mV) 2.500 2.300 2.100 1.900 1.700 1.500 1.8 2.3 2.7 VDD (V) Figure A-5. Typical Low-Side Driver (Sink) Characteristics (Ports A, B, and C) Typical VOH vs. VDD at Spec IOH A.6 Supply Current Characteristics Table A-6. Supply Current Characteristics VDD (V) Typical(1) Max(2) Temp. (°C) 3 800 μA 1.
Appendix A Electrical Characteristics Table A-6. Supply Current Characteristics (continued) Parameter Adder to stop3 for oscillator enabled(6) (OSCSTEN =1) (32 kHz) Adder for loss-of-clock detection (LOCD = 0) 1 2 3 4 5 6 Symbol VDD (V) Typical(1) Max(2) 3 4 μA 85 2 3.5 μA 85 3 9 μA 85 Temp. (°C) Typicals are measured at 25°C. See Table A-6 through Table A-9 for typical curves across voltage/temperature. Values given here are preliminary estimates prior to completing characterization.
Appendix A Electrical Characteristics Typical Room Temp SIDD1 1000 Room Temp SIDD1 (nA) SIDD1 (uA) 900 800 700 600 500 400 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) Figure A-7. Typical Stop1 IDD Typical Room Temp SIDD2 1000 Room Temp SIDD2 (nA) SIDD2 (uA) 900 800 TBD 700 600 500 400 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) Figure A-8. Typical Stop 2 IDD MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Appendix A Electrical Characteristics Typical Room Temp SIDD3 1000 Room Temp SIDD3 (nA) SIDD3 (uA) 900 800 TBD 700 600 500 400 1.8 2.1 2.4 2.7 3 3.3 3.6 VDD (V) Figure A-9. Typical Stop3 IDD A.7 ADC Characteristics Table A-7. 3 Volt 12-bit ADC Operating Conditions Symbol Min Typ(1) Max Unit Absolute VDDAD 1.8 — 3.
Appendix A Electrical Characteristics Table A-7. 3 Volt 12-bit ADC Operating Conditions Min Typ(1) Max — — — — 2 5 10 bit mode fADCK > 4MHz fADCK < 4MHz — — — — 5 10 8 bit mode (all valid fADCK) — — 10 0.4 — 8.0 0.4 — 4.0 Characteristic Analog Source Resistance Conditions Symbol 12 bit mode fADCK > 4MHz fADCK < 4MHz ADC Conversion Clock Freq. Unit Comment kΩ External to MCU RAS High Speed (ADLPC=0) fADCK Low Power (ADLPC=1) MHz 1 Typical values assume VDDAD = 3.
Appendix A Electrical Characteristics Table A-8. 3 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) C Symbol Min Typ(1) Max Unit Supply Current ADLPC=1 ADLSMP=0 ADCO=1 T IDDAD — 202 — μA Supply Current ADLPC=0 ADLSMP=1 ADCO=1 T IDDAD — 288 — μA Supply Current ADLPC=0 ADLSMP=0 ADCO=1 T IDDAD — 532 — μA — — 1 mA 2 3.3 5 MHz 1.25 2 3.3 tADACK = 1/fADACK — 20 — — 40 — ADCK cycles See Table A-7 for conversion time variances — 3.
Appendix A Electrical Characteristics Table A-8. 3 Volt 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) Characteristic Conditions C Symbol EZS Min Typ(1) Max Zero-Scale Error (64-pin package only) 12 bit mode T 10 bit mode P — ±1.5 ±2.1 8 bit mode P — ±0.5 ±0.7 Full-Scale Error (80-pin package only) 12 bit mode T — ±1.0 — 10 bit mode P — ±0.5 ±1 8 bit mode P — ±0.5 ±0.5 12 bit mode T 10 bit mode P — ±1 ±1.5 8 bit mode P — ±0.5 ±0.
Appendix A Electrical Characteristics Table A-9. LCD Electricals, 3-V Glass (continued) Characteristic Symbol Min Typ Max Unit CLCD 100 100 433 nF CBYLCD 100 100 433 nF all segments off, all FP enabled Isegoff — 0.35 — μA half of segments on Iseghalf — 1 — μA all segments on Isegallon — 1 — μA all segments off, all FP enabled Isegoff — 2.65 — μA half of segments on Iseghalf — 3.8 — μA all segments on Isegallon — 3.
Appendix A Electrical Characteristics Table A-10. LCD Electricals, 5 V Glass Characteristic Symbol Min Typ Max Unit LCD Supply Voltage VLCD 0.9 — 1.8 V LCD Frame Frequency fRame 25 30 100 Hz LCD Charge Pump Capacitance CLCD 100 100 433 nF CBYLCD 100 100 433 nF all segments off, all FP enabled Isegoff — 0.2 — μA half of segments on Iseghalf — 0.95 — μA all segments on Isegallon — 0.67 — μA all segments off, all FP enabled Isegoff — 3.
Appendix A Electrical Characteristics A.9 Internal Clock Generation Module Characteristics ICG EXTAL XTAL RS RF C1 Crystal or Resonator (See Note) C2 NOTE: Use fundamental mode crystal or ceramic resonator only. Table A-11.
Appendix A Electrical Characteristics Table A-12.
Appendix A Electrical Characteristics Figure A-11. Internal Oscillator Deviation from Trimmed Frequency A.10 AC Characteristics This section describes ac timing characteristics for each peripheral system. For detailed information about how clocks for the bus are generated, see Chapter 7, “Internal Clock Generator (ICG) Module.” MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Appendix A Electrical Characteristics A.10.1 Control Timing Table A-13. Control Timing Parameter Symbol Min Typical Max Unit Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz Real-time interrupt internal oscillator period tRTI 700 1300 μs External reset pulse width(1) textrst 1.
Appendix A Electrical Characteristics tILIH IRQ Figure A-14. IRQ Timing A.10.2 Timer/PWM (TPM) Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table A-14.
Appendix A Electrical Characteristics A.10.3 SPI Timing Table A-12 and Figure A-16 through Figure A-19 describe the timing requirements for the SPI system. Table A-15. SPI Timing No.
Appendix A Electrical Characteristics SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 11 3 4 4 12 SCK (CPOL = 1) (OUTPUT) 5 6 MISO (INPUT) MSB IN2 BIT 6 . . . 1 9 LSB IN 9 MOSI (OUTPUT) MSB OUT2 10 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-17.
Appendix A Electrical Characteristics SS (INPUT) 1 12 11 11 12 3 SCK (CPOL = 0) (INPUT) 2 4 4 SCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) 9 SLAVE MSB OUT BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 6 5 MOSI (INPUT) 10 10 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure A-19.
Appendix A Electrical Characteristics A.11 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see Chapter 4, “Memory.” Table A-16.
Appendix A Electrical Characteristics A.12 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance.
Appendix A Electrical Characteristics A.12.2 Conducted Transient Susceptibility Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient signal on each pin of the microcontroller.
Appendix A Electrical Characteristics MC9S08LC60 Series Data Sheet: Technical Data, Rev.
Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering numbers for MC9S08LC60 and MC9S08LC36 devices. See below for an example of the device numbering system. Table B-1.
Appendix B Ordering Information and Mechanical Drawings MC9S08LC60 Series Data Sheet: Technical Data, Rev.
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