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HCS08

Microcontrollers

freescale.com

MC9S08QG8

MC9S08QG4

Data Sheet

MC9S08QG8

Rev. 5

11/2009

Summary of content (314 pages)

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MC9S08QG8 MC9S08QG4 Data Sheet HCS08 Microcontrollers MC9S08QG8 Rev. 5 11/2009 freescale.
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MC9S08QG8/4 Features 8-Bit HCS08 Central Processor Unit (CPU) • • • • • • 20-MHz HCS08 CPU (central processor unit) HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) Debug module containing two comparators and nine trigger modes.
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MC9S08QG8 Data Sheet Covers MC9S08QG8 MC9S08QG4 MC9S08QG8 Rev. 5 11/2009 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved.
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Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev No. Revision Date Description of Changes Previous version was 1.01; revision numbering will increment by integers from now on.
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This product incorporates SuperFlash® Technology licensed from SST.
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MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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List of Chapters Chapter Title Page Chapter 1 Device Overview ...................................................................... 19 Chapter 2 External Signal Description .................................................... 23 Chapter 3 Modes of Operation ................................................................. 33 Chapter 4 Memory Map and Register Definition .................................... 39 Chapter 5 Resets, Interrupts, and General System Control..................
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Contents Section Number Title Page Chapter 1 Device Overview 1.1 Introduction ..................................................................................................................................... 19 1.1.1 Devices in the MC9S08QG8/4 Series ...............................................................................19 1.1.2 MCU Block Diagram.........................................................................................................
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Section Number 4.6 4.7 Title Page 4.5.2 Program and Erase Times ..................................................................................................47 4.5.3 Program and Erase Command Execution ..........................................................................48 4.5.4 Burst Program Execution...................................................................................................49 4.5.5 Access Errors .........................................................................
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Section Number Title Page Chapter 6 Parallel Input/Output Control 6.1 6.2 6.3 6.4 Port Data and Data Direction .......................................................................................................... 77 Pin Control — Pullup, Slew Rate, and Drive Strength ................................................................... 78 Pin Behavior in Stop Modes............................................................................................................ 79 Parallel I/O Registers ...
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Section Number 8.2 8.3 8.4 Title Page 8.1.4 Modes of Operation .........................................................................................................109 8.1.5 Block Diagram .................................................................................................................109 External Signal Description .......................................................................................................... 111 Register Definition ........................................
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Section Number Title Page 9.6.1 External Pins and Routing ...............................................................................................137 9.6.2 Sources of Error ...............................................................................................................139 Chapter 10 Internal Clock Source (S08ICSV1) 10.1 Introduction ................................................................................................................................... 143 10.1.
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Section Number Title Page 11.4 Functional Description .................................................................................................................. 165 11.4.1 IIC Protocol......................................................................................................................165 11.5 Resets ............................................................................................................................................ 168 11.6 Interrupts ......................
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Section Number Title Page Chapter 14 Serial Communications Interface (S08SCIV3) 14.1 Introduction ................................................................................................................................... 191 14.1.1 Features ............................................................................................................................194 14.1.2 Modes of Operation .........................................................................................................
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Section Number Title Page 15.4.4 SPI Status Register (SPIS) ...............................................................................................220 15.4.5 SPI Data Register (SPID) ................................................................................................221 15.5 Functional Description .................................................................................................................. 222 15.5.1 SPI Clock Formats ..............................................
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Section Number Title Page 17.2.4 BDC Hardware Breakpoint..............................................................................................251 17.3 On-Chip Debug System (DBG) .................................................................................................... 252 17.3.1 Comparators A and B ......................................................................................................252 17.3.2 Bus Capture Information and FIFO Operation ...................................
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Section Number Title Page MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 1 Device Overview 1.1 Introduction The MC9S08QG8 is a member of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and package types. Refer to Table 1-1 for features associated with each device in this series. 1.1.1 Devices in the MC9S08QG8/4 Series Table 1-1 summarizes the features available in the MC9S08QG8/4 series of MCUs. Table 1-1.
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Chapter 1 Device Overview 1.1.2 MCU Block Diagram BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Chapter 1 Device Overview Table 1-2 provides the functional versions of the on-chip modules. Table 1-2.
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Chapter 1 Device Overview MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 2 External Signal Description This section describes signals that connect to package pins. It includes pinout diagrams, table of signal properties, and detailed discussions of signals. 2.1 Device Pin Assignment The following figures show the pin assignments for the available packages. Refer to Table 1-1 to see which package types are available for each device in the series.
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Chapter 2 External Signal Description PTA5/IRQ/TCLK/RESET 1 16 PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA4/ACMPO/BKGD/MS 2 15 PTA1/KBIP1/ADP1/ACMP– VDD 3 14 PTA2/KBIP2/SDA/ADP2 VSS 4 13 PTA3/KBIP3/SCL/ADP3 PTB7/SCL/EXTAL 5 12 PTB0/KBIP4/RxD/ADP4 PTB6/SDA/XTAL 6 11 PTB1/KBIP5/TxD/ADP5 PTB5/TPMCH1/SS 7 10 PTB2/KBIP6/SPSCK/ADP6 PTB4/MISO 8 9 PTB3/KBIP7/MOSI/ADP7 16-PIN ASSIGNMENT PDIP PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS VDD VSS PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPMCH1/SS PTB4/MISO 1
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NC PTA0/KBIP0/TPMCH0/ADP0/ACMP+ NC Pin 1 indicator NC PTA5/IRQ/TCLK/RESET NC Chapter 2 External Signal Description 24 23 22 21 20 19 18 PTA1/KBIP1/ADP1/ACMP‚ 17 PTA2/KBIP2/SDA/ADP2 MC9S08QG8/4 VSS 3 16 PTA3/KBIP3/SCL/ADP3 PTA4/ACMP0/BKGD/MS 1 VDD 2 PTB7/SCL/EXTAL 4 15 PTB0/KBIP4/RxD/ADP4 PTB6/SDA/XTAL 5 14 PTB1/KBIP5/TxD/ADP5 PTB3/KBIP7/MOSI/ADP7 NC 13 PTB2/KBIP6/SPSCK/ADP6 10 11 12 NC 9 PTB4/MISO 7 8 NC NC PTB5/TPMCH1/SS 6 Figure 2-3. 24-Pin Packages 2.
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Chapter 2 External Signal Description MC9S08QG8/4 VDD SYSTEM POWER + 3V CBLK CBY + 10 μF PTA0/KBIP0/TPMCH0/ADP0/ACMP+ VDD PTA1/KBIP1/ADP1/ACMP– PTA2/KBIP2/SDA/ADP2 PORT A 0.1 μF VSS PTA3/KBIP3/SCL/ADP3 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK/RESET NOTE 1 RF C1 RS C2 X1 I/O AND XTAL NOTE 2 PERIPHERAL INTERFACE TO EXTAL NOTE 2 APPLICATION SYSTEM BACKGROUND HEADER BKGD VDD PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 VDD ASYNCHRONOUS PORT B 4.
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Chapter 2 External Signal Description 2.2.2 Oscillator (XOSC) Out of reset, the MCU uses an internally generated clock provided by the internal clock source (ICS) module. The internal frequency is nominally 16-MHz and the default ICS settings will provide for a 8-MHz bus out of reset. For more information on the ICS, see Chapter 10, “Internal Clock Source (S08ICSV1).
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Chapter 2 External Signal Description 2.2.4 Background / Mode Select (BKGD/MS) During a power-on-reset (POR) or background debug force reset (see 5.8.3, “System Background Debug Force Reset Register (SBDFR),” for more information), the PTA4/ACMPO/BKGD/MS pin functions as a mode select pin. Immediately after any reset, the pin functions as the background pin and can be used for background debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1), an internal pullup device is automatically enabled.
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Chapter 2 External Signal Description NOTE To avoid extra current drain from floating input pins, the reset initialization routine in the application program must either enable on-chip pullup devices or change the direction of unused pins to outputs so the pins do not float. When using the 8-pin devices, the user must either enable on-chip pullup devices or change the direction of non-bonded out port B pins to outputs so the pins do not float. 2.2.5.
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Chapter 2 External Signal Description Table 2-1.
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Chapter 2 External Signal Description NOTE When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software should clear out any associated flags before interrupts are enabled. Table 2-1 shows the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module.
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Chapter 2 External Signal Description MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 3 Modes of Operation 3.1 Introduction The operating modes of the MC9S08QG8/4 are described in this section. Entry into each mode, exit from each mode, and functionality while in each mode are described. 3.2 • • • 3.
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Chapter 3 Modes of Operation After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program. Background commands are of two types: • Non-intrusive commands, defined as commands that can be issued while the user program is running.
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Chapter 3 Modes of Operation 3.6 Stop Modes One of three stop modes is entered upon execution of a STOP instruction when STOPE in SOPT1 is set. In any stop mode, the bus and CPU clocks are halted. The ICS module can be configured to leave the reference clocks running. See Chapter 10, “Internal Clock Source (S08ICSV1),” for more information. Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions.
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Chapter 3 Modes of Operation STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode. Because of this, background debug communication remains possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. Most background commands are not available in stop mode.
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Chapter 3 Modes of Operation 3.6.3 Stop1 Mode Stop1 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Most of the internal circuitry of the MCU is powered off in stop1, providing the lowest possible standby current. Upon entering stop1, all I/O pins automatically transition to their default reset states. Exit from stop1 is performed by asserting the wake-up pin (PTA5) on the MCU.
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Chapter 3 Modes of Operation Table 3-2. Stop Mode Behavior (continued) Mode Peripheral Stop1 Stop2 Stop3 MTIM Off Off Standby SCI Off Off Standby SPI Off Off Standby TPM Off Off Standby Voltage Regulator Off Standby Standby XOSC Off Off Optionally On3 I/O Pins Hi-Z States Held States Held 1 Requires the asynchronous ADC clock and LVD to be enabled, else in standby. IRCLKEN and IREFSTEN set in ICSC1, else in standby. 3 ERCLKEN and EREFSTEN set in ICSC2, else in standby.
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Chapter 4 Memory Map and Register Definition 4.1 MC9S08QG8/4 Memory Map As shown in Figure 4-1, on-chip memory in the MC9S08QG8/4 series of MCUs consists of RAM, FLASH program memory for nonvolatile data storage, and I/O and control/status registers.
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Chapter 4 Memory Map and Register Definition 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor-provided equate file for the MC9S08QG8/4. Table 4-1.
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Chapter 4 Memory Map and Register Definition 4.3 Register Addresses and Bit Assignments The registers in the MC9S08QG8/4 are divided into these groups: • Direct-page registers are located in the first 96 locations in the memory map; these are accessible with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located from 0x1800 and above in the memory map. This leaves more room in the direct page for more frequently used registers and RAM.
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Chapter 4 Memory Map and Register Definition Table 4-2.
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Chapter 4 Memory Map and Register Definition Table 4-2.
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Chapter 4 Memory Map and Register Definition Table 4-3.
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Chapter 4 Memory Map and Register Definition Table 4-4.
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Chapter 4 Memory Map and Register Definition 4.5 FLASH The FLASH memory is intended primarily for program storage. In-circuit programming allows the operating program to be loaded into the FLASH memory after final assembly of the application product. It is possible to program the entire array through the single-wire background debug interface.
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Chapter 4 Memory Map and Register Definition 4.5.1 Features Features of the FLASH memory include: • FLASH size — MC9S08QG8: 8,192 bytes (16 pages of 512 bytes each) — MC9S08QG4: 4,096 bytes (8 pages of 512 bytes each) • Single power supply program and erase • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature • Flexible block protection • Security feature for FLASH and RAM • Auto power-down for low-frequency read accesses 4.5.
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Chapter 4 Memory Map and Register Definition 4.5.3 Program and Erase Command Execution The steps for executing any of the commands are listed below. The FCDIV register must be initialized and any error flags cleared before beginning command execution. The command execution steps are: 1. Write a data value to an address in the FLASH array. The address and data information from this write is latched into the FLASH interface. This write is a required first step in any command sequence.
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Chapter 4 Memory Map and Register Definition Note 1: Required only once after reset. WRITE TO FCDIV (Note 1) FLASH PROGRAM AND ERASE FLOW START FACCERR ? 0 1 CLEAR ERROR WRITE TO FLASH TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) FPVIOL OR FACCERR ? Note 2: Wait at least four bus cycles before checking FCBEF or FCCF. YES ERROR EXIT NO 0 FCCF ? 1 DONE Figure 4-2. FLASH Program and Erase Flowchart 4.5.
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Chapter 4 Memory Map and Register Definition The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst program time provided that the conditions above are met. In the case the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time.
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Chapter 4 Memory Map and Register Definition 4.5.5 Access Errors An access error occurs whenever the command execution protocol is violated. Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
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Chapter 4 Memory Map and Register Definition must be programmed to logic 0 to enable block protection. Therefore the value 0xF8 must be programmed into NVPROT to protect addresses 0xFA00 through 0xFFFF. FPS7 FPS6 FPS5 FPS4 FPS3 A15 A14 A13 A12 A11 FPS2 FPS1 A10 A9 1 1 1 1 1 1 1 1 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 4-4. Block Protection Mechanism One use for block protection is to block protect an area of FLASH memory for a bootloader program.
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Chapter 4 Memory Map and Register Definition the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain unsecured after a subsequent reset. The on-chip debug module cannot be enabled while the MCU is secure.
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Chapter 4 Memory Map and Register Definition 4.7 FLASH Registers and Control Bits The FLASH module has six 8-bit registers in the high-page register space. Two locations (NVOPT, NVPROT) in the nonvolatile register space in FLASH memory are copied into corresponding high-page control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in FLASH memory. Refer to Table 4-3 and Table 4-4 for the absolute address assignments for all FLASH registers.
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Chapter 4 Memory Map and Register Definition Table 4-7. FLASH Clock Divider Settings 4.7.2 fBus PRDIV8 (Binary) DIV (Decimal) fFCLK Program/Erase Timing Pulse (5 μs Min, 6.7 μs Max) 20 MHz 1 12 192.3 kHz 5.2 μs 10 MHz 0 49 200 kHz 5 μs 8 MHz 0 39 200 kHz 5 μs 4 MHz 0 19 200 kHz 5 μs 2 MHz 0 9 200 kHz 5 μs 1 MHz 0 4 200 kHz 5 μs 200 kHz 0 0 200 kHz 5 μs 150 kHz 0 0 150 kHz 6.
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Chapter 4 Memory Map and Register Definition Table 4-9. Security States1 1 4.7.3 R SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. FLASH Configuration Register (FCNFG) 7 6 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 KEYACC W Reset 0 0 0 = Unimplemented or Reserved Figure 4-7. FLASH Configuration Register (FCNFG) Table 4-10.
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Chapter 4 Memory Map and Register Definition Table 4-11. FPROT Register Field Descriptions Field Description 7:1 FPS FLASH Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected FLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased or programmed. 0 FPDIS 4.7.5 FLASH Protection Disable 0 FLASH block specified by FPS7:FPS1 is block protected (program or erase not allowed). 1 No FLASH block is protected.
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Chapter 4 Memory Map and Register Definition Table 4-12. FSTAT Register Field Descriptions (continued) Field Description 4 FACCERR Access Error Flag — FACCERR is set automatically when the proper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has been initialized, or if the MCU enters stop while a command was in progress.
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Chapter 5 Resets, Interrupts, and General System Control 5.1 Introduction This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts in the MC9S08QG8/4. Some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. This section gathers basic information about all reset and interrupt sources in one place for easy reference.
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Chapter 5 Resets, Interrupts, and General System Control 5.4 Computer Operating Properly (COP) Watchdog The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically.
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Chapter 5 Resets, Interrupts, and General System Control When the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to stop mode. The COP counter begins from zero after the MCU exits stop mode. 5.5 Interrupts Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so processing resumes where it was before the interrupt.
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Chapter 5 Resets, Interrupts, and General System Control 5.5.1 Interrupt Stack Frame Figure 5-1 shows the content and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR.
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Chapter 5 Resets, Interrupts, and General System Control The IRQ pin, when enabled, defaults to use an internal pullup device (IRQPDD = 0). If the user desires to use an external pullup, the IRQPDD can be written to a 1 to turn off the internal device. BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act as the IRQ input. NOTE This pin does not contain a clamp diode to VDD and should not be driven above VDD.
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Chapter 5 Resets, Interrupts, and General System Control Table 5-2.
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Chapter 5 Resets, Interrupts, and General System Control 5.6 Low-Voltage Detect (LVD) System The MC9S08QG8/4 includes a system to protect against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user selectable trip voltage, either high (VLVDH) or low (VLVDL).
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Chapter 5 Resets, Interrupts, and General System Control (RANGE = 0). Only the internal 1-kHz clock source can be selected to wake the MCU from stop1 or stop2 modes. The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control value (RTIS) used to select one of seven wakeup periods. The RTI has a local interrupt enable, RTIE, to allow masking of the real-time interrupt. The RTI can be disabled by writing each bit of RTIS to 0s, and no interrupts will be generated.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) This direct page register includes status and control bits, which are used to configure the IRQ function, report status, and acknowledge IRQ events. 7 R 6 1 5 4 IRQPDD 0 IRQPE 0 3 2 IRQF 0 W Reset 1 0 IRQIE IRQMOD 0 0 IRQACK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-2.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.2 System Reset Status Register (SRS) This high page register includes read-only status flags to indicate the source of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the SBDFR register, all of the status bits in SRS will be cleared. Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.3 System Background Debug Force Reset Register (SBDFR) This high page register contains a single write-only control bit. A serial background command such as WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset: 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-4.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.4 System Options Register 1 (SOPT1) This high page register is a write-once register so only the first write after reset is honored. It can be read at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.5 System Options Register 2 (SOPT2) This high page register contains bits to configure MCU specific features on the MC9S08QG8/4 devices. 7 R COPCLKS1 6 5 4 3 2 0 0 0 0 0 1 0 IICPS ACIC 0 0 W Reset: 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-6. System Options Register 2 (SOPT2) 1 This bit can be written only one time after reset. Additional writes are ignored. Table 5-7.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.6 System Device Identification Register (SDIDH, SDIDL) These high page read-only registers are included so host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU. 7 6 5 4 R 3 2 1 0 ID11 ID10 ID9 ID8 0 0 0 0 W Reset: — — — — = Unimplemented or Reserved Figure 5-7.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.7 System Real-Time Interrupt Status and Control Register (SRTISC) This high page register contains status and control bits for the RTI. R 7 6 RTIF 0 W 5 4 RTICLKS RTIE 0 0 3 2 1 0 0 RTIS RTIACK Reset: 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-9. System RTI Status and Control Register (SRTISC) Table 5-10.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.8 System Power Management Status and Control 1 Register (SPMSC1) This high page register contains status and control bits to support the low voltage detect function and to enable the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip voltage, see Table 5-14 for the LVDV bit description in SPMSC3.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.9 System Power Management Status and Control 2 Register (SPMSC2) This high page register contains status and control bits to configure the stop mode behavior of the MCU. See Section 3.6, “Stop Modes,” for more information on stop modes. R 7 6 5 4 3 2 0 0 0 PDF PPDF 0 W Reset: 1 0 PDC1 PPDC1 0 0 PPDACK 0 0 0 0 0 0 = Unimplemented or Reserved Figure 5-11.
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Chapter 5 Resets, Interrupts, and General System Control 5.8.10 System Power Management Status and Control 3 Register (SPMSC3) This high page register is used to report the status of the low voltage warning function and to select the low voltage detect trip voltage. R 7 6 LVWF 0 W 5 4 LVDV LVWV 3 2 1 0 0 0 0 0 LVWACK POR: 01 0 0 0 0 0 0 0 LVD: 01 0 U U 0 0 0 0 Any other reset: 01 0 U U 0 0 0 0 = Unimplemented or Reserved U= Unaffected by reset Figure 5-12.
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Chapter 6 Parallel Input/Output Control This section explains software controls related to parallel input/output (I/O) and pin control. The MC9S08QG8 has two parallel I/O ports which include a total of 12 I/O pins, one output-only pin and one input-only pin. See Section Chapter 2, “External Signal Description,” for more information about pin assignments and external hardware considerations of these pins.
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Chapter 6 Parallel Input/Output Control PTxDDn D Output Enable Q PTxDn D Output Data Q 1 Port Read Data 0 Input Data Synchronizer BUSCLK Figure 6-1. Parallel I/O Block Diagram The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output-only pin.
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Chapter 6 Parallel Input/Output Control 6.3 Pin Behavior in Stop Modes Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An explanation of pin behavior for the various stop modes follows: • In stop1 mode, all internal registers including parallel I/O control and data registers are powered off. Each of the pins assumes its default reset state (output buffer and internal pullup disabled).
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Chapter 6 Parallel Input/Output Control Table 6-1. PTAD Register Field Descriptions Field Description 5:0 PTAD[5:0] Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A pins that are configured as outputs, reads return the last value written to this register. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is driven out the corresponding MCU pin.
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Chapter 6 Parallel Input/Output Control 6.4.2.1 Port A Internal Pullup Enable (PTAPE) An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup enable register (PTAPEn). The pullup device is disabled if the pin is configured as an output by the parallel I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
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Chapter 6 Parallel Input/Output Control 6.4.2.3 Port A Drive Strength Select (PTADS) An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (PTADS). When high drive is selected, a pin is capable of sourcing and sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that the total current source and sink limits for the chip are not exceeded.
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Chapter 6 Parallel Input/Output Control 6.4.3 Port B Registers This section provides information about the registers associated with the parallel I/O ports. Refer to tables in Chapter 4, “Memory Map and Register Definition,” for the absolute address assignments for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 6.4.3.
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Chapter 6 Parallel Input/Output Control 6.4.4 Port B Control Registers The pins associated with port B are controlled by the registers in this section. These registers control the pin pullup, slew rate, and drive strength of the port B pins independent of the parallel I/O register. 6.4.4.1 Port B Internal Pullup Enable (PTBPE) An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup enable register (PTBPEn).
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Chapter 6 Parallel Input/Output Control 6.4.4.3 Port B Drive Strength Select (PTBDS) An output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (PTBDSn). When high drive is selected, a pin is capable of sourcing and sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that the total current source and sink limits for the chip are not exceeded.
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Chapter 6 Parallel Input/Output Control MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.1 Introduction This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.2 Programmer’s Model and CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X H INDEX REGISTER (HIGH) 8 15 INDEX REGISTER (LOW) 7 X 0 SP STACK POINTER 0 15 PROGRAM COUNTER 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C PC CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers 7.2.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.2.3 Stack Pointer (SP) This 16-bit address pointer register points at the next available location on the automatic last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can be any size up to the amount of available RAM. The stack is used to automatically save the return address for subroutine calls, the return address and CPU registers during interrupts, and for local variables.
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Chapter 7 Central Processor Unit (S08CPUV2) 7 0 CONDITION CODE REGISTER V 1 1 H I N Z C CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Field Description 7 V Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.3 Addressing Modes Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. This arrangement means that the same instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile program space.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.3.5 Extended Addressing Mode (EXT) In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte first). 7.3.6 Indexed Addressing Mode Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and two that use the stack pointer as the base reference. 7.3.6.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.3.6.7 SP-Relative, 16-Bit Offset (SP2) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 Special Operations The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
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Chapter 7 Central Processor Unit (S08CPUV2) interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain). For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack as part of the interrupt sequence.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.4.5 BGND Instruction The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug interface.
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Chapter 7 Central Processor Unit (S08CPUV2) 7.5 HCS08 Instruction Set Summary Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction.
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. .
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Chapter 7 Central Processor Unit (S08CPUV2) Operation BRA rel Branch Always (if I = 1) BRCLR n,opr8a,rel DIR (b0) DIR (b1) DIR (b2) DIR (b3) Branch if Bit n in Memory Clear (if (Mn) = 0) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 01 03 05 07 09 0B 0D 0F BRN rel Branch Never (if I = 0) REL 21 rr Branch if Bit n in Memory Set (if (Mn) = 1) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd dd dd dd dd dd dd dd BSET n,opr8a Set Bit n in Memory (Mn ← 1)
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Chapter 7 Central Processor Unit (S08CPUV2) CMP CMP CMP CMP CMP CMP CMP CMP #opr8i opr8a opr16a oprx16,X oprx8,X ,X oprx16,SP oprx8,SP Operation Compare Accumulator with Memory A–M (CCR Updated But Operands Not Changed) Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 A1 B1 C1 D1 E1 F1 9E D1 9E E1 ii dd hh ll ee ff ff ee ff ff Cycles Source Form Address Mode Table 7-2. .
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Chapter 7 Central Processor Unit (S08CPUV2) INC opr8a INCA INCX INC oprx8,X INC ,X INC oprx8,SP Operation Increment M ← (M) + $01 A ← (A) + $01 X ← (X) + $01 M ← (M) + $01 M ← (M) + $01 M ← (M) + $01 Object Code Cycles Source Form Address Mode Table 7-2. .
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Affect on CCR VH I N Z C rpwpp rfwpp pwpp rfwpp 0– – 42 5 ffffp –0 – – – 0 DIR INH INH IX1 IX SP1 30 dd 40 50 60 ff 70 9E 60 ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp No Operation — Uses 1 Bus Cycle INH 9D 1 p –– – – – – Nibble Swap Accumulator A ← (A[3:0]:A[7:4]) INH 62 1 p –– – – – – Inclusive OR Accumulator and Memory A ← (A) | (M) IMM DIR EXT IX2 IX1 IX SP2 SP1 AA BA CA DA EA FA 9E DA 9E EA 2 3 4 4 3 3 5 4 p
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. .
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code VH I N Z C 83 11 sssssvvfppp INH 84 1 p Transfer Accumulator to X (Index Register Low) X ← (A) INH 97 1 p –– – – – – Transfer CCR to Accumulator A ← (CCR) INH 85 1 p –– – – – – DIR INH INH IX1 IX SP1 3D dd 4D 5D 6D ff 7D 9E 6D ff 4 1 1 4 3 5 rfpp p p rfpp rfp prfpp 0– SWI Software Interrupt PC ← (PC) + $0001 Push (PCL); SP ← (SP) – $0001 Push (PCH); SP ← (SP) – $0001 Push (X); SP ← (SP) – $0001 Push (A); SP ← (SP)
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Chapter 7 Central Processor Unit (S08CPUV2) Operation Object Code Cycles Source Form Address Mode Table 7-2. . Instruction Set Summary (Sheet 9 of 9) Cyc-by-Cyc Details Affect on CCR VH I N Z C TXS Transfer Index Reg. to SP SP ← (H:X) – $0001 INH 94 2 fp –– – – – – WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Halt CPU INH 8F 2+ fp...
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Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
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Chapter 7 Central Processor Unit (S08CPUV2) Table 7-3.
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Chapter 8 Analog Comparator (S08ACMPV2) 8.1 Introduction The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). Figure 8-1 shows the MC9S08QG8/4 block diagram with the ACMP highlighted. 8.1.
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Chapter 8 Analog Comparator (S08ACMPV2) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Analog Comparator (S08ACMPV2) 8.1.3 Features The ACMP has the following features: • Full rail-to-rail supply operation. • Less than 40 mV of input offset. • Less than 15 mV of hysteresis. • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. • Option to compare to fixed internal bandgap reference voltage. • Option to allow comparator output to be visible on a pin, ACMPO. 8.1.
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Analog Comparator (S08ACMPV2) Internal Bus Internal Reference ACIE ACBGS ACME ACMP INTERRUPT REQUEST Status & Control Register ACF ACMP+ + – ACMP– set ACF ACMOD ACOPE Interrupt Control Comparator ACMPO Figure 8-2. Analog Comparator (ACMP) Block Diagram MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Analog Comparator (S08ACMPV2) 8.2 External Signal Description The ACMP has two analog input pins, ACMP+ and ACMP– and one digital output pin ACMPO. Each of these pins can accept an input voltage that varies across the full operating voltage range of the MCU. As shown in Figure 8-2, the ACMP– pin is connected to the inverting input of the comparator, and the ACMP+ pin is connected to the comparator non-inverting input if ACBGS is a 0.
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Analog Comparator (S08ACMPV2) 8.3.1 ACMP Status and Control Register (ACMPSC) ACMPSC contains the status flag and control bits which are used to enable and configure the ACMP. 7 6 5 4 3 ACME ACBGS ACF ACIE 0 0 0 0 R 2 1 0 ACO ACOPE ACMOD W Reset: 0 0 0 0 = Unimplemented Figure 8-3. ACMP Status and Control Register Table 8-2. ACMP Status and Control Register Field Descriptions Field 7 ACME Description Analog Comparator Module Enable — ACME enables the ACMP module.
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Analog Comparator (S08ACMPV2) 8.4 Functional Description The analog comparator can be used to compare two analog input voltages applied to ACMP+ and ACMP–; or it can be used to compare an analog input voltage applied to ACMP– with an internal bandgap reference voltage. ACBGS is used to select between the bandgap reference voltage or the ACMP+ pin as the input to the non-inverting input of the analog comparator.
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Analog Comparator (S08ACMPV2) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.1 Introduction The 10-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. Figure 9-1 shows the MC9S08QG8/4 with the ADC module and pins highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 9 Analog-to-Digital Converter (S08ADC10V1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.1.1 Module Configurations This section provides device-specific information for configuring the ADC on MC9S08QG8/4 devices. 9.1.1.1 Analog Supply and Voltage Reference Connections The VDDAD and VREFH sources for the ADC are internally connected to the VDD pin. The VSSAD and VREFL sources for the ADC are internally connected to the VSS pin. 9.1.1.2 Channel Assignments The ADC channel assignments for the MC9S08QG8/4 devices are shown in Table 9-1.
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Chapter 9 Analog-to-Digital Converter (S08ADC10V1) 9.1.1.3 Alternate Clock The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two, or the local asynchronous clock (ADACK) within the module. The alternate clock, ALTCLK, input for the MC9S08QG8/4 MCU devices is not implemented. 9.1.1.4 Hardware Trigger The ADC hardware trigger, ADHWT, is output from the real-time interrupt (RTI) counter.
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Analog-to-Digital Converter (S08ADC10V1) 9.1.2 Features Features of the ADC module include: • Linear successive approximation algorithm with 10 bits resolution. • Up to 28 analog inputs. • Output formatted in 10- or 8-bit right-justified format. • Single or continuous conversion (automatic return to idle after single conversion). • Configurable sample time and conversion speed/power. • Conversion complete flag and interrupt. • Input clock selectable from up to four sources.
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Analog-to-Digital Converter (S08ADC10V1) ADIV ADLPC MODE ADLSMP 2 ADTRG ADCO ADCH 1 ADCCFG complete COCO ADCSC1 ADICLK Compare true AIEN 3 Async Clock Gen ADACK MCU STOP ADCK ÷2 ALTCLK abort transfer sample initialize ••• AD0 convert Control Sequencer ADHWT Bus Clock Clock Divide AIEN 1 COCO 2 ADVIN Interrupt SAR Converter AD27 VREFH Data Registers Sum VREFL Compare true 3 Compare Value Registers ACFGT Value Compare Logic ADCSC2 Figure 9-2.
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Analog-to-Digital Converter (S08ADC10V1) 9.2.1 Analog Power (VDDAD) The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. 9.2.2 Analog Ground (VSSAD) The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected internally to VSS.
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Analog-to-Digital Converter (S08ADC10V1) 7 R 6 5 4 AIEN ADCO 0 0 3 2 1 0 1 1 COCO ADCH W Reset: 0 1 1 1 = Unimplemented or Reserved Figure 9-3. Status and Control Register (ADCSC1) Table 9-3. ADCSC1 Register Field Descriptions Field Description 7 COCO Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (ACFE = 0).
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Analog-to-Digital Converter (S08ADC10V1) Figure 9-4. Input Channel Select (continued) 9.3.
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Analog-to-Digital Converter (S08ADC10V1) Table 9-4. ADCSC2 Register Field Descriptions (continued) Field Description 5 ACFE Compare Function Enable — ACFE is used to enable the compare function. 0 Compare function disabled 1 Compare function enabled 4 ACFGT Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value.
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Analog-to-Digital Converter (S08ADC10V1) R 7 6 5 4 3 2 1 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented or Reserved Figure 9-7. Data Result Low Register (ADCRL) 9.3.5 Compare Value High Register (ADCCVH) This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled.
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Analog-to-Digital Converter (S08ADC10V1) 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset: 0 0 0 0 0 0 0 0 Figure 9-10. Configuration Register (ADCCFG) Table 9-5. ADCCFG Register Field Descriptions Field Description 7 ADLPC Low Power Configuration — ADLPC controls the speed and power configuration of the successive approximation converter. This is used to optimize power consumption when higher sample rates are not required.
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Analog-to-Digital Converter (S08ADC10V1) Table 9-8. Input Clock Select ADICLK Selected Clock Source 00 9.3.8 Bus clock 01 Bus clock divided by 2 10 Alternate clock (ALTCLK) 11 Asynchronous clock (ADACK) Pin Control 1 Register (APCTL1) The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0–7 of the ADC module.
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Analog-to-Digital Converter (S08ADC10V1) Table 9-9. APCTL1 Register Field Descriptions (continued) Field Description 1 ADPC1 ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1. 0 AD1 pin I/O control enabled 1 AD1 pin I/O control disabled 0 ADPC0 ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0. 0 AD0 pin I/O control enabled 1 AD0 pin I/O control disabled 9.3.
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Analog-to-Digital Converter (S08ADC10V1) Table 9-10. APCTL2 Register Field Descriptions (continued) Field Description 1 ADPC9 ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9. 0 AD9 pin I/O control enabled 1 AD9 pin I/O control disabled 0 ADPC8 ADC Pin Control 8 — ADPC8 is used to control the pin associated with channel AD8. 0 AD8 pin I/O control enabled 1 AD8 pin I/O control disabled 9.3.
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Analog-to-Digital Converter (S08ADC10V1) Table 9-11. APCTL3 Register Field Descriptions (continued) Field Description 1 ADPC17 ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17. 0 AD17 pin I/O control enabled 1 AD17 pin I/O control disabled 0 ADPC16 ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16. 0 AD16 pin I/O control enabled 1 AD16 pin I/O control disabled 9.
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Analog-to-Digital Converter (S08ADC10V1) are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the ADIV bits and can be divide-by 1, 2, 4, or 8. 9.4.2 Input Select and Pin Control The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the pins used as analog inputs.
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Analog-to-Digital Converter (S08ADC10V1) 9.4.4.2 Completing Conversions A conversion is completed when the result of the conversion is transferred into the data result registers, ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high at the time that COCO is set.
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Analog-to-Digital Converter (S08ADC10V1) result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm. If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (ADLSMP=1).
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Analog-to-Digital Converter (S08ADC10V1) 9.4.5 Automatic Compare Function The compare function can be configured to check for either an upper limit or lower limit. After the input is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to the compare value, COCO is set.
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Analog-to-Digital Converter (S08ADC10V1) 9.4.7.2 Stop3 Mode With ADACK Enabled If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult the module introduction for configuration information for this MCU. If a conversion is in progress when the MCU enters stop3 mode, it continues until completion.
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Analog-to-Digital Converter (S08ADC10V1) 2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 9.5.1.
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Analog-to-Digital Converter (S08ADC10V1) RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ADCSC1 = $41 CHECK COCO=1? NO YES READ ADCRH THEN ADCRL TO CLEAR COCO BIT CONTINUE Figure 9-14. Initialization Flowchart for Example 9.6 Application Information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 9.6.
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Analog-to-Digital Converter (S08ADC10V1) In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the VSSAD pin. This should be the only ground connection between these supplies if possible. The VSSAD pin makes a good single point ground location. 9.6.1.2 Analog Reference Pins In addition to the analog supplies, the ADC module has connections for two reference voltage inputs.
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Analog-to-Digital Converter (S08ADC10V1) 9.6.2 Sources of Error Several sources of error exist for A/D conversions. These are discussed in the following sections. 9.6.2.1 Sampling Error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.
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Analog-to-Digital Converter (S08ADC10V1) • • Average the result by converting the analog input many times in succession and dividing the sum of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error. Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and averaging. Noise that is synchronous to ADCK cannot be averaged out. 9.6.2.
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Analog-to-Digital Converter (S08ADC10V1) converter yields the lower code (and vice-versa). However, even very small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. This range is normally around ±1/2 LSB and will increase with noise. This error may be reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed in Section 9.6.2.3 will reduce this error.
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Analog-to-Digital Converter (S08ADC10V1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 10 Internal Clock Source (S08ICSV1) 10.1 Introduction The internal clock source (ICS) module provides clock source choices for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by either an internal or an external reference clock. The module can provide this FLL clock or either of the internal or external reference clocks as a source for the MCU system clock.
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Chapter 10 Internal Clock Source (S08ICSV1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Internal Clock Source (S08ICSV1) 10.1.3 Features Key features of the ICS module are: • Frequency-locked loop (FLL) is trimmable for accuracy — 0.
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Internal Clock Source (S08ICSV1) 10.1.4.5 FLL Bypassed External (FBE) In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is supplied from the FLL. 10.1.4.
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Internal Clock Source (S08ICSV1) 10.2 External Signal Description No ICS signal connects off chip. 10.3 Register Definition 10.3.1 ICS Control Register 1 (ICSC1) 7 6 5 4 3 2 1 0 IREFS IRCLKEN IREFSTEN 1 0 0 R CLKS RDIV W Reset: 0 0 0 0 0 Figure 10-3. ICS Control Register 1 (ICSC1) Table 10-1. ICS Control Register 1 Field Descriptions Field Description 7:6 CLKS Clock Source Select — Selects the clock source that controls the bus frequency.
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Internal Clock Source (S08ICSV1) 10.3.2 ICS Control Register 2 (ICSC2) 7 6 5 4 3 2 RANGE HGO LP EREFS 0 0 0 0 1 0 R BDIV ERCLKEN EREFSTEN W Reset: 0 1 0 0 Figure 10-4. ICS Control Register 2 (ICSC2) Table 10-2. ICS Control Register 2 Field Descriptions Field Description 7:6 BDIV Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This controls the bus frequency.
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Internal Clock Source (S08ICSV1) 10.3.3 ICS Trim Register (ICSTRM) 7 6 5 4 3 2 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U U U U U U Figure 10-5. ICS Trim Register (ICSTRM) Table 10-3. ICS Trim Register Field Descriptions Field Description 7:0 TRIM ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
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Internal Clock Source (S08ICSV1) 10.4 Functional Description 10.4.1 Operational Modes The states of the ICS are shown as a state diagram and are described in the following sections. The arrows indicate the allowed movements between the states.
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Internal Clock Source (S08ICSV1) 10.4.1.2 FLL Engaged External (FEE) The FLL engaged external (FEE) mode is entered when all the following conditions occur: • • • CLKS bits are written to 00 IREFS bit is written to 0 RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by the external reference clock.
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Internal Clock Source (S08ICSV1) times the filter frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for BDC communications, and the external reference clock is enabled. 10.4.1.6 FLL Bypassed External Low Power (FBELP) The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur: • CLKS bits are written to 10. • IREFS bit is written to 0. • BDM mode is not active and LP bit is written to 1.
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Internal Clock Source (S08ICSV1) 10.4.4 Low Power Bit Usage The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is not being used. However, in some applications it may be desirable to enable the FLL and allow it to lock for maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0. 10.4.
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Internal Clock Source (S08ICSV1) • • • • BDIV=00 (divide by 1), RDIV ≥ 010 BDIV=01 (divide by 2), RDIV ≥ 011 BDIV=10 (divide by 4), RDIV ≥ 100 BDIV=11 (divide by 8), RDIV ≥ 101 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 11 Inter-Integrated Circuit (S08IICV1) 11.1 Introduction The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF. 11.1.
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Chapter 11 Inter-Integrated Circuit (S08IICV1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Inter-Integrated Circuit (S08IICV1) 11.1.
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Inter-Integrated Circuit (S08IICV1) 11.1.4 Block Diagram Figure 11-2 is a block diagram of the IIC. ADDRESS DATA BUS INTERRUPT ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG INPUT SYNC START STOP ARBITRATION CONTROL CLOCK CONTROL IN/OUT DATA SHIFT REGISTER ADDRESS COMPARE SCL SDA Figure 11-2. IIC Functional Block Diagram 11.2 External Signal Description This section describes each user-accessible pin signal. 11.2.
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Inter-Integrated Circuit (S08IICV1) Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all IIC registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 11.3.1 IIC Address Register (IICA) 7 6 5 4 3 2 1 0 0 R ADDR W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-3.
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Inter-Integrated Circuit (S08IICV1) Table 11-3. IICF Register Field Descriptions Field Description 7:6 MULT IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 Reserved 5:0 ICR IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection.
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Inter-Integrated Circuit (S08IICV1) Table 11-4.
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Inter-Integrated Circuit (S08IICV1) 11.3.3 IIC Control Register (IICC) 7 6 5 4 3 IICEN IICIE MST TX TXAK R W Reset 2 1 0 0 0 0 0 0 RSTA 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-5. IIC Control Register (IICC) Table 11-5. IICC Register Field Descriptions Field Description 7 IICEN IIC Enable — The IICEN bit determines whether the IIC module is enabled. 0 IIC is not enabled. 1 IIC is enabled.
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Inter-Integrated Circuit (S08IICV1) 11.3.4 IIC Status Register (IICS) 7 R 6 TCF 5 4 BUSY IAAS 3 2 0 SRW ARBL 1 0 RXAK IICIF W Reset 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-6. IIC Status Register (IICS) Table 11-6. IICS Register Field Descriptions Field Description 7 TCF Transfer Complete Flag — This bit is set on the completion of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module.
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Inter-Integrated Circuit (S08IICV1) 11.3.5 IIC Data I/O Register (IICD) 7 6 5 4 3 2 1 0 0 0 0 0 R DATA W Reset 0 0 0 0 Figure 11-7. IIC Data I/O Register (IICD) Table 11-7. IICD Register Field Descriptions Field Description 7:0 DATA Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
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Inter-Integrated Circuit (S08IICV1) 11.4 Functional Description This section provides a complete functional description of the IIC module. 11.4.1 IIC Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
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Inter-Integrated Circuit (S08IICV1) 11.4.1.1 START Signal When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 11-8, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. 11.4.1.
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Inter-Integrated Circuit (S08IICV1) 11.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 11-8).
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Inter-Integrated Circuit (S08IICV1) DELAY START COUNTING HIGH PERIOD SCL1 SCL2 SCL INTERNAL COUNTER RESET Figure 11-9. IIC Clock Synchronization 11.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 11.4.1.
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Inter-Integrated Circuit (S08IICV1) 11.6.1 Byte Transfer Interrupt The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of byte transfer. 11.6.2 Address Detect Interrupt When the calling address matches the programmed slave address (IIC address register), the IAAS bit in the status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly. 11.6.
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Inter-Integrated Circuit (S08IICV1) 11.7 1. 2. 3. 4. 1. 2. 3. 4. 5. 6. 7.
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Inter-Integrated Circuit (S08IICV1) Clear IICIF Master Mode ? Y TX N Y RX Tx/Rx ? Arbitration Lost ? N Last Byte Transmitted ? N Clear ARBL Y RXAK=0 ? Last Byte to Be Read ? N N N Y Y IAAS=1 ? Y IAAS=1 ? Y N Address Transfer Y End of Addr Cycle (Master Rx) ? Y Y (Read) 2nd Last Byte to Be Read ? N SRW=1 ? Write Next Byte to IICD Set TXACK =1 TX/RX ? Generate Stop Signal (MST = 0) Y Set TX Mode RX TX N (Write) N Data Transfer ACK from Receiver ? N Switch to Rx Mode
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Inter-Integrated Circuit (S08IICV1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 12 Keyboard Interrupt (S08KBIV2) 12.1 Introduction The keyboard interrupt KBI module provides up to eight independently enabled external interrupt sources. Figure 12-1 Shows the MC9S08QG8/4 block guide with the KBI highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 12 Keyboard Interrupt (S08KBIV2) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Keyboard Interrupts (S08KBIV2) 12.1.1 Features The KBI features include: • Up to eight keyboard interrupt pins with individual pin enable bits. • Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity. • One software enabled keyboard interrupt. • Exit from low-power modes. 12.1.2 Modes of Operation This section defines the KBI operation in wait, stop, and background debug modes.
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Keyboard Interrupts (S08KBIV2) BUSCLK KBACK VDD 1 KBIP0 0 S RESET KBF D CLR Q KBIPE0 SYNCHRONIZER CK KBEDG0 KEYBOARD INTERRUPT FF 1 KBIPn 0 S STOP STOP BYPASS KBI INTERRU PT KBMOD KBIPEn KBIE KBEDGn Figure 12-2. KBI Block Diagram 12.2 External Signal Description The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt requests.
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Keyboard Interrupts (S08KBIV2) R 7 6 5 4 3 2 0 0 0 0 KBF 0 W Reset: 1 0 KBIE KBMOD 0 0 KBACK 0 0 0 0 0 0 = Unimplemented Figure 12-3. KBI Status and Control Register Table 12-2. KBISC Register Field Descriptions Field Description 7:4 Unused register bits, always read 0. 3 KBF Keyboard Interrupt Flag — KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF. 0 No keyboard interrupt detected. 1 Keyboard interrupt detected.
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Keyboard Interrupts (S08KBIV2) 7 6 5 4 3 2 1 0 KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0 0 0 0 0 0 0 0 0 R W Reset: Figure 12-5. KBI Edge Select Register Table 12-4. KBIES Register Field Descriptions Field 7:0 KBEDGn 12.4 Description Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level function of the corresponding pin). 0 Falling edge/low level. 1 Rising edge/high level.
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Keyboard Interrupts (S08KBIV2) KBISC provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK. 12.4.3 KBI Pullup/Pulldown Resistors The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port pullup enable register.
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Keyboard Interrupts (S08KBIV2) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 13 Modulo Timer (S08MTIMV1) 13.1 Introduction The MTIM is a simple 8-bit timer with several software selectable clock sources and a programmable interrupt. The central component of the MTIM is the 8-bit counter, which can operate as a free-running counter or a modulo counter. A timer overflow interrupt can be enabled to generate periodic interrupts for time-based software loops. Figure 13-1 shows the MC9S08QG8/4 block diagram with the MTIM highlighted. 13.1.
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Chapter 13 Modulo Timer (S08MTIMV1) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Modulo Timer (S08MTIMV1) 13.1.
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Modulo Timer (S08MTIMV1) 13.1.4 Block Diagram The block diagram for the modulo timer module is shown Figure 13-2. BUSCLK XCLK TCLK SYNC MTIM INTERRU PT CLOCK SOURCE SELECT PRESCALE AND SELECT DIVIDE BY CLKS PS 8-BIT COUNTER (MTIMCNT) TRST TSTP 8-BIT COMPARATOR TOF 8-BIT MODULO (MTIMMOD) TOIE Figure 13-2. Modulo Timer (MTIM) Block Diagram 13.2 External Signal Description The MTIM includes one external signal, TCLK, used to input an external clock when selected as the MTIM clock source.
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Modulo Timer (S08MTIMV1) Figure 13-3.
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Modulo Timer (S08MTIMV1) 13.3.1 MTIM Status and Control Register (MTIMSC) MTIMSC contains the overflow status flag and control bits which are used to configure the interrupt enable, reset the counter, and stop the counter. 7 R 6 5 TOF 0 TOIE W Reset: 4 3 2 1 0 0 0 0 0 0 0 0 0 TSTP TRST 0 0 0 1 Figure 13-4. MTIM Status and Control Register Table 13-2.
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Modulo Timer (S08MTIMV1) 13.3.2 MTIM Clock Configuration Register (MTIMCLK) MTIMCLK contains the clock select bits (CLKS) and the prescaler select bits (PS). R 7 6 0 0 5 4 3 2 CLKS 1 0 0 0 PS W Reset: 0 0 0 0 0 0 Figure 13-5. MTIM Clock Configuration Register Table 13-3. MTIM Clock Configuration Register Field Description Field 7:6 5:4 CLKS 3:0 PS Description Unused register bits, always read 0.
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Modulo Timer (S08MTIMV1) 13.3.3 MTIMCNT MTIM Counter Register (MTIMCNT) is the read-only value of the current MTIM count of the 8-bit counter. 7 6 5 4 R 3 2 1 0 0 0 0 0 COUNT W Reset: 0 0 0 0 Figure 13-6. MTIM Counter Register Table 13-4. MTIM Counter Register Field Description Field Description 7:0 COUNT MTIM Count — These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register. Reset clears the count to $00. 13.3.
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Modulo Timer (S08MTIMV1) 13.4 Functional Description The MTIM is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with nine selectable values. The module also contains software selectable interrupt logic. The MTIM counter (MTIMCNT) has three modes of operation: stopped, free-running, and modulo. Out of reset, the counter is stopped.
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Modulo Timer (S08MTIMV1) 13.4.1 MTIM Operation Example This section shows an example of the MTIM operation as the counter reaches a matching value from the modulo register. selected clock source MTIM clock (PS=%0010) MTIMCNT $A7 $A8 $A9 $AA $00 $01 TOF MTIMMOD: $AA Figure 13-8. MTIM counter overflow example In the example of Figure 13-8, the selected clock source could be any of the five possible choices. The prescaler is set to PS = %0010 or divide-by-4.
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Chapter 14 Serial Communications Interface (S08SCIV3) 14.1 Introduction Figure 14-1 shows the MC9S08QG8/4 block diagram with the SCI highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 14 Serial Communications Interface (S08SCIV3) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Chapter 14 Serial Communications Interface (S08SCIV3) Module Initialization: Write: SCIBDH:SCIBDL to set baud rate Write: SCFC1 to configure 1-wire/2-wire, 9/8-bit data, wakeup, and parity, if used. Write; SCIC2 to configure interrupts, enable Rx and Tx, RWU Enable Rx wakeup, SBK sends break character Write: SCIC3 to enable Rx error interrupt sources. Also controls pin direction in 1-wire modes. R8 and T8 only used in 9-bit data modes.
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Serial Communications Interface (S08SCIV3) 14.1.
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Serial Communications Interface (S08SCIV3) 14.1.3 Block Diagram Figure 14-3 shows the transmitter portion of the SCI. (Figure 14-4 shows the receiver portion of the SCI.
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Serial Communications Interface (S08SCIV3) Figure 14-4 shows the receiver portion of the SCI.
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Serial Communications Interface (S08SCIV3) 14.2 Register Definition The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data. Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address assignments for all SCI registers. This section refers to registers and control bits only by their names.
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Serial Communications Interface (S08SCIV3) Table 14-2. SCIBDL Register Field Descriptions Field Description 7:0 SBR[7:0] Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 14-1. 14.2.
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Serial Communications Interface (S08SCIV3) Table 14-3. SCIC1 Register Field Descriptions (continued) Field Description 1 PE Parity Enable — Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 No hardware parity generation or checking. 1 Parity enabled. 0 PT Parity Type — Provided parity is enabled (PE = 1), this bit selects even or odd parity.
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Serial Communications Interface (S08SCIV3) Table 14-4. SCIC2 Register Field Descriptions (continued) Field Description 2 RE Receiver Enable — When the SCI receiver is off, the RxD pin reverts to being a general-purpose port I/O pin. If LOOPS = 1, the RxD pin reverts to being a general-purpose I/O pin even if RE = 1. 0 Receiver off. 1 Receiver on.
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Serial Communications Interface (S08SCIV3) Table 14-5. SCIS1 Register Field Descriptions (continued) Field Description 5 RDRF Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive data register (SCID). To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register (SCID). 0 Receive data register empty. 1 Receive data register full.
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Serial Communications Interface (S08SCIV3) 14.2.5 SCI Status Register 2 (SCIS2) This register has one read-only status flag. Writes have no effect. R 7 6 5 4 3 0 0 0 0 0 2 1 0 0 RAF 0 0 BRK13 W Reset 0 0 0 0 0 0 = Unimplemented or Reserved Figure 14-10. SCI Status Register 2 (SCIS2) Table 14-6. SCIS2 Register Field Descriptions Field 2 BRK13 0 RAF 14.2.6 Description Break Character Length — BRK13 is used to select a longer break character length.
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Serial Communications Interface (S08SCIV3) Table 14-7. SCIC3 Register Field Descriptions (continued) Field 1 Description 5 TXDIR TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation (LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin. 0 TxD pin is an input in single-wire mode. 1 TxD pin is an output in single-wire mode. 4 TXINV1 Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
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Serial Communications Interface (S08SCIV3) 14.3 Functional Description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
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Serial Communications Interface (S08SCIV3) selecting the normal 8-bit data mode. In 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit.
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Serial Communications Interface (S08SCIV3) 14.3.3 Receiver Functional Description In this section, the receiver block diagram (Figure 14-4) is used as a guide for the overall receiver functional description. Next, the data sampling technique used to reconstruct receiver data is described in more detail. Finally, two variations of the receiver wakeup function are explained. The receiver is enabled by setting the RE bit in SCIC2.
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Serial Communications Interface (S08SCIV3) In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared. The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set. 14.3.3.2 Receiver Wakeup Operation Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended for a different SCI receiver.
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Serial Communications Interface (S08SCIV3) masked by local interrupt enable masks. The flags can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit data register empty (TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCID.
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Serial Communications Interface (S08SCIV3) If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the same time data is transferred from SCID to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit.
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Serial Communications Interface (S08SCIV3) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 15 Serial Peripheral Interface (S08SPIV3) 15.1 Introduction Figure 15-1 shows the MC9S08QG8/4 block diagram with the SPI highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 15 Serial Peripheral Interface (S08SPIV3) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Serial Peripheral Interface (S08SPIV3) 15.1.1 Features Features of the SPI module include: • Master or slave mode operation • Full-duplex or single-wire bidirectional option • Programmable transmit bit rate • Double-buffered transmit and receive • Serial clock phase and polarity options • Slave select output • Selectable MSB-first or LSB-first shifting 15.1.
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Serial Peripheral Interface (S08SPIV3) The most common uses of the SPI system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial A/D or D/A converters. Although Figure 15-2 shows a system where data is exchanged between two MCUs, many practical systems involve simpler connections where data is unidirectionally transferred from the master MCU to a slave or from a slave to the master MCU. 15.1.2.
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Serial Peripheral Interface (S08SPIV3) PIN CONTROL M SPE MOSI (MOMI) S Tx BUFFER (WRITE SPID) ENABLE SPI SYSTEM M SHIFT OUT SPI SHIFT REGISTER SHIFT IN MISO (SISO) S SPC0 Rx BUFFER (READ SPID) BIDIROE SHIFT DIRECTION LSBFE SHIFT CLOCK Rx BUFFER FULL Tx BUFFER EMPTY MASTER CLOCK BUS RATE CLOCK SPIBR CLOCK GENERATOR MSTR CLOCK LOGIC SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE MODE SELECT MODFEN SSOE MODE FAULT DETECTION SPRF SS SPTEF SPTIE MODF SPIE SPI INTERRUPT REQUEST Fi
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Serial Peripheral Interface (S08SPIV3) BUS CLOCK PRESCALER CLOCK RATE DIVIDER DIVIDE BY 1, 2, 3, 4, 5, 6, 7, or 8 DIVIDE BY 2, 4, 8, 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 MASTER SPI BIT RATE Figure 15-4. SPI Baud Rate Generation 15.2 External Signal Description The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control bits.
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Serial Peripheral Interface (S08SPIV3) 15.3 Modes of Operation 15.3.1 SPI in Stop Modes The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction. During either stop1 or stop2 mode, the SPI module will be fully powered down. Upon wake-up from stop1 or stop2 mode, the SPI module will be in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are affected.
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Serial Peripheral Interface (S08SPIV3) Table 15-1. SPIC1 Field Descriptions (continued) Field Description 4 MSTR Master/Slave Mode Select 0 SPI module configured as a slave SPI device 1 SPI module configured as a master SPI device 3 CPOL Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device. Refer to Section 15.5.1, “SPI Clock Formats” for more details.
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Serial Peripheral Interface (S08SPIV3) Table 15-3. SPIC2 Register Field Descriptions Field Description 4 MODFEN Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer to Table 15-2 for more details).
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Serial Peripheral Interface (S08SPIV3) Table 15-5. SPI Baud Rate Prescaler Divisor SPPR2:SPPR1:SPPR0 Prescaler Divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 Table 15-6. SPI Baud Rate Divisor 15.4.4 SPR2:SPR1:SPR0 Rate Divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 SPI Status Register (SPIS) This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0.
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Serial Peripheral Interface (S08SPIV3) Table 15-7. SPIS Register Field Descriptions Field Description 7 SPRF SPI Read Buffer Full Flag — SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.
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Serial Peripheral Interface (S08SPIV3) 15.5 Functional Description An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer starts.
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Serial Peripheral Interface (S08SPIV3) MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave. BIT TIME # (REFERENCE) 1 2 ...
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Serial Peripheral Interface (S08SPIV3) in LSBFE. Both variations of SPSCK polarity are shown, but only one of these waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1).
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Serial Peripheral Interface (S08SPIV3) 15.5.2 SPI Interrupts There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI transmit buffer empty flag (SPTEF).
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Serial Peripheral Interface (S08SPIV3) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Chapter 16 Timer/Pulse-Width Modulator (S08TPMV2) 16.1 Introduction Figure 16-1 shows the MC9S08QG8/4 block diagram with the TPM highlighted. 16.1.1 ACMP/TPM Configuration Information The ACMP module can be configured to connect the output of the analog comparator to TPM input capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPMCH0 pin is not available externally regardless of the configuration of the TPM module. 16.1.
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Chapter 16 Timer/Pulse-Width Modulator (S08TPMV2) BKGD/MS IRQ HCS08 CORE DEBUG MODULE (DBG) BDC RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT RTI COP IRQ LVD USER FLASH (MC9S08QG8 = 8192 BYTES) (MC9S08QG4 = 4096 BYTES) USER RAM (MC9S08QG8 = 512 BYTES) (MC9S08QG4 = 256 BYTES) 16-MHz INTERNAL CLOCK SOURCE (ICS) LOW-POWER OSCILLATOR 31.25 kHz to 38.
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Timer/Pulse-Width Modulator (S08TPMV2) 16.1.
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Timer/Pulse-Width Modulator (S08TPMV2) BUSCLK XCLK TPMxCLK SYNC CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT CLKSB PRESCALE AND SELECT DIVIDE BY 1, 2, 4, 8, 16, 32, 64, or 128 PS2 CLKSA PS1 PS0 CPWMS MAIN 16-BIT COUNTER TOF COUNTER RESET INTERRUPT LOGIC TOIE 16-BIT COMPARATOR TPMMODH:TPMMODL CHANNEL 0 ELS0B ELS0A PORT LOGIC 16-BIT COMPARATOR TPMC0VH:TPMC0VL CH0F INTERRUPT LOGIC MS0B MS0A ELS1B ELS1A CH0IE TPMC1VH:TPMC1VL CH1F INTERRUPT LOGIC 16-BIT LATCH MS1A ELSnB ELSnA ...
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Timer/Pulse-Width Modulator (S08TPMV2) All TPM channels are programmable independently as input capture, output compare, or buffered edge-aligned PWM channels. 16.2 External Signal Description When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled. After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. 16.2.
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Timer/Pulse-Width Modulator (S08TPMV2) Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 16.3.1 Timer Status and Control Register (TPMSC) TPMSC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this timer module.
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Timer/Pulse-Width Modulator (S08TPMV2) Table 16-2. TPM Clock Source Selection CLKSB:CLKSA TPM Clock Source to Prescaler Input 0:0 No clock selected (TPM disabled) 0:1 Bus rate clock (BUSCLK) 1:0 Fixed system clock (XCLK) 1:1 External source (TPMCLK)1,2 1 The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency.
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Timer/Pulse-Width Modulator (S08TPMV2) R 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 W Reset Any write to TPMCNTL clears the 16-bit counter. 0 0 0 0 0 0 Figure 16-5. Timer Counter Register Low (TPMCNTL) When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. 16.3.
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Timer/Pulse-Width Modulator (S08TPMV2) 16.3.4 Timer Channel n Status and Control Register (TPMCnSC) TPMCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. 7 6 5 4 3 2 CHnF CHnIE MSnB MSnA ELSnB ELSnA 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 16-8. Timer Channel n Status and Control Register (TPMCnSC) Table 16-4.
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Timer/Pulse-Width Modulator (S08TPMV2) Table 16-5.
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Timer/Pulse-Width Modulator (S08TPMV2) In output compare or PWM modes, writing to either byte (TPMCnVH or TPMCnVL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 16.
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Timer/Pulse-Width Modulator (S08TPMV2) When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the terminal count value (value in TPMMODH:TPMMODL) are normal length counts (one timer clock period long). An interrupt flag and enable are associated with the main 16-bit counter.
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Timer/Pulse-Width Modulator (S08TPMV2) 16.4.2.2 Output Compare Mode With the output compare function, the TPM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an output compare channel, the TPM can set, clear, or toggle the channel pin.
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Timer/Pulse-Width Modulator (S08TPMV2) 16.4.3 Center-Aligned PWM Mode This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The output compare value in TPMCnVH:TPMCnVL determines the pulse width (duty cycle) of the PWM signal and the period is determined by the value in TPMMODH:TPMMODL. TPMMODH:TPMMODL should be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output.
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Timer/Pulse-Width Modulator (S08TPMV2) transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter overflows (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). This TPMCNT overflow requirement only applies to PWM channels, not output compares. Optionally, when TPMCNTH:TPMCNTL = TPMMODH:TPMMODL, the TPM can generate a TOF interrupt at the end of this count.
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Timer/Pulse-Width Modulator (S08TPMV2) 16.5.3 Channel Event Interrupt Description The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned PWM, or center-aligned PWM). When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is set.
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Chapter 17 Development Support 17.1 Introduction Development support systems in the HCS08 include the background debug controller (BDC) and the on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories.
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Development Support 17.1.
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Development Support • read or written, and allow the user to trace one user instruction at a time, or GO to the user program from active background mode. Non-intrusive commands can be executed at any time even while the user’s program is running. Non-intrusive commands allow a user to read or write MCU memory locations or access status and control registers within the background debug controller.
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Development Support driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Section 17.2.2, “Communication Details,” for more detail. When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after reset.
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Development Support BDC CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 10 CYCLES SYNCHRONIZATION UNCERTAINTY EARLIEST START OF NEXT BIT TARGET SENSES BIT LEVEL PERCEIVED START OF BIT TIME Figure 17-2. BDC Host-to-Target Serial Bit Timing Figure 17-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU.
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Development Support Figure 17-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
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Development Support / d AAAA RD WD RD16 WD16 SS CC RBKP = = = = = = = = = = WBKP = Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) separates parts of the command delay 16 target BDC clock cycles a 16-bit address in the host-to-target direction 8 bits of read data in the target-to-host direction 8 bits of write data in the host-to-target direction 16 bits of read data in the target-to-host direction 16 bits of write data in the host-to-t
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Development Support Table 17-1. BDC Command Summary Command Mnemonic 1 Active BDM/ Non-intrusive Coding Structure Description SYNC Non-intrusive n/a1 Request a timed reference pulse to determine target BDC communication speed ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D. ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to Freescale document order no. HCS08RMv1/D.
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Development Support The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications speed to use for BDC communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host: • Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.
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Development Support 17.3 On-Chip Debug System (DBG) Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus information, and a flexible trigger system to decide when to capture bus information and what information to capture.
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Development Support the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO. In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO data port) causes the FIFO to shift so the next word of information is available at the FIFO data port.
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Development Support A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests from the debug module to the CPU.
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Development Support A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched the value in comparator A. There can be any number of cycles after the A match and before the B match. A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally) must match within the same bus cycle to cause a trigger event.
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Development Support 17.3.6 Hardware Breakpoints The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in Section 17.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction queue.
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Development Support 17.4.1.1 BDC Status and Control Register (BDCSCR) This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to user programs because it is not located in the normal memory map of the MCU. 7 R 6 5 4 3 BKPTEN FTS CLKSW BDMACT ENBDM 2 1 0 WS WSF DVF W Normal Reset 0 0 0 0 0 0 0 0 Reset in Active BDM: 1 1 0 0 1 0 0 0 = Unimplemented or Reserved Figure 17-5.
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Development Support Table 17-2. BDCSCR Register Field Descriptions (continued) Field Description 2 WS Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function. However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active background mode where all BDC commands work.
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Development Support R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 BDFR1 W Reset 0 0 0 0 0 0 0 0 = Unimplemented or Reserved 1 BDFR is writable only through serial background mode debug commands, not from user programs. Figure 17-6. System Background Debug Force Reset Register (SBDFR) Table 17-3.
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Development Support 17.4.3.5 Debug FIFO High Register (DBGFH) This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used and will read 0x00. Reading DBGFH does not cause the FIFO to shift to the next word.
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Development Support 17.4.3.7 Debug Control Register (DBGC) This register can be read or written at any time. 7 6 5 4 3 2 1 0 DBGEN ARM TAG BRKEN RWA RWAEN RWB RWBEN 0 0 0 0 0 0 0 0 R W Reset Figure 17-7. Debug Control Register (DBGC) Table 17-4. DBGC Register Field Descriptions Field Description 7 DBGEN Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.
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Development Support 17.4.3.8 Debug Trigger Register (DBGT) This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired to 0s. 7 6 TRGSEL BEGIN 0 0 R 5 4 0 0 3 2 1 0 TRG3 TRG2 TRG1 TRG0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 17-8. Debug Trigger Register (DBGT) Table 17-5.
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Development Support R 7 6 5 4 3 2 1 0 AF BF ARMF 0 CNT3 CNT2 CNT1 CNT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 17-9. Debug Status Register (DBGS) Table 17-6. DBGS Register Field Descriptions Field Description 7 AF Trigger Match A Flag — AF is cleared at the start of a debug run and indicates whether a trigger match A condition was met since arming.
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Development Support MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Appendix A Electrical Characteristics A.1 Introduction This section contains electrical and timing specifications. A.2 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section.
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Appendix A Electrical Characteristics A.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design.
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Appendix A Electrical Characteristics Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273°C) Eqn. A-2 Solving Equation A-1 and Equation A-2 for K gives: K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. A-3 where K is a constant pertaining to the particular part.
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Appendix A Electrical Characteristics A.4 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
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Appendix A Electrical Characteristics A.5 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table A-5. Operating Range Parameter Supply voltage (run, wait and stop modes.) Symbol Min VDD 1.81 Typical Max Unit 3.6 V 85 125 °C Temperature C M 1 –40 –40 — — As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. Table A-6.
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Appendix A Electrical Characteristics Table A-6. DC Characteristics (continued) Parameter Internal pulldown resistor (KBI) Symbol Min RPD Output high voltage — low drive (PTxDSn = 0) IOH = –2 mA (VDD ≥ 1.8 V) Output high voltage — high drive (PTxDSn = 1) IOH = –10 mA (VDD ≥ 2.7 V) IOH = –6 mA (VDD ≥ 2.3 V) IOH = –3 mA (VDD ≥ 1.8 V) Maximum total IOH for all port pins 2 3 4 5 6 7 Max Unit 17.5 52.5 kΩ VDD – 0.5 — VOH | IOHT | Output low voltage — low drive (PTxDSn = 0) IOL = 2.0 mA (VDD ≥ 1.
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Appendix A Electrical Characteristics PULLUP RESISTOR TYPICALS 85°C 25°C –40°C 35 30 25 20 1.8 2 2.2 2.4 2.6 2.8 VDD (V) 3 3.2 3.4 PULLDOWN RESISTOR TYPICALS 40 PULLDOWN RESISTOR (kΩ) PULLUP RESISTOR (kΩ) 40 35 30 25 20 3.6 85°C 25°C –40°C 1.8 2.3 2.8 VDD (V) 3.3 3.6 Figure A-1. Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V) TYPICAL VOL VS IOL AT VDD = 3.0 V 1.2 1 0.15 VOL (V) 0.8 VOL (V) TYPICAL VOL VS VDD 0.2 85°C 25°C –40°C 0.6 0.4 0.2 0.
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Appendix A Electrical Characteristics TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 1.2 85°C 25°C –40°C 85°C, IOH = 2 mA 25°C, IOH = 2 mA –40°C, IOH = 2 mA 0.2 VDD – VOH (V) VDD – VOH (V) 1 TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.25 0.8 0.6 0.4 0.15 0.1 0.05 0.2 0 0 0 –5 –10 IOH (mA)) –15 –20 1 2 VDD (V) 3 4 Figure A-4. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0) TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.4 TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 0.
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Appendix A Electrical Characteristics Table A-7. Supply Current Characteristics Parameter Symbol RTI adder to stop1, stop2 or stop3 4 — LVD adder to stop3 (LVDE = LVDSE = 1) — Adder to stop3 for oscillator enabled 5 (EREFSTEN =1) — VDD (V)1 Typical2 Max T (°C) 3 300 nA — 85 2 300 nA — 85 3 70 μA — 85 2 60 μA — 85 3 5 μA — 85 2 4 μA — 85 1 3-V values are 100% tested; 2-V values are characterized but not tested. Typicals are measured at 25°C.
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Appendix A Electrical Characteristics A.7 External Oscillator (XOSC) and Internal Clock Source (ICS) Characteristics Reference Figure A-7 for crystal or resonator circuit. Table A-8. XOSC and ICS Specifications (Temperature Range = –40 to 125°C Ambient) Characteristic Internal reference frequency — factory trimmed at VDD = 3.
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Appendix A Electrical Characteristics Table A-8. XOSC and ICS Specifications (Temperature Range = –40 to 125°C Ambient) Characteristic Resolution of trimmed DCO output frequency at fixed voltage and temperature 4 Symbol Min Typ Max Unit Δfdco_res_t — ±0.1 ± 0.2 %fdco — –1.5 to ±0.5 ±3 — –1.0 to ±0.5 ±2 — ±0.
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Appendix A Electrical Characteristics A.8 AC Characteristics This section describes timing characteristics for each peripheral system. A.8.1 Control Timing Table A-9. Control Timing Symbol Min Typ1 Max Unit Bus frequency (tcyc = 1/fBus) fBus 0 — 10 MHz Real-time interrupt internal oscillator period tRTI 700 1000 1300 μs textrst 100 — — ns IRQ pulse width Asynchronous path2 Synchronous path3 tILIH 100 1.
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Appendix A Electrical Characteristics Period (μs) 1600 1400 1200 1000 800 600 400 200 0 –40 –20 0 20 40 Temperature (°C) 60 80 100 120 140 Figure A-8. Typical RTI Clock Period vs. Temperature textrst RESET PIN Figure A-9. Reset Timing tIHIL KBIPx IRQ/KBIPx tILIH Figure A-10. IRQ/KBIPx Timing A.8.2 TPM/MTIM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter.
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Appendix A Electrical Characteristics Table A-10. TPM/MTIM Input Timing Function Symbol Min Max Unit External clock frequency fTCLK 0 fBus/4 Hz External clock period tTCLK 4 — tcyc External clock high time tclkh 1.5 — tcyc External clock low time tclkl 1.5 — tcyc tICPW 1.5 — tcyc Input capture pulse width tTCLK tclkh TCLK tclkl Figure A-11. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure A-12. Timer Input Capture Pulse A.8.
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Appendix A Electrical Characteristics Table A-11. SPI Timing (continued) No.
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Appendix A Electrical Characteristics SS1 (OUTPUT) 11 1 2 SPSCK (CPOL = 0) (OUTPUT) 3 4 4 12 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 9 LSB IN 10 9 MOSI (OUTPUT) BIT 6 . . . 1 MSB OUT2 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-13.
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Appendix A Electrical Characteristics SS (INPUT) 1 12 11 11 12 3 SPSCK (CPOL = 0) (INPUT) 2 4 4 SPSCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) MSB OUT SLAVE BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 6 5 MOSI (INPUT) 10 10 9 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure A-15.
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Appendix A Electrical Characteristics A.9 Analog Comparator (ACMP) Electricals Table A-12. Analog Comparator Electrical Specifications Characteristic Symbol Min Typical Max Unit VDD 1.80 — 3.6 V Supply current (active) IDDAC — 20 — μA Analog input voltage VAIN VSS – 0.3 — VDD V Analog input offset voltage VAIO 20 40 mV Supply voltage Analog comparator hysteresis VH 3.0 9.0 15.0 mV Analog input leakage current IALKG — — 1.
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Appendix A Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN + VADIN VAS + – CAS – RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure A-17. ADC Input Impedance Equivalency Diagram Table A-14.
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Appendix A Electrical Characteristics Table A-14. 3 Volt 10-bit ADC Characteristics (continued) Conditions Symb Min Typ1 Max Unit Comment Short sample (ADLSMP=0) tADC — 20 — — 40 — ADCK cycles — 3.5 — See Table 9-12 for conversion time variances — 23.5 — — ±1.5 ±3.5 — ±0.7 ±1.5 — ±0.5 ±1.0 — ±0.3 ±0.5 — ±0.5 ±1.0 — ±0.3 ±0.5 — ±1.5 ±2.1 — ±0.5 ±0.7 0 ±1.0 ±1.5 0 ±0.5 ±0.5 — — ±0.5 — — ±0.5 0 ±0.2 ±4 0 ±0.1 ±1.2 — 1.646 — — 1.
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Appendix A Electrical Characteristics A.11 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table A-15. FLASH Characteristics Characteristic Symbol Min Typical Max Unit Vprog/erase 1.8 — 3.6 V 2.1 — 3.6 VRead 1.8 — 3.
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Appendix A Electrical Characteristics A.12 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance.
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Appendix A Electrical Characteristics Table A-17. Conducted Susceptibility, EFT/B Parameter Symbol Conducted susceptibility, electrical fast transient/burst (EFT/B) 1 VCS_EFT Conditions VDD = 3.3V TA = +25oC package type TBD fOSC/fBUS TBD crystal TBD bus Result Amplitude1 (Min) A TBD B TBD C TBD D TBD Unit kV Data based on qualification test results. Not tested in production. The susceptibility performance classification is described in Table A-18. Table A-18.
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Appendix A Electrical Characteristics MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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Appendix B Ordering Information and Mechanical Drawings B.1 Ordering Information This section contains ordering information for MC9S08QG8 and MC9S08QG4 devices. Table B-1. Device Numbering System 1 2 Available Packages2 Memory Device Number1 FLASH RAM 24-Pin 16-Pin 8-Pin MC9S08QG8 8K 512 24 QFN 16 PDIP 16 QFN 16 TSSOP 8 DFN 8 NB SOIC MC9S08QG4 4K 256 24 QFN 16 QFN 16 TSSOP 8 DFN 8 PDIP 8 NB SOIC See Table 1-1 for a complete description of modules included on each device.
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Appendix B Ordering Information and Mechanical Drawings Table B-2. Package Information (continued) Pin Count Type Designator Document No. 8 DFN FQ 98ARL10557D 8 PDIP PA 98ASB42420B 8 NB SOIC DN 98ASB42564B MC9S08QG8 and MC9S08QG4 Data Sheet, Rev.
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.