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Table Of Contents

List of Sections
Table of Contents
General Description
- Contents
- Introduction
- Features
- MC9S12DP256 112-Pin Block Diagram
- Ordering Information
Central Processing Unit (CPU)
- Contents
- Introduction
- Programming Model
- Data Types
- Addressing Modes
- Indexed Addressing Modes
- Opcodes and Operands
- Instruction Set Summary
Pinout and Signal Description
- Contents
- MC9S12DP256 Pin Assignments in 112-pin QFP
- Power Supply Pins
- Signal Descriptions
- Port Signals
System Configuration
- Contents
- Introduction
- Modules Variabilities
- MCU Variabilities
Registers
- Contents
- Register Block
Operating Modes
- Contents
- Introduction
- Operating Modes
- Background Debug Mode
- Security
Resource Mapping
- Contents
- Introduction
- Internal Resource Mapping
- Flash EEPROM mapping through internal Memory Expansion
- Miscellaneous System Control Register
- Memory Maps
Bus Control and Input/Output
- Contents
- Introduction
- Detecting Access Type from External Signals
- Stretched Bus Cycles
- PIPE Status Signals
- Registers
Resets and Interrupts
- Contents
- Introduction
- Register Map
- Exception Priority
- Maskable interrupts
- Latching of Interrupts
- Register Descriptions
- Resets
- Effects of Reset
- Register Stacking
Voltage Regulator (VREG)
- Contents
- Overview
- Features
- Block Diagram
- Functional Description
- External Pin Connection
- Reset Initialization
- Modes of Operation
Flash EEPROM 256K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
EEPROM 4K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Interrupt Operation
Port Integration Module
- Contents
- Overview
- Block Diagram
- External Pin Descriptions
- 80 Pin QFP bond-out version
- Register Map
- Register Descriptions
- Reset Initialization
- Functional Description
- Low Power Options
- Interrupt Operation
Clocks and Reset Generator (CRG)
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Interrupt Operation
- Low Power Options
Pulse Width Modulator (PWM)
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Register Descriptions
- Functional Description
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
Enhanced Capture Timer (ECT)
- Contents
- Overview
- Features
- Modes of Operation
- Abbreviations
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Modes of Operation
- Interrupts
- Description of Interrupt Operation
Serial Communications Interface (SCI)
- Contents
- Overview
- Features
- Modes of Operation
- SCI Interface Diagram
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Modes of Operation
- Interrupt Operation
Serial Peripheral Interface (SPI)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Low Power Mode Options
- Errata
- Reset
- Interrupts
Inter-IC Bus (IIC)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- I-Bus Protocol
- Interrupt Operation
- Modes of Operation
- Programming
MSCAN
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Functional Description
- Register Descriptions
- Modes of Operation
- Low Power Options
- Interrupt Operation
Analog to Digital Converter
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Sample Conversion
- General Purpose Input Ports
Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
Background Debug Module (BDM)
- Contents
- Overview
- Interface Signals
- Registers
- Operation
- Modes of Operation
- Low-Power Options
- Interrupt Operation
Breakpoint (BKP) Module
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Descriptions
- Functional Description
- Breakpoint Operating Modes
- Breakpoint Types
- Modes of Operation
- Low Power Options
- Reset Initialization
- Interrupt Operation
- General Purpose I/O Ports
Revision History
- Changes from Rev 1.0 to Rev 1.1
Glossary
Literature Updates
- Literature Distribution Centers
- Customer Focus Center
- Microcontroller Division’s Web Site

MC9S12DP256/D

MC9S12DP256

Advance Information

December 1, 2000 Ñ Revision 1.1

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

Summary of content (748 pages)

PAGE 1
Freescale Semiconductor, Inc. MC9S12DP256/D Freescale Semiconductor, Inc... MC9S12DP256 Advance Information December 1, 2000 Ñ Revision 1.1 For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. List of Sections List of Sections List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Freescale Semiconductor, Inc... Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . 19 Pinout and Signal Description . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Sections Clocks and Reset Generator (CRG). . . . . . . . . . . . . . 257 Pulse Width Modulator (PWM). . . . . . . . . . . . . . . . . . . 297 Enhanced Capture Timer (ECT) . . . . . . . . . . . . . . . . . 341 Serial Communications Interface (SCI) . . . . . . . . . . . 389 Freescale Semiconductor, Inc... Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . 429 Inter-IC Bus (IIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 MSCAN . . . .
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Freescale Semiconductor, Inc. Table of Contents Table of Contents List of Sections Freescale Semiconductor, Inc... Table of Contents General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MC9S12DP256 112-Pin Block Diagram . .
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table of Contents Registers Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Operating Modes Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 External Pin Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Reset Initialization . . . . . .
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table of Contents External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Pin QFP bond-out version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Initialization . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table of Contents Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Module Memory Map . . . . . .
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Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Inter-IC Bus (IIC) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 Sample Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 General Purpose Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 Byte Data Link Controller Module Contents .
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Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoint Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoint Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. General Description General Description Freescale Semiconductor, Inc... Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MC9S12DP256 112-Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 16 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. General Description Features • 16-bit STAR12 CPU – Upward compatible with M68HC11 instruction set – Interrupt stacking and programmer’s model identical to M68HC11 Freescale Semiconductor, Inc... – 20-bit ALU – Instruction pipe – Enhanced indexed addressing • Multiplexed External Bus • Memory – 256K byte Flash EEPROM – 4.0K byte EEPROM – 12.0K byte RAM • Two 8 channel Analog-to-Digital Converters – 10-bit resolution • Five 1M bit per second, CAN 2.
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Freescale Semiconductor, Inc. General Description Features • 8 PWM channels with programmable period and duty cycle – Standard 8-bit 8-channel or 16-bit 4-channel or any combination of 8/16 bit – Separate control for each pulse width and duty cycle – Left-aligned or center-aligned outputs Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. General Description MC9S12DP256 112-Pin Block Diagram Internal Logic 2.5V VDD1,2 VSS1,2 PLL 2.5V VDDPLL VSSPLL BDLC (J1850) CAN0 CAN2 VDDX VSSX A/D Converter 5V & Voltage Regulator Reference VDDA VSSA Voltage Regulator 5V & I/O VDDR VSSR Note: This block diagram is for the 112-pin version. Pins in bold are not availble in the 80-pin version.
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Freescale Semiconductor, Inc. General Description Ordering Information Ordering Information Table 1 MC9S12DP256 Device Ordering Information Temperature Package Freescale Semiconductor, Inc... 112-Pin QFP Range Designator –40 to +125°C C, V, M Voltage Frequency Order Number 5V 25MHz TBD Table 2 MC9S12DP256 Development Tools Ordering Information Description Details Order Number TBD MC9S12DP256 — Revision 1.1 General Description For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... General Description MC9S12DP256 — Revision 1.1 General Description For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Central Processing Unit (CPU) Freescale Semiconductor, Inc... Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Programming Model STAR12 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. 7 A 0 7 B 0 8-BIT ACCUMULATORS A & B Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Programming Model Index registers X and Y are used for indexed addressing mode. In the indexed addressing mode, the contents of a 16-bit index register are added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator to form the effective address of the operand to be used in the instruction. Stack and Memory Layout Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) temporary storage of data. The stack pointer can also be used in all indexed addressing modes. Freescale Semiconductor, Inc... Program counter is a 16-bit register that holds the address of the next instruction to be executed. The program counter can be used in all indexed addressing modes except autoincrement/decrement. Condition Code Register (CCR) contains five status indicators, two interrupt masking bits, and a STOP disable bit.
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Addressing Modes Addressing Modes Addressing modes determine how the CPU accesses memory locations to be operated upon. The STAR12 CPU includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed addressing. Table 3 is a summary of the available addressing modes. Table 3 M68HC12 Addressing Mode Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Indexed Addressing Modes Freescale Semiconductor, Inc... The STAR12 CPU indexed modes reduce execution time and eliminate code size penalties for using the Y index register. STAR12 CPU indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode.
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Opcodes and Operands Opcodes and Operands Freescale Semiconductor, Inc... The STAR12 CPU uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers.
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary The following table defines the special characters used to describe the effects of instruction execution on the status bits in the condition codes register (SXHINZVC column). Special Character Description - Status bit not affected by operation. 0 Status bit cleared by operation. 1 Status bit set by operation. Source Form || Status bit may be cleared or remain set, but is not set by operation.
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary Source Form LSRD Address Mode Operation Logical shift right D Machine Coding (Hex) Access Detail SXHINZVC INH 49 O – – – – 0 ∆ ∆ ∆ 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pinout and Signal Description Pinout and Signal Description Freescale Semiconductor, Inc... Contents MC9S12DP256 Pin Assignments in 112-pin QFP . . . . . . . . . . . . . . . 41 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Pinout and Signal Description MC9S12DP256 Pin Assignments in 112-pin QFP 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X G X X=L, M OR N VIEW Y Freescale Semiconductor, Inc... B L V M B1 28 AA J V1 57 29 F D 56 0.13 N M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 S1 A S C2 C VIEW AB θ2 0.050 0.10 T 112X SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.
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Freescale Semiconductor, Inc. Pinout and Signal Description Power Supply Pins Freescale Semiconductor, Inc... MC9S12DP256 power and ground pins are described below and summarized in Table 6. External Power (VDDX) and Ground (VSSX) External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Pinout and Signal Description Power Supply Pins VDDPLL, VSSPLL Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 2.5V voltage is generated by the internal voltage regulator. VREGEN Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally.
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Freescale Semiconductor, Inc. Pinout and Signal Description Table 6 MC9S12DP256 Power and Ground Connection Summary Freescale Semiconductor, Inc... Pin Number 112-pin QFP Nominal Voltage VDD1, 2 13, 65 2.5 V VSS1, 2 14, 66 0V VDDR 41 5.0 V VSSR 40 0V VDDX 107 5.0 V VSSX 106 0V VDDA 83 5.0 V VSSA 86 0V VRL 85 0V VRH 84 5.0 V VDDPLL 43 2.
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Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions Signal Descriptions Freescale Semiconductor, Inc... Crystal Driver and External Clock Input (XTAL, EXTAL) These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. Out of reset the frequency applied to EXTAL is two times the desired ECLK rate. NOTE: CRYSTAL CIRCUIT IS CHANGED FROM STANDARD.
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Freescale Semiconductor, Inc. Pinout and Signal Description Freescale Semiconductor, Inc... port PE7 (XCLKS) low during the reset phase the internal low current oscillator is bypassed and an internal buffer driven by EXTAL feeds the internal clocks. The XTAL output is normally intended to drive only a crystal. The XTAL output can be buffered with a high-impedance buffer to drive the EXTAL input of another device. The maximum output voltage of this pin is VDDPLL.
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Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions Freescale Semiconductor, Inc... Reset (RESET) RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. The MCU goes into reset asynchronously and comes out of reset synchronously.
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Freescale Semiconductor, Inc. Pinout and Signal Description Freescale Semiconductor, Inc... vector ($FFFE:FFFF) is taken when RESET is finally released. If RESET is high after this 32 cycle delay, the reset source is tentatively assumed to be either a COP failure or a clock monitor failure. If the internally latched state of the clock monitor fail circuit is true, processing begins by fetching the clock monitor vector ($FFFC:FFFD).
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Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions Freescale Semiconductor, Inc... MCU will recognize another interrupt as soon as the interrupt mask bit in the MCU is cleared (normally upon return from an interrupt). Mode Select (MODA, MODB, and MODC) The state of these pins during reset determine the MCU operating mode. After reset, MODA and MODB can be configured as instruction queue tracking signals IPIPE0 and IPIPE1 in expanded modes.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Pinout and Signal Description Read/Write (R/W) In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until enabled.
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Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions Table 7 MC9S12DP256 Signal Description Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pinout and Signal Description Table 7 MC9S12DP256 Signal Description Summary Freescale Semiconductor, Inc... Pin Function Pin Number Pin Name Powered by 112-pin Description KWH7 PH7 VDDR 32 KWH6 PH6 VDDR 33 KWH5 PH5 VDDR 34 KWH4 PH4 VDDR 35 XCLKS_NOACC PE7 VDDR 36 IPIPE1_MODB PE6 VDDR 37 IPIPE0_MODA PE5 VDDR 38 ECLK PE4 VDDR 39 E Clock is the output connection for the external bus clock.
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Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions Table 7 MC9S12DP256 Signal Description Summary Freescale Semiconductor, Inc... Pin Function Pin Number Pin Name Powered by 112-pin Description LSTRB_TAGLO PE3 VDDR 53 Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. The low strobe function is the exclusive-NOR of A0 and the internal SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.
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Freescale Semiconductor, Inc. Pinout and Signal Description Table 7 MC9S12DP256 Signal Description Summary Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pinout and Signal Description Signal Descriptions Table 7 MC9S12DP256 Signal Description Summary Pin Function Pin Number Pin Name Powered by 112-pin PP7 VDDX 109 KWP6_PWM6_SS2 PP6 VDDX 110 KWP5_PWM5_MOSI2 PP5 VDDX 111 KWP4_PWM4_MISO2 PP4 VDDX 112 Pulse Width Modulator Channel See also pins 1–4 Pins shared with SPI system 2 Freescale Semiconductor, Inc... KWP7_PWM7_SCK2 Description MC9S12DP256 — Revision 1.
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Freescale Semiconductor, Inc. Pinout and Signal Description Port Signals Freescale Semiconductor, Inc... The MC9S12DP256 incorporates eleven ports which are used to control and access the various device subsystems. When not used for these purposes, port pins may be used for general-purpose I/O.
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Freescale Semiconductor, Inc. Pinout and Signal Description Port Signals an output; clearing a bit in DDRB makes the corresponding bit in port B an input. The default reset state of DDRB is all zeroes. This register is not in the on-chip map in expanded and peripheral modes. Freescale Semiconductor, Inc... Port E Port E is associated with external bus control signals and interrupt inputs.
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Freescale Semiconductor, Inc. Pinout and Signal Description clearing a bit in DDRK makes the corresponding bit in port K an input. The default reset state of DDRK is all zeroes. Freescale Semiconductor, Inc... NOTE: The ports H, J, M, P, S, T can be configured in a very flexible way. For a full and detailed overview refer to Section Port Integration Module. Port M for MSCAN and BDLC There are four identical MSCAN ports and a BDLC module sharing the multiplex port M.
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Freescale Semiconductor, Inc. Pinout and Signal Description Port Signals Freescale Semiconductor, Inc... accumulator inputs. All eight pins are available for general-purpose I/O when not configured for timer functions. Port P for PWM The PWM module has a total of 8 external pins on which the pulse width modulated waveforms are output. The 8 PWM outputs are multiplexed on the PP[7:0] pins. This port is further shared with SPI 1 and 2 as well as with interrupt inputs.
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Freescale Semiconductor, Inc. Pinout and Signal Description Port Pull-Up Pull-Down and Reduced Drive MCU ports can be configured for internal pull-up. To reduce power consumption and RFI, the pin output drivers can be configured to operate at a reduced drive level. Reduced drive causes a slight increase in transition time depending on loading and should be used only for ports which have a light loading. Table 9 summarizes the port pull-up default status and controls. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. System Configuration System Configuration Freescale Semiconductor, Inc... Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Modules Variabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 MCU Variabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. System ConÞguration MCU Variabilities Part ID Register Assignments The PARTID register is located in the IPBI (IP-Bus interface) at address $__1A,$__1B. It contains a unique part ID for each revision of the chip. Table 11 contains the assigned part ID numbers. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Registers Registers Contents Freescale Semiconductor, Inc... Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Register Block The register block can be mapped to any 2K byte boundary within the first 32K byte of the standard 64K byte address space by manipulating bits REG[14:11] in the INITRG register. INITRG establishes the upper five bits of the register block’s 16-bit address. The register block occupies 1K byte.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Registers MC9S12DP256 — Revision 1.1 Registers For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Operating Modes Operating Modes Freescale Semiconductor, Inc... Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Operating Modes Freescale Semiconductor, Inc... Table 13 Mode Selection Input BKGD & bit MODC Input & bit MODB Input & bit MODA Mode Description 0 0 0 Special Single Chip, BDM allowed and ACTIVE. BDM is “allowed” in all other modes but a serial command is required to make BDM “active”.
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Freescale Semiconductor, Inc. Operating Modes Operating Modes PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset. The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis. Freescale Semiconductor, Inc... Normal Operating Modes These modes provide three operating configurations.
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Freescale Semiconductor, Inc. Operating Modes Normal Expanded Wide Mode — In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Freescale Semiconductor, Inc... Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pullup resistors enabled).
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Freescale Semiconductor, Inc. Operating Modes Operating Modes Normal Expanded Narrow Mode — This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. Freescale Semiconductor, Inc... Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data.
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Freescale Semiconductor, Inc. Operating Modes any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. Internal Visibility — Internal visibility is available when the MCU is operating in expanded wide modes or special narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is enabled by setting the IVIS bit in the MODE register. Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Operating Modes Operating Modes Emulation Expanded Narrow Mode — Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B.
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Freescale Semiconductor, Inc. Operating Modes Special Operating Modes There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. Freescale Semiconductor, Inc... Special Single-Chip Mode — When the MCU is reset in this mode, the background debug mode is enabled and “active”. The MCU does not fetch the reset vector and execute application code as it would in other modes.
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Freescale Semiconductor, Inc. Operating Modes Operating Modes Special Test Mode — In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset. Freescale Semiconductor, Inc... Test Operating Mode There is a test operating mode in which an external master, such as an I.C.
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Freescale Semiconductor, Inc. Operating Modes . Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Operating Modes EME — Emulate Port E Normal and Emulation: write never Freescale Semiconductor, Inc... Special: write anytime 1 = If in any expanded mode or special peripheral mode, PORTE and DDRE are removed from the memory map. Removing the registers from the map allows the user to emulate the function of these registers externally. 0 = PORTE and DDRE are in the memory map so Port E can be used for general purpose I/O.
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Freescale Semiconductor, Inc. Operating Modes Security user memory from $FF00 to $FFFF is not in the map except through serial BDM commands. Security Freescale Semiconductor, Inc... The device will make available a security feature preventing the unauthorized read and write of the memory contents.
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Freescale Semiconductor, Inc. Operating Modes The user can select any of the three combinations to secure the microcontroller. Freescale Semiconductor, Inc... Table 15 : Security Bits CAUTION: sec1 sec0 secreq 0 0 1 (secured) 0 1 1 (secured) 1 0 0 (unsecured) 1 1 1 (secured) Check the Flash Specification for more details on the security configuration. Operation of the Secured Microcontroller Normal Single Chip Mode This will be the most common usage of the secured part.
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Freescale Semiconductor, Inc. Operating Modes Security Freescale Semiconductor, Inc... the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. MC9S12DP256 — Revision 1.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Operating Modes MC9S12DP256 — Revision 1.1 Operating Modes For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Resource Mapping Resource Mapping Freescale Semiconductor, Inc... Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Internal Resource Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Flash EEPROM mapping through internal Memory Expansion . . . . 111 Miscellaneous System Control Register . . . . . . . . . . . . . . . . . . . . . . 118 Memory Maps . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Resource Mapping If conflicts occur when mapping resources, the register block will take precedence over the other resources; RAM or EEPROM addresses occupied by the register block will not be available for storage. When active, BDM ROM takes precedence over other resources, although a conflict between BDM ROM and register space is not possible. The following table shows resource mapping precedence. Only one module will be selected at a time.
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Freescale Semiconductor, Inc. Resource Mapping Internal Resource Mapping Register Block Mapping After reset the 1K byte register block resides at location $0000 but can be reassigned to any 2K byte boundary within the first 32K byte of the 64K byte address space. Mapping of internal registers is controlled by five bits in the INITRG register. This register initializes the internal Registers position. Normal and Emulation: Write once. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Resource Mapping Read: Anytime. Reset: $09 (RAM located from $1000 – $3FFF) INITRM — Initialization of Internal RAM Position Register Address Offset: $0010 Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 RAM15 RAM14 RAM13 RAM12 RAM11 0 0 RAMHAL 0 0 0 0 1 0 0 1 RAM[15:11] — Internal RAM map position This register initializes the internal RAM position. Only the upper two bits define the 16K page the RAM resides in.
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Freescale Semiconductor, Inc. Resource Mapping Flash EEPROM mapping through internal Memory Expansion INITEE— Initialization of Internal EEPROM Position Register Address Offset: $0012 Reset: Bit 7 6 5 4 3 2 1 Bit 0 EE15 EE14 EE13 EE12 0 0 0 EEON 0 0 0 0 0 0 0 1 Freescale Semiconductor, Inc... EE[15:12] — Internal EEPROM map position These bits specify the upper four bits of the 16-bit EEPROM address.
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Freescale Semiconductor, Inc. Resource Mapping Program space expansion There are 256K bytes of Flash EEPROM for MC9S12DP256. With a 64K byte address space, the PPAGE register is needed to perform on chip memory expansion. A program space window of 16K byte pages is located from $8000 to $BFFF. Six page indices are used to point to one of 64 different 16K byte pages. A total of 16 pages ($30 – $3F) are occupied by the 256K Flash block. The other pages are available for expanded addressing if enabled.
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Freescale Semiconductor, Inc. Resource Mapping Flash EEPROM mapping through internal Memory Expansion Page Index register descriptions PORTK — Port K Data Register Address Offset: $0032 Port: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 0 0 0 2 1 Bit 0 XAB16 XAB15 XAB14 Freescale Semiconductor, Inc... Reset: Alt. pin function Unaffected by reset ECS/ ROMONE 0 XAB19 XAB18 XAB17 Read and write anytime Writes do not change pin state when pin configured for page index emulation output.
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Freescale Semiconductor, Inc. Resource Mapping Freescale Semiconductor, Inc... Bit 5 – Bit 0 — Port K bits 5 – 0. These six bits are used to determine which array page is being accessed. They can be viewed as expanded addresses XAB19 – XAB15 and XAB14 of the 20-bit address used to access the 256K byte Flash EEPROM array. The decoding is done internally based upon the regular address bus bits 15 and 14 (AB[15:14]) and the state of the ROMHM bit in the MISC register.
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Freescale Semiconductor, Inc. Resource Mapping Flash EEPROM mapping through internal Memory Expansion DDRK — Port K Data Direction Register Address Offset: $0033 Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDK7 0 DDK5 DDK4 DDK3 DDK2 DDK1 DDK0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read and write: anytime. This register determines the primary direction for each port K pin configured as general-purpose I/O.
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Freescale Semiconductor, Inc. Resource Mapping PPAGE — (Program) Page Index Register Address Offset: $0030 Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 0 0 0 0 0 0 0 0 This register determines the active page viewed through the Program Page Window from $8000 – $BFFF. CALL and RTC instructions have a special single wire mechanism to read and write this register without using an address bus. There are 256K bytes of Flash EEPROM.
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Freescale Semiconductor, Inc. Resource Mapping Flash EEPROM mapping through internal Memory Expansion Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Resource Mapping Write never. Miscellaneous System Control Register Freescale Semiconductor, Inc... Additional mapping and external resource controls are available. To use external resources the part must be operated in one of the expanded modes.
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Freescale Semiconductor, Inc. Resource Mapping Memory Maps Table 20 EXSTR Stretch Bit Definition Stretch bit EXSTR1 Stretch bit EXSTR0 Number of E Clocks Stretched 0 0 0 0 1 1 1 0 2 1 1 3 Freescale Semiconductor, Inc... ROMHM — Flash EEPROM only in second half of memory map 1 = Disables direct access to the 16K byte Flash EEPROM in location $4000 – $7FFF in the memory map. The physical location of this 16K byte Flash can still be accessed through the Program Page window.
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Freescale Semiconductor, Inc. Resource Mapping $0000 $0000 $0400 REGISTERS (Mappable to any 2k Block within the first 32K) $03FF $0000 $1000 4K Bytes EEPROM (Mappable to any 4K Block) $0FFF Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Resource Mapping Memory Maps $0000 $0400 Freescale Semiconductor, Inc... $1000 $4000 $3E 16K Flash Unpaged One 16K Page accessible at a time (selected by PPAGE values $30 .. $3F) $8000 $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E $3F 16K Flash Paged $C000 $3F 16K Flash Unpaged $FF00 VECTORS $FFFF NORMAL SINGLE CHIP Figure 9 MC9S12DP256 Memory Paging MC9S12DP256 — Revision 1.1 Resource Mapping For More Information On This Product, Go to: www.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Resource Mapping MC9S12DP256 — Revision 1.1 Resource Mapping For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Bus Control and Input/Output Bus Control and Input/Output Freescale Semiconductor, Inc... Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . 123 Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 PIPE Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Bus Control and Input/Output Freescale Semiconductor, Inc... Table 21 Access Type vs.
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Freescale Semiconductor, Inc. Bus Control and Input/Output PIPE Status Signals PIPE Status Signals PIPE status signals IPIPE[1:0] provide information about data movement in the queue and indicate when the CPU begins to execute instructions. This makes it possible to monitor CPU activity on a cycle-by-cycle basis for debugging. Information available on the IPIPE[1:0] pins is time multiplexed. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Control and Input/Output • Start odd – This state indicates the current opcode is located in the top of the queue, low byte. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Control and Input/Output Registers Registers Not all registers are visible in the MC9S12DP256 memory map under certain conditions. Freescale Semiconductor, Inc... In special peripheral mode the first 16 registers associated with bus expansion are removed from the memory map. In expanded modes, some or all of port A, port B, and port E are used for expansion buses and control signals.
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Freescale Semiconductor, Inc. Bus Control and Input/Output PORTA — Port A Register Address Offset: $0000 Single Chip Bit 7 6 5 4 3 2 1 Bit 0 BIT 7 6 5 4 3 2 1 BIT 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Control and Input/Output Registers DDRA — Port A Data Direction Register Address Offset: $0002 Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 BIT 7 6 5 4 3 2 1 BIT 0 0 0 0 0 0 0 0 0 This register controls the data direction for Port A. When Port A is operating as a general purpose I/O port, DDRA determines the primary direction for each Port A pin.
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Freescale Semiconductor, Inc. Bus Control and Input/Output these pins can be used as general purpose I/O. Data Direction Register B (DDRB) determines the primary direction of each pin. DDRB also determines the source of data for a read of PORTB. This register is not in the on-chip map in expanded and peripheral modes. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Control and Input/Output Registers DDRB — Port B Data Direction Register Address Offset: $0003 Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 This register controls the data direction for Port B. When Port B is operating as a general purpose I/O port, DDRB determines the primary direction for each Port B pin.
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Freescale Semiconductor, Inc. Bus Control and Input/Output PORTE — Port E Register Address Offset: $0008 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 R/W IRQ XIRQ Reset: Freescale Semiconductor, Inc... Alt. Pin Function Unaffected by reset XCLKS or NOACC MODB or IPIPE1 or SCGTO MODA or IPIPE0 or RCRTO ECLK LSTRB or TAGLO Port E is associated with external bus control signals and interrupt inputs.
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Freescale Semiconductor, Inc. Bus Control and Input/Output Registers DDRE — Port E Data Direction Register Address Offset: $0009 Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 Bit 2 0 0 0 0 0 0 0 0 0 0 Data Direction Register E is associated with Port E. For bits in Port E that are configured as general purpose I/O lines, DDRE determines the primary direction of each of these pins.
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Freescale Semiconductor, Inc. Bus Control and Input/Output PEAR — Port E Assignment Register Address Offset: $000A Reset: Reset: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Control and Input/Output Registers NOACCE — CPU No Access Output Enable Normal: write once Emulation: write never Special: write anytime 1 = The associated pin (Port E bit 7) is output and indicates whether the cycle is a CPU free cycle. 0 = The associated pin (Port E bit 7) is general purpose I/O. Freescale Semiconductor, Inc... This bit has no effect in single chip or peripheral modes.
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Freescale Semiconductor, Inc. Bus Control and Input/Output LSTRE — Low Strobe (LSTRB) Enable Normal: write once Freescale Semiconductor, Inc... Emulation: write never Special: write anytime. 1 = The associated pin (Port E bit 3) is configured as the LSTRB bus control output. If BDM tagging is enabled, TAGLO is multiplexed in on the data cycle and LSTRB is driven out on the address cycle. 0 = The associated pin (Port E bit 3) is a general purpose I/O pin.
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Freescale Semiconductor, Inc. Bus Control and Input/Output Registers PUCR — Pull-Up Control Register Address Offset: $000C Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 PUPKE 0 0 PUPEE 0 0 PUPBE PUPAE 1 0 0 1 0 0 0 0 This register is used to select pullup resistors for the pins associated with the A, B, E, K ports. Pullups are assigned on a per-port basis and apply to any pin in the corresponding port that is currently configured as an input.
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Freescale Semiconductor, Inc. Bus Control and Input/Output RDRIV — Reduced Drive of I/O Lines Address Offset: $000D Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 RDPK 0 0 RDPE 0 0 RDPB RDPA 0 0 0 0 0 0 0 0 This register is used to select reduced drive for the pins associated with the A, B, E, K ports. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading).
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Freescale Semiconductor, Inc. Bus Control and Input/Output Registers EBICTL — External Bus Interface Control Address Offset: $000E Reset: Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 ESTR 0 0 0 0 0 0 0 0 Peripheral 0 0 0 0 0 0 0 1 All other modes The EBICTL register is used to control miscellaneous functions (i.e. stretching of external E clock). This register is not in the on-chip map in peripheral mode.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Bus Control and Input/Output MC9S12DP256 — Revision 1.1 Bus Control and Input/Output For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Resets and Interrupts Resets and Interrupts Freescale Semiconductor, Inc... Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Maskable interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Resets and Interrupts Maskable interrupts Maskable interrupts Freescale Semiconductor, Inc... Maskable interrupt sources include on-chip peripheral systems and external interrupt service requests. Interrupts from these sources are recognized when the global interrupt mask bit (I) in the CCR is cleared. The default state of the I bit out of reset is one, but it can be written at any time.
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Freescale Semiconductor, Inc. Resets and Interrupts Latching of Interrupts Freescale Semiconductor, Inc... XIRQ is always level triggered and IRQ can be selected as a level triggered interrupt. These level triggered interrupt pins should only be released during the appropriate interrupt service routine. Generally the interrupt service routine will handshake with the interrupting logic to release the pin.
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Freescale Semiconductor, Inc. Resets and Interrupts Latching of Interrupts Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Resets and Interrupts Register Descriptions Register Descriptions Interrupt Control and Priority Register INTCR — Interrupt Control Register Freescale Semiconductor, Inc... Address Offset: $001E Reset: Bit 7 6 5 4 3 2 1 Bit 0 IRQE IRQEN 0 0 0 0 0 0 0 1 0 0 0 0 0 0 IRQE — IRQ Select Edge Sensitive Only 1 = IRQ configured to respond only to falling edges.
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Freescale Semiconductor, Inc. Resets and Interrupts HPRIO — Highest Priority I Interrupt Address Offset: $001F Bit 7 6 5 4 3 2 1 Bit 0 PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 1 1 1 1 0 0 1 0 Freescale Semiconductor, Inc... Reset: Determines which I maskable interrupt will be promoted to highest priority (of the I maskable interrupts). To promote an interrupt the user writes the least significant byte of the associated interrupt vector address to this register.
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Freescale Semiconductor, Inc. Resets and Interrupts Register Descriptions ITCR — Interrupt Test Control Register Address Offset: $0015 Reset: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 WRTINT ADR3 ADR2 ADR1 ADR0 0 0 0 0 1 1 1 1 Freescale Semiconductor, Inc... WRTINT — Write to the Interrupt Test Registers Read anytime; Write only in special modes and with I-mask and X-mask set.
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Freescale Semiconductor, Inc. Resets and Interrupts ITEST — Interrupt Test Register Address Offset: $0016 Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 INTE INTC INTA INT8 INT6 INT4 INT2 INT0 0 0 0 0 0 0 0 0 Read: When ADR3–ADR0 have the value of $F, only bits 2–0 in the ITEST register will be accessible. That is, vectors higher than $FFF4 cannot be tested using the test registers and bits 7–3 will always read 0.
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Freescale Semiconductor, Inc. Resets and Interrupts Resets Resets Freescale Semiconductor, Inc... There are four possible sources of reset. Power-on reset (POR), and external reset on the RESET pin share the normal reset vector. The computer operating properly (COP) reset and the clock monitor reset each has a vector. Entry into reset is asynchronous and does not require a clock but the MCU cannot sequence out of reset without a system clock.
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Freescale Semiconductor, Inc. Resets and Interrupts V PORR VDD 4096 ECLKs RESET Internal POR 64 ECLKs 32 ECLKs Freescale Semiconductor, Inc... Internal RESET . Figure 12 RESET pin held low externally For the POR to be rearmed, VDD must fall to VPORA or below before the circuit asserts a power-on reset (see Figure 13). The RESET pin will be asserted low until VDD has risen to a level above VPORR. At this point the POR sequence will restart.
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Freescale Semiconductor, Inc. Resets and Interrupts Resets External Reset Freescale Semiconductor, Inc... NOTE: External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal processing.
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Freescale Semiconductor, Inc. Resets and Interrupts When COP is enabled, the program must write $55 and $AA (in this order) to the ARMCOP register during the selected time-out period. Once this is done, the internal COP counter resets to the start of a new time-out period. If the program fails to do this the part will reset. Also, if any value other than $55 or $AA is written, the part is immediately reset. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Resets and Interrupts Effects of Reset Effects of Reset Freescale Semiconductor, Inc... When a reset occurs, MCU registers and control bits are changed to known start-up states, as follows. Operating Mode and Memory Map Operating mode and default memory mapping are determined by the states of the BKGD, MODA, and MODB pins during reset. The MODA, MODB, and MODC bits in the MODE register reflect the status of the mode-select inputs at the rising edge of reset.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Resets and Interrupts Central Processing Unit After reset, the CPU fetches a vector from the appropriate address, then begins executing instructions. The stack pointer and other CPU registers are indeterminate immediately after reset. The CCR X and I interrupt mask bits are set to mask any interrupt requests. The S bit is also set to inhibit the STOP instruction.
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Freescale Semiconductor, Inc. Resets and Interrupts Register Stacking Register Stacking Freescale Semiconductor, Inc... Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared. When an interrupt service request is recognized, the CPU responds at the completion of the instruction being executed. Interrupt latency varies according to the number of cycles required to complete the instruction.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Resets and Interrupts MC9S12DP256 — Revision 1.1 Resets and Interrupts For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Voltage Regulator (VREG) Voltage Regulator (VREG) Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Voltage Regulator (VREG) Block Diagram VDDR Freescale Semiconductor, Inc... VDDA R VREF + – VDD1,2 R + VSSA por – VPOR = VSS1,2 + – VDDPLL Figure 14 VREG Block Diagram MC9S12DP256 — Revision 1.1 Voltage Regulator (VREG) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Voltage Regulator (VREG) Functional Description Freescale Semiconductor, Inc... Functional Description The voltage regulator module generates the supply voltage needed for the core logic as well as for the oscillator/pll section. The reference for the regulation loops are derived from a voltage divider connected between VDDA and VSSA. Both regulation loops, VDD and VDDPLL, consist of an operational amplifier driving an nmos power transistor in unit gain configuration.
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Freescale Semiconductor, Inc. Voltage Regulator (VREG) • Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. • VSSPLL must be directly connected to VSSR. • Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8 and Q1 as small as possible. • Central power input should be fed in at the VDDA/VSSA pins. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Voltage Regulator (VREG) External Pin Connection VREGEN C6 VDDX VSSX VSSA to supply C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR C4 C7 C8 C5 VDDR Q1 C10 C9 Freescale Semiconductor, Inc... to supply R1 VSSPLL VDDPLL Figure 15 Recommended PCB layout MC9S12DP256 — Revision 1.1 Voltage Regulator (VREG) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Voltage Regulator (VREG) Reset Initialization Freescale Semiconductor, Inc... On system power up, the voltage regulator is started in run mode if VREGEN is connected to VDDA. VDDA must be monitored by an external voltage comparator to ensure that the MCU is not executing code while the power supply is out of specification limits to avoid erroneous operation. Modes of Operation The voltage regulator has three operating modes: run, standby and disabled.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Flash EEPROM 256K Freescale Semiconductor, Inc... Contents Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Flash EEPROM 256K Banked Register A register operating on one flash block which shares the same register address as the equivalent registers for the other flash blocks. The active register bank is selected by two bank-select bits in the unbanked register space. Unbanked Register A register which operates on all flash blocks. Command Sequence Three-step MCU instructions sequence to program or erase the Flash.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Features It is possible to perform ‘Read-While-Write’, i.e. program or erase one flash block under control of software routines executing out of another flash block. Freescale Semiconductor, Inc... Each block has hardware interlocks which protect data from accidental corruption. One protected area is located at the upper address of the flash module ($xxxx –$FFFF) normally used for boot code and another area is located at the lowest address ($4000–$xxxx).
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Freescale Semiconductor, Inc. Flash EEPROM 256K Freescale Semiconductor, Inc... Block Diagram Flash Flash Flash Flash Block0 Block1 Block2 Block3 32K * 16bits 32K * 16bits 32K * 16bits 32K * 16bits Control Control Control Control Register Register Register Register Bank 0 Bank 1 Bank 2 Bank 3 Common Registers Module Bus Interface Star12 Bus Figure 16 Flash 256K Block Diagram MC9S12DP256 — Revision 1.1 Flash EEPROM 256K For More Information On This Product, Go to: www.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Module Memory Map Module Memory Map Freescale Semiconductor, Inc... Overview The memory data is accessible in the address range $4000–$FFFF. All 16 pages of 16K bytes are accessible in the address range $8000–$BFFF by using the PPAGE register. The flash module contains a bank of control and status registers in the same address space INITRG + $100 - INITRG + $10F for each of the blocks.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Flash EEPROM 256K Flash 0 Relative Address within Flash block $0000 $3C Flash 1 Relative Address within Flash Block $0000 $38 $4000 $4000 $3D $39 $8000 Flash Protect Low Area $3E 0.5K, 1K, 2K, 4K $8000 Flash Protect Low Area $3A 0.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Module Memory Map Flash Data Memory Map Since the address range of the flash module is larger than the 64K (16-bit) native address space of the STAR12 the modules will be mapped through an address window from $8000–$BFFF in 16K byte blocks. The additional address bits are located in the PPAGE register. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Flash EEPROM 256K Flash Protection Option Fields Flash block 0 also holds a field of 16-bytes containing Security, Protection as well as “backdoor” comparison bytes. The layout of this field is as follows: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Flash EEPROM 256K Module Memory Map Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Flash EEPROM 256K Functional Description Freescale Semiconductor, Inc... NOTE: Program and Erase Procedures All internal program and erase timings are handled by a state machine. The timebase is derived from the oscillator clock OSCCLK via a programmable down counter.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Functional Description Freescale Semiconductor, Inc... 2. Write to the (core) PPAGE register ($x030) to select one of the 16K page to be programmed if programming in the $8000–$BFFF address range. There is no need to set PPAGE when programming in the $4000–$7FFF or $C000–$FFFF address ranges. After this initialization step the CBEIF flag should be tested to ensure that the address, data and command buffers are empty.
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Freescale Semiconductor, Inc. Flash EEPROM 256K 1. Writing to the flash address space before initializing FCLKDIV. 2. Writing to the flash address space in the range $8000–$BFFF when PPAGE does not select a 16K block in the flash selected by BKSEL[1:0]. 3. Writing to the flash address space $4000–$7FFF or $C000–$FFFF with BKSEL[1:0] not selecting Flash 0. 4. Writing a misaligned word or a byte to the flash address space. Freescale Semiconductor, Inc... 5.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Register Descriptions Register Descriptions NOTE: All bits of all registers in this module are completely synchronous to internal clocks during a register read. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Flash EEPROM 256K FDIV[5:0] — Flash Clock Divider The combination of FDIV8 and FDIV[5:0] is used to divide the oscillator clock down to a frequency of 150KHz - 200KHz. This resulting clock, FCLK, is used to drive the program and erase state machines for the flash. For frequencies of OSCCLK > 12.8MHz the Prescaler bit FDIV8 must be turned on. Freescale Semiconductor, Inc... FCLKDIV must be chosen such that the following equation is valid.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Register Descriptions Freescale Semiconductor, Inc... Table 29 Example FCLKDIV settings Oscillator Frequency PRDIV8 FDIV[5:0] FCLK Frequency FCLK Period 1.0MHz 0 000100 200KHz 5us 2.0MHz 0 001001 200KHz 5us 4.0MHz 0 010011 200KHz 5us 8.0MHz 0 100111 200KHz 5us 16.
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Freescale Semiconductor, Inc. Flash EEPROM 256K When KEYEN is set, the user can then bypass the security by: 1. Setting the KEYACC bit in the configuration (FCNFG) register. 2. Writing the correct four 16bit words to the flash using the backdoor comparison keys addresses. 3. Clear the KEYACC bit. 4. If all four 16bit words match the flash content, the MCU is unsecured by forcing the bits SEC[1:0] to the unsecure state. Freescale Semiconductor, Inc... 5.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Register Descriptions FCNFG Ñ Flash Configuration Register Address Offset: $0003 Read: Write: Reset: Bit 7 6 5 CBEIE CCIE KEYACC 0 0 0 4 3 2 0 0 0 0 0 0 1 Bit 0 BKSEL1 BKSEL0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime Write: Anytime This register is unbanked. It enables the interrupts, gates the security backdoor writes and selects the register bank to be operated on.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Freescale Semiconductor, Inc... Table 31 Register Bank Selects BKSEL[1:0] Description 00 Flash 0 01 Flash 1 10 Flash 2 11 Flash 3 FPROT Ñ Flash Protection Register Address Offset: $0004 Bit 7 Read: FPOPEN 6 5 4 3 2 1 Bit 0 F FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 F F F F F F F Write: Reset: F = Reserved or unimplemented Read: Anytime Write: Only in special modes This register is banked.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Register Descriptions possible when protection is fully disabled by setting the FPLDIS and FPHDIS bits. In order to change the flash protection in special modes, the protection register can be written directly. Freescale Semiconductor, Inc... In order to change the protection in user mode the flash locations $FF0A, $FF0B, $FF0C and $FF0D have to be re-programmed and the MCU reset to reload the FPROT registers from those flash locations.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Flash EEPROM 256K Register Descriptions FPLS[1:0] — Flash Protection Lower Address size These 2 bits determine the size of the protected area. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Flash EEPROM 256K FSTAT Ñ Flash Status Register Address Offset: $0005 Bit 7 Read: Write: Reset: CBEIF 1 6 CCIF 1 5 4 PVIOL ACCERR 0 0 3 0 2 BLANK 0 0 1 Bit 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime Write: Anytime to clear flags This register is banked. The bits in this register are set by various conditions.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Register Descriptions ACCERR — Access error Indicates an illegal access to the flash block or violation of the defined command sequence. This can be: 1. Writing to the flash address space before initializing FCLKDIV. Freescale Semiconductor, Inc... 2. Writing to the flash address space in the range $8000–$BFFF when PPAGE does not select a 16K block in the flash selected by BKSEL[1:0]. 3.
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Freescale Semiconductor, Inc. Flash EEPROM 256K BLANK — Blank Verify Flag Indicates that the flash block is fully erased in response to an EraseVerify command. The flag is cleared by writing a “1”. Writing a “0” has no effect. 1 = Flash block fully erased. 0 = Flash block not fully erased. Freescale Semiconductor, Inc... BITS[1:0] — These bits are reserved for factory testing and are not available to the user.
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Freescale Semiconductor, Inc. Flash EEPROM 256K Register Descriptions PROG — Word programming Trying to program a word located in a protected area will result in a protection error indicated by PVIOL set. 1 = Program memory 0=- Freescale Semiconductor, Inc... ERVER — Enable Erase Verify Verifies the flash block is fully erased. A successful verification will set the BLANK bit in the FSTAT register. 1 = Perform an erase verify after mass erase.
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Freescale Semiconductor, Inc. Flash EEPROM 256K External Pin Descriptions This module does not have external pins relevant for the user. Freescale Semiconductor, Inc... Reset Initialization Out of reset the module holds core activity while the Protection and Security registers are loaded from Flash 0. Thereafter, the Flash module is immediately accessible, operating in read mode. If a reset occurs while any command is in progress that command will be immediately aborted.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Flash EEPROM 256K Interrupt Operation Wait Mode When the MCU enters WAIT mode and any command is active (CCIF = 0) the command will be completed. If enabled, the CCIF interrupt can be used to waken the MCU out of Wait mode. Stop Mode No low power options exist for this module in stop mode.
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Freescale Semiconductor, Inc. Flash EEPROM 256K block0 CBEIF Block0 select block1 CBEIF Block1 select CBEIE Flash Interrupt Request Freescale Semiconductor, Inc... block0 CCIF Block0 select block1 CCIF Block1 select CCIE Figure 20 256K (4 Blocks) Flash Interrupt Implementation. CAUTION: Recovery from STOP or WAIT When programming or erasing Flash Block 0 the interrupt vectors are not readable. It is therefor not recommended to program or erase the Flash Block 0 with interrupts enabled.
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Freescale Semiconductor, Inc. EEPROM 4K EEPROM 4K Freescale Semiconductor, Inc... Contents Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. EEPROM 4K Overview Freescale Semiconductor, Inc... The 4k byte EEPROM module serves as electrically erasable and programmable, non-volatile data memory without requiring external programming voltage sources. The EEPROM may be read as either bytes, aligned words or misaligned words. Access time is one bus cycle for byte and aligned word and two bus cycles for misaligned word read. Write operations for program or erase are only allowed as aligned word accesses.
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Freescale Semiconductor, Inc. EEPROM 4K Block Diagram Freescale Semiconductor, Inc... Block Diagram EEPROM Block Control 2k * 16-Bits Registers Module Bus Interface Star12 Bus Figure 21 EEPROM 4K Block Diagram Module Memory Map Overview The memory data is accessible in the address range $x000 - $xFFF and can be re-mapped to any 4k boundary in the MCU address range. After reset the MCU register block will be mapped on top of the EEPROM in the address range $0000 - $03FF.
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Freescale Semiconductor, Inc. EEPROM 4K Data Memory Map Freescale Semiconductor, Inc... $x000 EEPROM Control Register Base +$110– $11B EEPROM Protected Area 64, 128, 192, 256, 320, 384, 448, 512 bytes $xFFF 16bytes: Protection byte and reserved bytes Figure 22 EEPROM Data Memory Map EEPROM Protection Option Fields The EEPROM block reserves one byte, $xFFD as a protection byte which is loaded to the EPROT register on reset. MC9S12DP256 — Revision 1.
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Freescale Semiconductor, Inc. EEPROM 4K Module Memory Map Register Memory Map . Register name ECLKDIV Freescale Semiconductor, Inc... Unused Bit 7 4 3 2 1 Bit 0 Addr.
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Freescale Semiconductor, Inc. EEPROM 4K NOTE: Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. Freescale Semiconductor, Inc... Functional Description All internal program and erase timings are handled by a state machine. The timebase is derived from the oscillator clock OSCCLK via a programmable down counter.
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Freescale Semiconductor, Inc. EEPROM 4K Functional Description 1. Write an aligned data word (16-bits) to be programmed to the EEPROM address space between $x000 and $xFFF. The address and data will be stored in internal buffers. For program, all address bits are valid. For erase, the value of the data bytes is don’t care. For mass erase the address can be anywhere in the available address space of the 4k byte block to be erased. For sector erase the address bits 1:0 are don’t cared.
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Freescale Semiconductor, Inc. EEPROM 4K 6. Writing a second command to the ECMD register before executing the previously written command. 7. Writing a MASS erase command to ECMD while any protection is enabled. See EPROT register description. 8. Writing a SECTOR erase command to ECMD while protection is enabled for that sector. See EPROT register description. Freescale Semiconductor, Inc... 9. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the command register. 10.
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Freescale Semiconductor, Inc. EEPROM 4K Register Descriptions Register Descriptions NOTE: All bits of all registers in this module are completely synchronous to internal clocks during a register read. Freescale Semiconductor, Inc... ECLKDIV Ñ EEPROM Clock Divider Register.
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Freescale Semiconductor, Inc. EEPROM 4K machines for the EEPROM. For frequencies of OSCCLK > 12.8MHz the Prescaler bit FDIV8 must be turned on. ECLKDIV must be chosen such that the following equation is valid. If FDIV8 == 1 then CLK = OSCCLK / 8, else CLK = OSCCLK ECLKDIV = INT (CLK[KHz] / 200KHz) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. EEPROM 4K Register Descriptions ECNFG Ñ EEPROM Configuration Register Address Offset: $0003 Read: Write: Reset: Bit 7 6 CBEIE CCIE 0 0 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime Write: Anytime This register enables the interrupts CBEIE — Command Buffers Empty Interrupt Enable This bit enables the interrupts in case of an empty address, data and command buffers.
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Freescale Semiconductor, Inc. EEPROM 4K EPROT Ñ EEPROM Protection Register Address Offset: $0004 Bit 7 Read: EPOPEN 6 5 4 3 2 1 Bit 0 F F F EPDIS EP2 EP1 EP0 F F F F F F F Write: Reset: F Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime Write: Only in special modes This register is banked. The EEPROM protection registers are loaded during the reset sequence from address $_FFD as indicated by the “F” in the reset row of the register diagram.
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Freescale Semiconductor, Inc. EEPROM 4K Register Descriptions EPDIS — EEPROM Protection disable This bit determines whether there is a protected area at the higher end of the EEPROM block address map. 1 = Protection disabled 0 = Protection enabled Freescale Semiconductor, Inc... EP[2:0] — EEPROM Protection address size These 3 bits determine the size of the protected area.
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Freescale Semiconductor, Inc. EEPROM 4K ESTAT Ñ EEPROM Status Register Address Offset: $0005 Bit 7 Read: Write: Reset: CBEIF 1 6 CCIF 1 5 4 PVIOL ACCERR 0 0 3 0 2 BLANK 0 0 1 Bit 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime Write: Anytime to clear flags The bits in this register are set by various conditions.
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Freescale Semiconductor, Inc. EEPROM 4K Register Descriptions ACCERR — Access error Indicates an illegal access to the EEPROM block or violation of the defined command sequence. This can be: 1. Writing to the EEPROM address space before initializing ECLKDIV. 2. Writing a misaligned word or a byte to the EEPROM address space. Freescale Semiconductor, Inc... 3. Writing to the EEPROM address space while CBEIF is not set. 4.
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Freescale Semiconductor, Inc. EEPROM 4K ECMD Ñ EEPROM Command Buffer and Register Address Offset: $0006 Bit 7 Read: 5 0 Write: Reset: 6 0 ERASE PROG 0 0 4 3 0 0 2 1 0 ERVER 0 0 Bit 0 0 MASS 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime Write: After aligned write to the EEPROM address space in the command sequence. (See PVIOL description in ESTAT register) This register is buffered.
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Freescale Semiconductor, Inc. EEPROM 4K Register Descriptions MASS — Enables Mass Erase Perform a mass erase of the selected 4k byte block. This bit works in conjunction with the ERASE bit. If any protection is active on the selected block, mass erase has no effect and PVIOL is set. 1 = Perform a mass erase of the whole block 0 = Perform sector erase Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. EEPROM 4K External Pin Descriptions This module does not have external pins relevant for the user. Freescale Semiconductor, Inc... Reset Initialization Out of reset the module is immediately accessible operating in read mode. If a reset occurs while any command is in progress that command will be immediately aborted. The state of the word being programmed or the sector / block being erased is not guaranteed.
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Freescale Semiconductor, Inc. EEPROM 4K Interrupt Operation Interrupt Operation This module can generate an interrupt when all commands are completed or the command buffer is empty. Interrupt Sources Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... EEPROM 4K MC9S12DP256 — Revision 1.1 EEPROM 4K For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Port Integration Module Port Integration Module Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Port Integration Module associated with the fifth CAN module and the IIC interface1. Ports P, H and J can also be used as external interrupt sources. Each I/O pin can be configured by several registers: Input/output selection, drive strength reduction, enable and select of pull resistors, interrupt enable and status flags. Freescale Semiconductor, Inc... The port integration module is device dependant which is reflected in its naming.
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Port Integration Module External Pin Descriptions All ports start up as general purpose inputs on reset. Freescale Semiconductor, Inc... 80 Pin QFP bond-out version In case the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs with enabled pull resistance to avoid excess current consumption. This applies to the following pins: • All port K and H. • Port PP6, PJ1–0, PM7–4. • PAD15–8.
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Freescale Semiconductor, Inc. Port Integration Module Register Map Register Map Freescale Semiconductor, Inc... Register name Bit 7 6 5 4 3 2 1 Bit 0 Addr.
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Freescale Semiconductor, Inc. Port Integration Module Register name PPSS WOMS Freescale Semiconductor, Inc... Unimplemented Bit 7 Read: PPSS7 Write: 6 5 4 3 2 1 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 Bit 0 Addr.
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Freescale Semiconductor, Inc. Port Integration Module Register Map Freescale Semiconductor, Inc... Register name Bit 7 6 5 4 3 2 1 Bit 0 Addr.
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Freescale Semiconductor, Inc. Port Integration Module Freescale Semiconductor, Inc... Register name Bit 7 PTJ Read: PTJ7 Write: PTIJ Read: PTIJ7 Write: 6 PTJ6 PTIJ6 DDRJ Read: DDRJ7 Write: DDRJ6 RDRJ Read: RDRJ7 Write: RDRJ6 PERJ Read: PERJ7 Write: PERJ6 PPSJ Read: PPSJ7 Write: PPSJ6 PIEJ Read: PIEJ7 Write: PIEJ6 PIFJ Read: PIFJ7 Write: PIFJ6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit 0 Addr.
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Freescale Semiconductor, Inc. Port Integration Module Register Map Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions The following table summarizes the effect on the various configuration bits, data direction (DDR), output level (I/O), reduced drive (RDR), pull enable (PE), polarity select (PS) and interrupt enable (IE) for the ports. The configuration bit PS is used for two purposes: Freescale Semiconductor, Inc... 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port T I/O Register (PTT) Address Offset: $0000 Read: Write: ECT: Bit 7 6 5 4 3 2 1 Bit 0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 I/OC7 I/OC6 I/OC5 I/OC4 I/OC3 I/OC2 I/OC1 I/OC0 0 0 0 0 0 0 0 0 Reset: Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime.
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Freescale Semiconductor, Inc. Port Integration Module Port T Data Direction Register (DDRT) Address Offset: $0002 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures each port T pin as either input or output.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port T Reduced Drive Register (RDRT) Address Offset: $0003 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored.
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Freescale Semiconductor, Inc. Port Integration Module Port T Polarity Select Register (PPST) Address Offset: $0005 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Freescale Semiconductor, Inc... The SPI pins (PS[7:4]) configuration is determined by several status bits in the SPI module. See Serial Peripheral Interface (SPI) section for details. The SCI ports associated with transmit pins 3 and 1 are configured as outputs if the transmitter is enabled. The SCI pins associated with receive pins 2 and 0 are configured as inputs if the receiver is enabled.
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Freescale Semiconductor, Inc. Port Integration Module Freescale Semiconductor, Inc... This register configures each port S pin as either input or output. If SPI is enabled, the SPI determines the pin direction. For details see Serial Peripheral Interface (SPI) section. If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port S Pull Device Enable Register (PERS) Address Offset: $000C Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 1 1 1 1 1 1 1 1 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime.
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Freescale Semiconductor, Inc. Port Integration Module Freescale Semiconductor, Inc... PPSS[7:0] — Pull Select Port S 1 = A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input. 0 = A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input or as wired-or output.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port M I/O Register (PTM) Address Offset: $0010 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 RxCAN3 TxCAN2 RxCAN2 TxCAN1 RxCAN1 TxCAN0 RxCAN0 TxBDLC RxBDLC 0 0 CAN: TxCAN3 J1850: Freescale Semiconductor, Inc... Reset: 0 0 0 0 0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime.
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Freescale Semiconductor, Inc. Port Integration Module This register always reads back the status of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. Port M Data Direction Register (DDRM) Freescale Semiconductor, Inc... Address Offset: $0012 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 0 0 0 0 0 0 0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port M Reduced Drive Register (RDRM) Address Offset: $0013 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures the drive strength of each port M output pin as either full or reduced. If the port is used as input this bit is ignored.
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Freescale Semiconductor, Inc. Port Integration Module PERM[7:0] — Pull Device Enable Port M 1 = Either a pull-up or pull-down device is enabled. 0 = Pull-up or pull-down device is disabled. Port M Polarity Select Register (PPSM) Freescale Semiconductor, Inc... Address Offset: $0015 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 0 0 0 0 = Reserved or unimplemented Read: Anytime. Write: Anytime.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port M Wired-Or Mode Register (WOMM) Address Offset: $0016 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain).
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Port Integration Module read. The PWM function takes precedence over the general purpose I/O function if the associated PWM channel is enabled. While channels 6–0 are output only if the respective channel is enabled, channel 7 can be PWM output or input if the shutdown feature is enabled. See Chapter PWM. The SPI function takes precedence over the general purpose I/O function associated with if enabled. See Chapter SPI.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port P Data Direction Register (DDRP) Address Offset: $001A Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output.
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Freescale Semiconductor, Inc. Port Integration Module Port P Reduced Drive Register (RDRP) Address Offset: $001B Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures the drive strength of each port P output pin as either full or reduced. If the port is used as input this bit is ignored.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port P Polarity Select Register (PPSP) Address Offset: $001D Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime.
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Freescale Semiconductor, Inc. Port Integration Module Port P Interrupt Enable Register (PIEP) Address Offset: $001E Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port P.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions PIFP[7:0] — Interrupt Flags Port P 1 = Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a ‘1’ clears the associated flag. 0 = No active edge pending. Writing a ‘0’ has no effect. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Port Integration Module Port H Data Direction Register (DDRH) Address Offset: $0022 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures each port H pin as either input or output. DDRH[7:0] — Data Direction Port H 1 = Associated pin is configured as output.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port H Pull Device Enable Register (PERH) Address Offset: $0024 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Port Integration Module PPSH[7:0] — Polarity Select Port H 1 = Rising edge on the associated port H pin sets the associated flag bit in the PIFH register. A pull-down device is connected to the associated port H pin, if enabled by the associated bit in register PERH and if the port is used as input. 0 = Falling edge on the associated port H pin sets the associated flag bit in the PIFH register.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port H Interrupt Flag Register (PIFH) Address Offset: $0027 Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 0 0 0 0 0 0 0 0 Reset: Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSH register.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Port Integration Module If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. The CAN function (TxCAN and RxCAN) takes precedence over the general purpose I/O function if the associated CAN module is enabled. See Chapter CAN. The IIC function takes precedence over the general purpose I/O function associated with if enabled.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port J Data Direction Register (DDRJ) Address Offset: $002A Read: Write: Reset: Bit 7 6 DDRJ7 DDRJ6 0 0 5 4 3 2 0 0 0 0 –f –f –f –f 1 Bit 0 DDRJ1 DDRJ0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures each port J pin as either input or output.
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Freescale Semiconductor, Inc. Port Integration Module Port J Reduced Drive Register (RDRJ) Address Offset: $002B Read: Write: Reset: Bit 7 6 RDRJ7 RDRJ6 0 0 5 4 3 2 0 0 0 0 0 0 0 0 1 Bit 0 RDRJ1 RDRJ0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored.
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Freescale Semiconductor, Inc. Port Integration Module Register Descriptions Port J Polarity Select Register (PPSJ) Address Offset: $002D Read: Write: Reset: Bit 7 6 PPSJ7 PPSJ6 0 0 5 4 3 2 0 0 0 0 0 0 0 0 1 Bit 0 PPSJ1 PPSJ0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled.
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Freescale Semiconductor, Inc. Port Integration Module Port J Interrupt Enable Register (PIEJ) Address Offset: $002E Read: Write: Reset: Bit 7 6 PIEJ7 PIEJ6 0 0 5 4 3 2 0 0 0 0 0 0 0 0 1 Bit 0 PIEJ1 PIEJ0 0 0 Freescale Semiconductor, Inc... = Reserved or unimplemented Read: Anytime. Write: Anytime. This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port J. PIEJ[7:6][1:0] — Interrupt Enable Port J 1 = Interrupt is enabled.
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Freescale Semiconductor, Inc. Port Integration Module Reset Initialization PIFH[7:6][1:0] — Interrupt Flags Port J 1 = Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a ‘1’ clears the associated flag. 0 = No active edge pending. Writing a ‘0’ has no effect. Freescale Semiconductor, Inc... Reset Initialization All registers including the data registers get set/reset asynchronously.
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Freescale Semiconductor, Inc. Port Integration Module Data direction register This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored. PTI 0 Freescale Semiconductor, Inc... PT 1 0 I/O PAD 1 0 DDR 1 MOD do obe mod_en Figure 26 Illustration of I/O pin functionality Reduced drive register If the port is used as an output the register allows the configuration of the drive strength.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Port Integration Module Functional Description Port S This port is associated with the serial SCI and SPI modules. In all modes, port S pins PS[7:0] can be used either for general-purpose I/O, or with the SCI and SPI subsystems. During reset, port S pins are configured as inputs with pull-up. Port M This port is associated with the J1850 and 4 CAN modules.
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Freescale Semiconductor, Inc. Port Integration Module consecutive samples have to be either low or high in order to detect a valid low or high input. Freescale Semiconductor, Inc... The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock is generated by a single RC oscillator in the Port Integration Module.
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Freescale Semiconductor, Inc. Port Integration Module Low Power Options tpulse Freescale Semiconductor, Inc... Figure 28 Pulse Illustration Port H Port H offers 8 I/O ports with the same interrupt features as port P. Port J This port is associated with the fifth CAN and the IIC module. In all modes, port J pins PJ[7:6] and PJ[1:0] can be used for either general purpose I/O, or with the CAN and IIC subsystems. Pins PJ6 and PJ7 are shared between the CAN4 and the IIC module.
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Freescale Semiconductor, Inc. Port Integration Module Interrupt Operation Port P, H and J generate a separate edge sensitive interrupt if enabled. Interrupt Sources Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Clocks and Reset Generator (CRG) Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Register Map. . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Features The main features of this block are: • Crystal (or ceramic resonator) oscillator (OSC) – Crystal Monitor (CM) – Startup counter Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Block Diagram Block Diagram The block diagram below shows a high level view of the CRG and OSC modules. CRG IP Bus Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Map The register map for the CRG appears below. Reg Name SYNR Read: Bit 7 6 5 4 3 2 1 Bit 0 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0 RTIF PORF LOCK TRACK 0 0 PLLWAI CWAI RTIWAI 0 0 0 RTR2 RTR1 RTR0 CR2 CR1 CR0 Write: REFDV Read: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description Freescale Semiconductor, Inc... Table 45 CRG Register Address Summary NOTE: Register SYN REFDV CTFLG CRGFLG CRGINT CLKSEL Base Address $0000 $0001 $0002 $0003 $0004 $0005 Register PLLCTL RTICTL COPCTL FORBYP CTCTL ARMCOP Base Address $0006 $0007 $0008 $0009 $000A $000B Register Address = Module Address + Base Address + Address Offset The Module Address is determined at the MCU level.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Freescale Semiconductor, Inc... The crystal oscillator is equipped with a feedback system which does not waste current generating harmonics. Its configuration is “Colpitts oscillator with translated ground”. The transconductor used is driven by a current source under the control of a peak detector which will measure the amplitude of the AC signal appearing on EXTAL node in order to implement an Amplitude Limitation Control (ALC) loop.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description Phase Locked Loop (PLL) REFERENCE EXTAL REFDV <3:0> REDUCED OSCCLK CONSUMPTION REFERENCE OSCILLATOR PROGRAMMABLE DIVIDER Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency. NOTE: Freescale Semiconductor, Inc... PLL operation Although it is possible to synthesize a PLLCLK frequency less than OSCCLK, some systems using a constant OSCCLK frequency base may not be able to operate.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Freescale Semiconductor, Inc... The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below the maximum system frequency, fsys, and require fast start-up. The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Clocks and Reset Generator (CRG) Functional Description high. After the Startup Counter reaches the end of the count, 8192 self clock mode cycles, reset is released. At this time, if the crystal monitor indicates the presence of an external clock, self-clock mode is de-asserted and the MCU exits reset normally, using OSCCLK clock.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) VDD Power-On Detector OSCCLK (Slow crystal) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description Freescale Semiconductor, Inc... counts 8192 crystal clock cycles and at the end of the start up count the MCU completes its internal reset sequence. If the SCME and CME bits are set, and a loss of crystal clock is detected by the crystal monitor circuit, the PLL VCO clock at its minimum frequency is provided as the system clock (self clock mode), allowing the MCU to continue operating.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) OSCCLK Crystal Monitor Fail 0 --> 8192 0 --> 8192 Startup counter (Clocked by SYSCLK) Freescale Semiconductor, Inc... self-clock PLLSEL Restore PLLSEL SYSCLK PLLSEL = 0 OSCCLK SYSCLK PLLSEL = 1 PLLCLK static PLLCLK (self-clock) Restore OSCCLK PLLCLK (self-clock) Restore PLLCLK Figure 32 Crystal Clock Loss during Normal Operation STOP mode If CME bit is cleared, the MCU goes into STOP mode when a STOP instruction is executed.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Clocks and Reset Generator (CRG) Functional Description Startup Counter. When the presence of an external clock is detected, the SCM flag is cleared. This sets the self-clock interrupt flag and if enabled by the SCMIE bit, the self-clock mode interrupt is requested. Upon leaving self-clock mode, PLLSEL is restored to its value before the loss of crystal clock, and the system clock returns to its previous frequency.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Table 46 Outcome of oscillation absence conditions Condition Freescale Semiconductor, Inc... POR Startup counter clock Outcome Self clock Part resets. Startup counter starts in self clock mode. Part switches to OSCCLK when crystal monitor indicates no failure and at the end of the startup counter.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description CME=1 & SCME=0 ? Power on detected CPU executes STOP instruction Clock failure YES MCU resets CME=1 & SCME=0 ? YES MCU resets NO NO Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) System Clocks Generator CRG PLLSEL Freescale Semiconductor, Inc... PHASE LOCK LOOP PLLCLK 1 SYSCLK CLK24 0 ÷2 OSCCLK CLOCK PHASE GENERATOR CLK3 CLK23 EXTAL OSCILLATOR OSCCLK XTAL RTI COP CRYSTAL MONITOR OSCCLK Figure 35 Clock Generator The clock generator creates the system clocks used in the MCU. The peripheral and memory modules use CLK3. The CLK23 signal is used to generate the clock visible at the ECLK pin.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description CORE CLOCK clk24 PERIPHERALS CLK3 CLOCK Freescale Semiconductor, Inc... ECLK clk23 Figure 36 System clocks phase relationship External clock mode The oscillator can be completely bypassed and turned off by selecting an external clock source instead. The crystal monitor, PLL, RTI, COP and OSCCLK are driven by this external clock instead of the output of the oscillator.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Clocks and Reset Generator (CRG) static period). In the case of POR, the reset recovery sequence starts in self clock mode. The internal reset recovery sequence then drives RESET low for 128 SYSCLK cycles and releases the drive to allow RESET to rise. 64 SYSCLK cycles later this circuit samples the RESET pin to see if it has risen to a logic one level.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Functional Description CR[2:0] 0:0:0 Freescale Semiconductor, Inc... OSCCLK CR[2:0] 0:0:1 ÷ 16384 ÷4 0:1:0 ÷4 0:1:1 ÷4 1:0:0 ÷4 1:0:1 ÷2 1:1:0 ÷2 1:1:1 COP TIMEOUT Figure 37 Clock Chain for COP Power-On detect sequence Figure 38 and Figure 39 show the power-up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) 8192 SYSCLK RESET Internal POR 128 SYSCLK Freescale Semiconductor, Inc... Internal RESET 64 SYSCLK Figure 39 RESET pin held low externally Real Time Interrupt (RTI) NOTE: The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI timer runs with OSCCLK. See Figure 40.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions OSCCLK ÷ 1024 RTR[6:4] 0:0:0 Freescale Semiconductor, Inc... 0:0:1 ÷2 0:1:0 ÷2 0:1:1 ÷2 1:0:0 ÷2 1:0:1 ÷2 1:1:0 ÷2 1:1:1 4-BIT MODULUS COUNTER (RTR[3:0]) RTI TIMEOUT Figure 40 Clock Chain for RTI Register Descriptions NOTE: CRG Synthesizer Register (SYNR) All bits of all registers in this module are completely synchronous to internal clocks during a register read.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) . Address Offset: $0000 Read: Bit 7 6 0 0 0 0 Write: Reset: 5 4 3 2 1 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Unimplemented or reserved Read: anytime. Write: anytime except if PLLSEL = 1. Write to this register initializes the lock detector. CRG Reference Divider Register (REFDV) The REFDV register provides a finer granularity for the PLL multiplier steps.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions CRG Test Flags Register (CTFLG) The CTFLG register is reserved for test mode only.: Address Offset: $0002 Read: Write: Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 0 TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0 0 0 0 0 0 0 0 0 1 0 Read: always read $00 except in test modes. Write: only in test modes.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) 1 = Set when a power on reset has occurred LOCKIF — PLL Lock Interrupt Flag This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 = No change in LOCK bit 1 = LOCK condition has changed, either from a locked state to an unlocked state or vice versa. Freescale Semiconductor, Inc... LOCK — Lock Status Write never. This bit is cleared in Self-Clocked Mode as the lock detector can not operate without the reference frequency.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions CRG Interrupt Enable Register (CRGINT) Address Offset: $0004 Bit 7 Read: Write: Freescale Semiconductor, Inc... Reset: RTIE 0 6 5 0 0 0 0 4 LOCKIE 0 3 2 0 0 0 0 1 SCMIE 0 0 0 0 Read and write anytime. RTIE — Real Time Interrupt Enable 0 = Interrupt requests from RTI are disabled. 1 = Interrupt will be requested whenever RTIF is set.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) PLLSEL — PLL selected for system clock Write anytime except when LOCK is cleared and AUTO is set, or TRACK is cleared and AUTO is cleared. In self-clock mode, the output of the PLLSEL bit is forced to 1, but the PLLSEL bit reads the latched value. 0 = SYSCLK is derived from OSCCLK. 1 = SYSCLK is derived from PLLCLK. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions PLLWAI — PLL stops in WAIT mode User mode: Write once Test mode: Write anytime Freescale Semiconductor, Inc... If PLLWAI is set, PLLON and PLLSEL bits remain set during wait mode but the PLL is powered down. Upon exiting wait mode, an automatic recovery delay is imposed until LOCK is detected. AUTO bit is forced to 1 if PLLWAI is set. 0 = Allows the PLL to keep running in wait mode.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) CRG PLL Control Register (PLLCTL) A description of the PLLCTL register follows: Address Offset: $0006 Read: Write: Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 CME PLLON AUTO ACQ 1 1 1 1 3 2 1 0 0 0 0 0 0 0 SCME 1 Read anytime. Refer to each bit for write conditions. CME — Crystal Monitor Enable Write anytime. 0 = Crystal monitor is disabled. 1 = Crystal monitor is enabled.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions ACQ — Acquisition Write anytime. If AUTO =1 this bit has no effect. 0 = Low bandwidth software selected 1 = High bandwidth software selected SCME — Self-clock mode enable Freescale Semiconductor, Inc... User mode: Write once Test mode: Write anytime 0 = Detection of crystal clock failure causes crystal monitor reset 1 = Detection of crystal clock failure forces the MCU in self-clock mode.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Table 47 RTI Frequency Divide Rates Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions CRG COP Control Register (COPCTL) A description of the COPCTL register follows:. Address Offset: $0008 Bit 7 Read: Write: Freescale Semiconductor, Inc... Reset: WCOP 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 CR2 CR1 CR0 0 0 0 Read anytime. Write once in user mode, anytime in test mode. A write to this register will initialize the COP counter.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Table 48 COP Watchdog Rates(1) Freescale Semiconductor, Inc... Window COP enabled: CR2 CR1 CR0 Divide OSCCLK by 0 0 0 0 0 Window start (OSCCLK Periods) Window end OSCCLK Periods) OFF OFF OFF 1 2 14 12297 16387 16 49161 65539 0 1 0 2 0 1 1 2 18 196,617 262,147 20 786,441 1,048,579 1 0 0 2 1 0 1 2 22 3,145,737 4,194,307 23 6,291,465 8,388,611 12,582,921 16,777,219 1 1 0 2 1 1 1 2 24 1.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Register Descriptions CRG Test Control Register (CTCTL) The CTCTL register is reserved for test mode only.: Address Offset: $000A Read: Write: Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 0 TCTL7 TCTL6 TCTL5 TCTL4 TCTL3 TCTL2 TCTL1 TCTL0 0 0 0 0 0 0 0 0 Read: always read $00 except in test modes. Write: only in test modes.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Freescale Semiconductor, Inc... External Pin Descriptions VDDPLL, VSSPLL These pins provide operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. XFC A passive external loop filter must be placed on the control line (XFC pad). The filter is a second-order, low-pass filter to eliminate the VCO input ripple.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) External Pin Descriptions EXTAL C MCU Crystal or ceramic resonator XTAL C Freescale Semiconductor, Inc... VSSPLL Figure 42 Common Crystal Connections EXTAL CMOS-COMPATIBLE EXTERNAL OSCILLATOR MCU XTAL NC Figure 43 External Oscillator Connections Reset (RESET) RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Reset Initialization When a reset occurs, CRG registers and control bits are changed to known start-up states, as outlined in Register Descriptions. Freescale Semiconductor, Inc... Interrupt Operation Real Time Interrupt The CRG generates a real time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to zero.
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Interrupt Operation Interrupt Vectors The interrupts/reset vectors requested by the CRG are listed below. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clocks and Reset Generator (CRG) Low Power Options Freescale Semiconductor, Inc... This section summarizes the low power options available in the CRG sub-block. Low power design practices are implemented where possible. Run Mode The RTI can be stopped by setting the associated rate select bits to zero. The COP can be stopped by setting the associated rate select bits to zero in special mode.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Pulse Width Modulator (PWM) Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs. Freescale Semiconductor, Inc... Features • Eight independent PWM channels with programmable period and duty cycle. • Dedicated counter for each PWM channel. • Programmable PWM enable/disable for each channel. • Software selection of PWM duty pulse polarity for each channel. • Period and duty cycle are double buffered.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Block Diagram Freescale Semiconductor, Inc... CON67 CON45 CON23 CON01 CAEx PPOLx PWMEx PCLKx PWMEx PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 PFRZ Block Diagram E Clk PWMx PWMx PWM TIMER CHANNELS PWM CLOCK SELECT Clocks Bus Clock freeze_mode BUS INTERFACE Data and Address BUS Figure 44 Pulse Width Modulation Block Diagram External Pin Descriptions The PWM module has no external pins. MC9S12DP256 — Revision 1.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Map Freescale Semiconductor, Inc... This section describes the content of the registers in the PWM. The base address of the PWM module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. The figure below shows the registers associated with the PWM and their relative offset from the base address.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Map Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions PWM Enable Register (PWME) Address Offset: $0000 Read: Write: Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 0 0 0 0 0 0 0 0 Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx=1), the associated PWM output is enabled immediately.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Freescale Semiconductor, Inc... PWME5 — Pulse Width Channel 5 Enable 1 = Pulse Width channel 5 is enabled. The pulse modulated signal becomes available at PWM, o/p bit 5 when its clock source begins its next cycle. 0 = Pulse Width channel 5 is disabled. PWME4 — Pulse Width Channel 4 Enable 1 = Pulse Width channel 4 is enabled. The pulse modulated signal becomes available at PWM, o/p bit 4 when its clock source begins its next cycle.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions PWM Polarity Register (PWMPOL) Address Offset: $0001 Read: Write: Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 0 0 0 0 0 0 0 0 The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the PWMPOL register.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Freescale Semiconductor, Inc... PPOL4 — Pulse Width Channel 4 Polarity 1 = PWM channel 4 output is high at the beginning of the period, then goes low when the duty count is reached. 0 = PWM channel 4 output is low at the beginning of the period, then goes high when the duty count is reached. PPOL3 — Pulse Width Channel 3 Polarity 1 = PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions PWM Clock Select Register (PWMCLK) Address Offset: $0002 Read: Write: Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 0 0 0 0 0 0 0 0 Each PWM channel has a choice of two clocks to use as the clock source for that channel as described below. Read: anytime Write: anytime CAUTION: Register bits PCLK0 to PCLK7 can be written anytime.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) PCLK2 — Pulse Width Channel 2 Clock Select 1 = Clock SB is the clock source for PWM channel 2. 0 = Clock B is the clock source for PWM channel 2. Freescale Semiconductor, Inc... PCLK1 — Pulse Width Channel 1 Clock Select 1 = Clock SA is the clock source for PWM channel 1. 0 = Clock A is the clock source for PWM channel 1. PCLK0 — Pulse Width Channel 0 Clock Select 1 = Clock SA is the clock source for PWM channel 0.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions Freescale Semiconductor, Inc... Table 50 Clock B Prescaler Selects PCKB2 PCKB1 PCKB0 Value of Clock B 0 0 0 E 0 0 1 E/2 0 1 0 E/4 0 1 1 E/8 1 0 0 E / 16 1 0 1 E / 32 1 1 0 E / 64 1 1 1 E / 128 PCKA2–PCKA0 — Prescaler Select for Clock A Clock A is one of two clock sources which can be used for channels 0, 1, 4, or 5.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) PWM Center Align Enable Register (PWMCAE) Address Offset: $0004 Read: Write: Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 0 0 0 0 0 0 0 0 The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions CAE2 — Center Aligned Output Mode on channel 2 1 = Channel 2 operates in Center Aligned Output Mode. 0 = Channel 2 operates in Left Aligned Output Mode. Freescale Semiconductor, Inc... CAE1 — Center Aligned Output Mode on channel 1 1 = Channel 1 operates in Center Aligned Output Mode. 0 = Channel 1 operates in Left Aligned Output Mode.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Freescale Semiconductor, Inc... CAUTION: Change these bits only when both corresponding channels are disabled. CON67 — Concatenate channels 6 and 7 1 = Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit PWM (bit 7 of port PWMP).
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions the output for this 16-bit PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. 0 = Channels 0 and 1 are separate 8-bit PWMs. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Reserved Register (PWMPRSC) Address Offset: Read: $0007 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: Freescale Semiconductor, Inc... = Reserved or unimplemented This register is reserved for factory testing of the PWM module and is not available in normal modes.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions Read: anytime Write: anytime (causes the scale counter to load the PWMSCLA value) PWM Scale B Register (PWMSCLB) Freescale Semiconductor, Inc... Address Offset: $0009 Read: Write: Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) These registers are reserved for factory testing of the PWM module and are not available in normal modes. Read: always read $00 in normal modes Write: unimplemented in normal modes Freescale Semiconductor, Inc... WARNING: PWM Channel Counter Registers (PWMCNTx) Writing to this register when in special modes can alter the PWM functionality. Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions Bit 7 Address 5 4 3 2 1 $000C Bit 0 PWMCNT0 Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: 0 0 0 0 0 0 0 0 Reset: 0 0 0 0 0 0 0 0 Address Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Freescale Semiconductor, Inc... PWM Channel Period Registers (PWMPERx) There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions Bit 7 Address Read: Write: Reset: Address Read: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) PWM Channel Duty Registers (PWMDTYx) There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions For Boundary Case programming values, please refer to PWM Boundary Cases. Bit 7 Address Read: Write: Reset: Address Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) PWM Shutdown Register (PWMSDN) Address Offset: $0024 Read: Write: Freescale Semiconductor, Inc... Reset: Bit 7 6 5 PWMIF PWMIE 0 0 0 PWMRSTRT 0 4 PWMLVL 0 3 2 0 PWM7IN 0 0 1 Bit 0 PWM7INL PWM7ENA 0 0 = Reserved or unimplemented The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Register Descriptions PWMRSTRT — PWM Restart. Freescale Semiconductor, Inc... The PWM can only be restarted if the PWM channel input is de-asserted. After writing a ‘1’ to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes next ‘counter == 0’ phase. Also if the PWM7ENA bit is reset to 0, the PWM do not start before the counter passes $00. The bit is always read as ‘0’.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Freescale Semiconductor, Inc... Functional Description PWM Clock Select There are four available clocks called clock A, clock B, clock SA (Scaled A), and clock SB (Scaled B). These four clocks are based on the clock, E Clock which runs at the same frequency as the IP bus clock ipg_clock.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Functional Description Clock A M U X Clock to PWM Ch 0 Clock A/2, A/4, A/6,....A/512 PCKA2 PCKA1 PCKA0 PCLK0 8-bit Down Counter Count=1 M U X Load Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Freescale Semiconductor, Inc... Prescale The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode (ipg_freeze active) the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Functional Description When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Freescale Semiconductor, Inc... As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for this case will be E divided by 4. A pulse will occur at a rate of once every 255x4 E cycles.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Clock Source From Port PWMP Data Register 8-bit Counter GATE PWMCNTx (clock edge sync) 8-bit Compare = up/down reset T M U Q PWMDTYx Freescale Semiconductor, Inc... Q R M U To Pin Driver 8-bit Compare = PWMPERx PPOLx Q T CAEx Q R PWMEx Figure 47 PWM Timer Channel Block Diagram PWM Enable CAUTION: Each PWM channel has an enable bit (PWMEx) to start its waveform output.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Functional Description Freescale Semiconductor, Inc... edge. When the channel is disabled (PWMEx=0), the counter for the channel does not count. PWM Polarity Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram as a mux select of either the Q output or the Q output of the PWM output flip flop.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Freescale Semiconductor, Inc... PWM Timer Counters Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (reference PWM Clock Select for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 47.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Functional Description The counter is cleared at the end of the effective period (see Left Aligned Outputs and Center Aligned Outputs for more details). Table 52 PWM Timer Counter Conditions Counter Clears ($00) Counter Counts When PWMCNTx register written to any value Freescale Semiconductor, Inc... Effective period ends Left Aligned Outputs When PWM channel is enabled (PWMEx=1). Counts from last value in PWMCNTx.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) PPOLx=0 PPOLx=1 PWMDTYx Period = PWMPERx Freescale Semiconductor, Inc... Figure 48 PWM Left Aligned Output Waveform To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register for that channel.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Functional Description E=100ns DUTY CYCLE = 75% PERIOD = 400ns Freescale Semiconductor, Inc... Figure 49 PWM Left Aligned Output Example Waveform Center Aligned Outputs For Center Aligned Output Mode selection, set the CAEx bit (CAEx=1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) PPOLx=0 PPOLx=1 PWMDTYx PWMDTYx PWMPERx PWMPERx Freescale Semiconductor, Inc... Period = PWMPERx*2 Figure 50 PWM Center Aligned Output Waveform To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Functional Description E=100ns E=100ns DUTY CYCLE = 75% PERIOD = 800ns Freescale Semiconductor, Inc... Figure 51 PWM Center Aligned Output Example Waveform PWM 16-Bit Functions The PWM timer also has the option of generating 8-channels of 8-bits or 4-channels of 16-bits for greater PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Clock Source 7 High Low PWMCNT6 PWCNT7 Period/Duty Compare PWM7 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Functional Description Freescale Semiconductor, Inc... channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown in Figure 52. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) PWM Boundary Cases The following table summarizes the boundary conditions for the PWM regardless of the output mode (Left Aligned or Center Aligned) and 8-bit (normal) or 16-bit (concatenation): Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Modes of Operation Freescale Semiconductor, Inc... Modes of Operation Normal Modes The PWM module behaves as described within this specification in all normal modes. Special Modes The PWM module behaves as described within this specification in all special modes. WARNING: While in special modes, do not access registers $0006, $0007, $000A and $000B. Writing to any of these registers can alter the PWM functionality.
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Freescale Semiconductor, Inc. Pulse Width Modulator (PWM) Low Power Options This section summarizes the low power options available in the PWM module. Low power design practices are implemented where possible. Freescale Semiconductor, Inc... The IP bus module clock (ipb_clk) is used for the programming model register writes. This clock is active only when module_en is asserted.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Enhanced Capture Timer (ECT) Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) byte and low byte separately for all of these registers may not yield the same result as accessing them in one word. Freescale Semiconductor, Inc... Features • 16-Bit Buffer Register for four Input Capture (IC) channels. • Four 8-Bit Pulse Accumulators with 8-bit buffer registers associated with the four buffered IC channels. Configurable also as two 16-Bit Pulse Accumulators. • 16-Bit Modulus Down-Counter with 4-bit Prescaler.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Abbreviations Freescale Semiconductor, Inc... PACLK – 16-bit pulse accumulator A (PACA) clock MC9S12DP256 — Revision 1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Block Diagram M clock 16-bit Free-running 16 Bit MAIN TIMER main timer Prescaler PCLK 16-bit load register ÷ 1, 4, 8, 16 M clock 16-bit modulus down counter Prescaler RESET 0 Underflow TIMCLK ÷ 1, 2, ...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Block Diagram 16-bit Free-running 16 Bit MAIN TIMER main timer TIMCLK ÷1, 2, ...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Load holding register and reset pulse accumulator 0 8-bit PAC0 (PACN0) EDG0 Edge detector Delay counter PA0H holding register Interrupt 0 EDG1 PT1 Edge detector 8-bit PAC1 (PACN1) Delay counter IP data bus Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Block Diagram TIMCLK(Timer clock) CLK1 CLK0 PACLK PACLK / 256 PACLK / 65536 Clock select (PAMOD) Edge detector PT7 Interrupt 8-bit PAC3 (PACN3) 8-bit PAC2 (PACN2) MUX PACA Divide by 64 M clock Intermodule Bus Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Pulse accumulator A PAD Freescale Semiconductor, Inc... OC7 (OM7=1 or OL7=1) or (OC7M7 = 1) Figure 57 Block Diagram for Port7 with Output compare/Pulse Accumulator A 16-bit Main Timer PTn Edge detector Delay counter Set CnF Interrupt TCn Input Capture Reg. TCnH I.C. Holding Reg. BUFEN •∑ LATQ • TFMOD Figure 58 Interrupt Flag Setting MC9S12DP256 — Revision 1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Enhanced Capture Timer (ECT) Block Diagram ECTOVI (Timer overflow interrupt) ECTPAAO (PACA overflow interrupt) ECTPAAI (PACA input interrupt) ECTPABO (PACB overflow interrupt) ECTMCUFI (Modulus counter interrupt) Interrupt Vector Generation ECTCH (0–7) (Timer input capture/output compare interrupt) Figure 59 Interrupt Enable Bits MC9S12DP256 — Revision 1.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Signal Descriptions Pad / Pin Interface IPbus Interface wdata[15:0] Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Module Memory Map IModule Specific Signals Figure 61 summarizes the ect_16b8c signal characteristics. Figure 61 ECT16b8c Signal Characteristics Signal Name Mnemonic Input/ Active Output State Reset State Function Pad Input Signals Timer Input Data ect_ic_ind[7:0] Input — — Input digital from buffer to module Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Module Memory Map Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Freescale Semiconductor, Inc... This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions immediately. The action taken is the same as if a successful comparison had just taken place with the TCn register except the interrupt flag does not get set Freescale Semiconductor, Inc... NOTE: A successful channel 7 output compare overrides any channel 6:0 compares.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Output Compare 7 Data Register (OC7D) Register offset: $0003 RESET: Bit 7 6 5 4 3 2 1 Bit 0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read or write anytime. A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Timer System Control Register 1 (TSCR1) Register offset: $0006 RESET: Bit 7 6 5 4 TEN TSWAI TSFRZ TFFCA 0 0 0 0 3 2 1 Bit 0 0 0 0 0 Freescale Semiconductor, Inc... Read or write anytime. TEN — Timer Enable 1 = Allows the timer to function normally. 0 = Disables the main timer, including the counter. Can be used for reducing power consumption.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Enhanced Capture Timer (ECT) TFFCA — Timer Fast Flag Clear All 1 = For TFLG1($0E), a read from an input capture or a write to the output compare channel ($10–$1F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($0F), any access to the TCNT register ($04, $05) clears the TOF flag. Any access to the PACN3 and PACN2 registers ($22, $23) clears the PAOVF and PAIF flags in the PAFLG register ($21).
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Timer Control Registers 1and 2 (TCTL1, TCTL2) Register offset: $0008 Bit 7 6 5 4 3 2 1 Bit 0 TCTL1 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 RESET 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCTL2 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 RESET 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Register offset: $0009 Read or write anytime.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Timer Control Registers 3 and 4 (TCTL3, TCTL4) Register offset: $000A Bit 7 6 5 4 3 2 1 Bit 0 TCTL3 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A RESET: 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 TCTL4 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A RESET: 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Register offset: $000B Read or write anytime.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Timer Interrupt Enable Register (TIE) Register offset: $000C RESET: Bit 7 6 5 4 3 2 1 Bit 0 C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read or write anytime. The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously. If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is reset from $FFFF to $0000. PR2, PR1, PR0 — Timer Prescaler Select Freescale Semiconductor, Inc... These three bits specify the number of ÷2 stages that are to be inserted between the module clock and the main timer counter.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Read anytime. Write used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel ($10–$1F) will cause the corresponding channel flag CnF to be cleared. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Timer Input Capture/Output Compare Registers 0Ð7 (TC0ÐTC7) Register offset: $0010–$001F Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions 16-Bit Pulse Accumulator A Control Register (PACTL) Register offset: $0020 Freescale Semiconductor, Inc... RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 0 0 16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit pulse accumulators PAC3 and PAC2. When PAEN is set, the PACA is enabled. The PACA shares the input pin with IC7.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) PAMOD — Pulse Accumulator Mode This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). 1 = gated time accumulation mode 0 = event counter mode PEDGE — Pulse Accumulator Edge Control Freescale Semiconductor, Inc... This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). For PAMOD bit = 0 (event counter mode).
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) PAIF — Pulse Accumulator Input edge Flag Set when the selected edge is detected at the PT7 input pin. In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PT7 input pin triggers PAIF. Freescale Semiconductor, Inc... This bit is cleared by a write to the PAFLG register with bit 0 set.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Pulse Accumulators Count Registers (PACN1, PACN0) Freescale Semiconductor, Inc... Register offset: $0024–$0025 PACN1 Bit 7 6 5 4 3 2 1 Bit 0 PACN0 Bit 7 6 5 4 3 2 1 Bit 0 RESET 0 0 0 0 0 0 0 0 Read or write any time. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) MODMC — Modulus Mode Enable 1 = Modulus mode is enabled. When the counter reaches $0000, the counter is loaded with the latest value written to the modulus count register. 0 = The counter counts once from the value written to it and will stop at $0000. Freescale Semiconductor, Inc... NOTE: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to $FFFF.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions When MCEN=0, the counter is preset to $FFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. MCPR1, MCPR0 — Modulus Counter Prescaler select Freescale Semiconductor, Inc... These two bits specify the division rate of the modulus counter prescaler.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read. Freescale Semiconductor, Inc... Each POLFx corresponds to a timer PORTx input. 1 = The first input capture has been caused by a rising edge. 0 = The first input capture has been caused by a falling edge.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions If enabled, after detection of a valid edge on input capture pin, the delay counter counts the pre-selected number of M clock (module clock) cycles, then it will generate a pulse on its output. The pulse is generated only if the level of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to narrow input pulses. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Freescale Semiconductor, Inc... NOVWx — No Input Capture Overwrite 1 = The related capture register or holding register cannot be written by an event unless they are empty (see IC Channels). This will prevent the captured value to be overwritten until it is read or latched in the holding register. 0 = The contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions Freescale Semiconductor, Inc... In all other input capture cases the interrupt flag is set by a valid external event on PTn. 1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags C3F–C0F in TFLG1 ($0E) are set only when a latch on the corresponding holding register occurs. If the queue mode is not engaged, the timer flags C3F–C0F are set the same way as for TFMOD=0.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Freescale Semiconductor, Inc... With a latching event the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse accumulators are cleared. 0 = Queue Mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input pin transition.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions 16-Bit Pulse Accumulator B Control Register (PBCTL) Register offset: $0030 Freescale Semiconductor, Inc... RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 PBEN 0 0 0 0 PBOVI 0 0 0 0 0 0 0 0 0 Read or write any time. 16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit pulse accumulators PAC1 and PAC0. When PBEN is set, the PACB is enabled. The PACB shares the input pin with IC0.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Pulse Accumulator B Flag Register (PBFLG) Register offset: $0031 RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 PBOVF 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read or write any time. PBOVF — Pulse Accumulator B Overflow Flag This bit is set when the 16-bit pulse accumulator B overflows from $FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from $FF to $00.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Register Descriptions These registers are used to latch the value of the corresponding pulse accumulator when the related bits in register ICPAR ($28) are enabled (see Pulse Accumulators). Freescale Semiconductor, Inc... Modulus Down-Counter Count Register (MCCNT) Register offset: $0036–$0037 RESET: BIt 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 1 1 1 1 1 1 1 1 Read or write any time.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) If modulus mode is not enabled (MODMC=0), a write to this address will clear the prescaler and will immediately update the counter register with the value written to it and down-counts once to $0000 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Modes of Operation Modes of Operation Freescale Semiconductor, Inc... The Enhanced Capture Timer has 8 Input Capture, Output Compare (IC/OC) channels same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the IOSx bit in TIOS register, they are called Input Capture (IC) channels.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) cleared, with a new occurrence of a capture, the contents of IC register are overwritten by the new value. If the corresponding NOVWx bit of the ICOVW register is set, the capture register cannot be written unless it is empty. This will prevent the captured value to be overwritten until it is read. Freescale Semiconductor, Inc... Buffered IC Channels There are two modes of operations for the buffered IC channels.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Modes of Operation In queue mode, reads of holding register will latch the corresponding pulse accumulator value to its holding register. Freescale Semiconductor, Inc... Pulse Accumulators There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC buffered channels. A pulse accumulator counts the number of active edges at the input of its channel.
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Interrupts This section describes interrupts originated by the ECT block.The MCU must service the interrupt requests. Table 63 lists the interrupts generated by the ECT to communicate with the MCU. Table 63 ECT Interrupts Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Enhanced Capture Timer (ECT) Description of Interrupt Operation Description of Interrupt Operation Freescale Semiconductor, Inc... The ECT only originates interrupt requests. The following is a description of how the ECT makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Enhanced Capture Timer (ECT) MC9S12DP256 — Revision 1.1 Enhanced Capture Timer (ECT) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Serial Communications Interface (SCI) Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 SCI Interface Diagram. . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) • Separately enabled transmitter and receiver • Programmable transmitter output parity • Two receiver wakeup methods: – Idle line wakeup – Address mark wakeup • Interrupt-driven operation with eight flags: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Modes of Operation • Wait Mode SCI operation in wait mode is a configurable low power mode. Depending on the state of internal bits, the SCI can operate normally when the CPU is in wait mode or the SCI clock generation can be turned off and the SCI module enters a power conservation state during wait mode. In the later case, any transmission or reception in progress stops at wait mode entry. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCI Interface Diagram Block Diagram Freescale Semiconductor, Inc... Figure 63 is a block diagram of the SCI.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Signal Descriptions Signal Descriptions Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) sci_tx_obe If the pad is controlled by the SCI, then this signal determines whether the SCI will drive sci_tx_do. Interrupt Signal The SCI has one interrupt signal. Refer to the Interrupt Operation subsection for more details. Freescale Semiconductor, Inc... Module Memory Map The memory map for the SCI module is given below in Table 65. The Address listed for each register is the address offset.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Quick Reference Register Quick Reference Freescale Semiconductor, Inc... Register name Bit 7 6 5 0 0 0 SBR7 SBR6 SBR5 SCIBDH Read: Write: SCIBDL Read: Write: SCICR1 Read: LOOPS SCISWAI RSRC Write: SCICR2 Read: Write: SCISR1 4 3 2 1 Bit 0 Addr.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions Freescale Semiconductor, Inc... This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register location do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions Write: anytime SBR12–SBR0 — SCI Baud Rate Bits Freescale Semiconductor, Inc... The baud rate for the SCI is determined by these 13 bits. NOTE: The baud rate generator is disabled until the TE bit or the RE bit is set for the first time after reset. The baud rate generator is disabled when BR = 0.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 0 = SCI enabled in wait mode RSRC — Receiver Source Bit When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. 1 = Receiver input connected externally to transmitter 0 = Receiver input internally connected to transmitter output Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions PE — Parity Enable Bit PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 1 = Parity function enabled 0 = Parity function disabled Freescale Semiconductor, Inc... PT — Parity Type Bit PT determines whether the SCI generates and checks for even parity or odd parity.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) TCIE — Transmission Complete Interrupt Enable Bit TCIE enables the transmission complete flag, TC, to generate interrupt requests. 1 = TC interrupt requests enabled 0 = TC interrupt requests disabled Freescale Semiconductor, Inc... RIE — Receiver Full Interrupt Enable Bit RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions SBK — Send Break Bit Freescale Semiconductor, Inc... Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11, respectively 13 or 14 bits).
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) TC — Transmit Complete Flag Freescale Semiconductor, Inc... TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the sci_tx_do becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions Freescale Semiconductor, Inc... OR — Overrun Flag OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCI Status Register 2 (SCISR2) Address Offset: $005 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 W RESET: 2 1 BRK13 TXDIR 0 0 0 RAF 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Register Descriptions SCI Data Registers (SCIDRH/L) Address Offset: $006 7 R R8 W RESET: 0 6 T8 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) NOTE: In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. NOTE: When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH), then SCIDRL. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits. Freescale Semiconductor, Inc... Table 67 Example of 8-bit Data Formats Start Bit 1 1 Data Bits 8 7 Address Bits 0 0 Parity Bits 0 1 Stop Bit 1 1 1 7 1(1) 0 1 1. The address bit identifies the frame as an address character. See section on Receiver Wakeup.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) • Synchronization with the bus clock can cause phase shift. Figure 69 lists some examples of achieving target baud rates with a module clock frequency of 25 MHz SCI baud rate = SCI module clock / (16 *SCIBR[12:0]) Freescale Semiconductor, Inc... Table 69 Baud Rates (Example: Module Clock = 25.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Transmitter INTERNAL BUS ÷ 16 BAUD DIVIDER STOP SBR12–SBR0 H 11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0 sci_tx_do L PARITY GENERATION LOOP CONTROL BREAK (ALL 0s) PT PREAMBLE (ALL ONES) PE LOAD FROM SCIDR T8 SHIFT ENABLE MSB M Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Freescale Semiconductor, Inc... Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Freescale Semiconductor, Inc... Break Characters Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1).
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description NOTE: If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin. Receiver INTERNAL BUS sci_rx_ind FROM sci_tx_ind OR TRANSMITTER LOOP CONTROL RE 11-BIT RECEIVE SHIFT REGISTER START DATA RECOVERY STOP BAUD DIVIDER H 8 L 7 6 5 4 3 2 1 0 MSB MODULE CLOCK SCI DATA REGISTER ALL ONES Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Character Reception During an SCI reception, the receive shift register shifts a frame in from the sci_rx_ind signal. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. Data Sampling The receiver samples the sci_rx_ind signal at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Figure 70 summarizes the results of the start bit verification samples. Table 70 Start Bit Verification Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Table 72 Stop Bit Recovery Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0 In Figure 69, the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
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Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Figure 72 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description In Figure 74, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Slow Data Tolerance Figure 75 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. MSB STOP Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Fast Data Tolerance Figure 76 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. STOP IDLE OR NEXT FRAME RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RECEIVER RT CLOCK Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description The logic 1 msb of an address frame clears the receiver’s RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) . TRANSMITTER RECEIVER sci_tx_do RXD Freescale Semiconductor, Inc... Figure 78 Loop Operation (LOOPS = 1, RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the sci_rx_ind signal to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Interrupt Operation Stop Mode The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI module clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Freescale Semiconductor, Inc... operation) and all the following interrupts, when generated, are ORed together and issued through that port. TDRE Description The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit shift register (SCIDRH/L) is empty and that a new byte can be written to the SCIDRH/L for transmission.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Interrupt Operation Freescale Semiconductor, Inc... idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). MC9S12DP256 — Revision 1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Serial Communications Interface (SCI) MC9S12DP256 — Revision 1.1 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Features Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Block Diagram This is a high level description only, detailed descriptions of operating modes are contained in section Low Power Mode Options.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Signal Descriptions Table 74 summarizes the Serial Peripheral Interface pad interface signal characteristics. Table 74 SPI Pad Interface Signal Characteristics Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Signal Descriptions Basically four signals are used in the following configuration (Refer to Figure 80) to generate each of the ports MISO, MOSI, SCK and SS. Figure 80 SPI External Interface ss_do 0 SPI BLOCK 1 ss_obe SS PAD GPI/O Freescale Semiconductor, Inc... ss_port_en ss_ind Pad Input Signals Slave Data in (spi_mosi_ind) This is one of the two SPI module pins that transmit serial data.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Freescale Semiconductor, Inc... Normally this signal is asserted when the SPE bit of the SPICR1 register is set. Also, when configured in Slave mode and in Bidirectional mode of operation, this signal is de-asserted. Miso port enable (miso_port_en) This pin indicates that the SPI is the master of the MISO pad. SS port enable (ss_port_en) This pin indicates that the SPI is the master of the SS pad.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Signal Descriptions SCK port output enable (sck_obe) This pin indicates that the SCK output buffer is enabled if sck_port_en was set. Freescale Semiconductor, Inc... Output Signals Master Data out (spi_mosi_do) This pin is used to transmit data out of the SPI module when it is configured as a Master. Slave Data out (spi_miso_do) This pin is used to transmit data out of the SPI module when it is configured as a Slave.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Module Memory Map Freescale Semiconductor, Inc... The memory map for the Serial Peripheral Interface is given below in Table 75. The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from reserved addresses ($0006 through $0007 and $0004) return zeros and writes to reserved addresses have no effect.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Quick Reference Register Quick Reference Register Name Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions Freescale Semiconductor, Inc... This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions MSTR — SPI Master/Slave Mode Select Bit 1 = Master mode 0 = Slave mode Freescale Semiconductor, Inc... CPOL — SPI Clock Polarity Bit This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPI Control Register 2 (SPICR2) Address Offset: $0001 R Bit 7 6 5 0 0 0 0 0 0 W Reset: 4 3 MODFEN BIDIROE 0 0 2 0 0 1 Bit 0 SPISWAI SPC0 0 0 Freescale Semiconductor, Inc... = Unimplemented or Reserved Read: anytime Write: anytime; writes to unimplemented bits have no effect MODFEN — Mode Fault Enable Bit This bit when set allows the MODF flag to be set.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions Table 77 Bidirectional Pin Configurations Pin Mode SPC0 A Normal B C Bidirectional D MSTR 0 1 0 1 0 1 MISO (1) MOSI (2) Slave Out Slave In Master In Master Out Slave I/O ----Master I/O SCK (3) SCK in SCK out SCK in SCK out SS (4) SS in SS I/O SS In SS I/O 1. Slave output is enabled if BIDIROE bit = 1, SS = 0, and MSTR = 0 (C) Freescale Semiconductor, Inc... 2.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPI Status Register (SPISR) Address Offset: $0003 R Bit 7 6 5 4 3 2 1 Bit 0 SPRF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 W Reset: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Register Descriptions MODF — Mode Fault Flag Freescale Semiconductor, Inc... This bit is set if the SS input becomes low while the SPI is configured as a master. The flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. The MODF flag is set only if the MODFEN bit of SPICR2 register is set, Refer to MODFEN bit description in SPI Control Register 2 (SPICR2).
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. Freescale Semiconductor, Inc... The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description two fundamentally different protocols by shifting the clock by a half cycle or by not shifting the clock (see Transmission Formats). The SPI can be configured to operate as a master or as a slave. When MSTR in SPI control register1 is set, the master mode is selected; when the MSTR bit is clear, the slave mode is selected. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) status register. If the SPI interrupt enable bit (SPIE) is set when the MODF bit gets set, then an SPI interrupt sequence is also requested Freescale Semiconductor, Inc... When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB of the SPI shifter. Freescale Semiconductor, Inc... If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB of the SPI shifter.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Clock Phase and Polarity Controls Using two bits in the SPI control register1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. Freescale Semiconductor, Inc... The CPHA clock phase control bit selects one of two fundamentally different transmission formats.
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Freescale Semiconductor, Inc. • Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master. • The SPIF flag in the SPI status register is set indicating that the transfer is complete. Figure 83 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The SS line can remain active low between successive transfers. NOTE: Freescale Semiconductor, Inc... CPHA = 1 Transfer Format There is a functional hazard, the SPI may lose data in this mode (CPHA=0) if configured as a slave with the SCK rate at div2 of the slave’s module clock (see Errata).
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) automatically when the SPI status register is read (with SPIF set) followed by a read or write to the SPI data register. If the SPIE bit is set when the SPIF flag is set, a hardware interrupt is requested. Freescale Semiconductor, Inc... SPI Baud Rate Generation Baud rate generation consists of a series of divider stages.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description Special Features SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Table 79 Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Serial Out Normal Mode SPC0 = 0 SPI Freescale Semiconductor, Inc... Serial Out Bidirectional Mode SPC0 = 1 Serial In MOSI Serial Out MISO MOMI BIDIROE & MSTR Serial In Serial In SPI SPI port pin 0 MOSI BIDIROE & MSTR SPI BIDIROE & MSTR Serial In SPI Slave Mode MSTR = 0 MISO SPI port pin 1 BIDIROE & MSTR Serial Out SISO .
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Low Power Mode Options In the special case where the MODFEN bit is cleared, the SS pin is a general purpose input/output pin for the SPI system configured in master mode. In this special case, the mode error function is inhibited and MODF remains cleared. Freescale Semiconductor, Inc... In case the SPI system is configured as a slave and the MODFEN bit is cleared the SS pin is a dedicated input pin.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. Freescale Semiconductor, Inc... – If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Errata Errata There is a case where data may be lost between the master and slave SPI modules. This occurs only if the following settings are true: 1. SCK is running at busclock/2 in slave mode of operation 2. Transmission protocol CPHA = 0 Freescale Semiconductor, Inc... 3. SPIDR write to slave just before SS sync goes low Figure 86 depicts the module clock just before the SCK edge.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) This hazard is most visible when the SCK runs at div2 of the slave’s module clock. At other baud rates, there is more time between the falling SS signal and the first SCK edge. i.e. div4 has two module clocks between the SS fall and the SCK edge. Freescale Semiconductor, Inc... Reset The reset values of registers and signals are described in Registers. All registers reset to a particular value.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Serial Peripheral Interface (SPI) Interrupts Description of Interrupt Operation The Serial Peripheral Interface only originates interrupt requests. The following is a description of how the Serial Peripheral Interface makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. MODF Description MODF occurs when the master detects an error on the SS pin.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Serial Peripheral Interface (SPI) MC9S12DP256 — Revision 1.1 Serial Peripheral Interface (SPI) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Inter-IC Bus (IIC) Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pF. Features Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Block Diagram • Wait Mode IIC operation in wait mode is a configurable low power mode. Depending on the state of internal bits, the IIC can operate normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module enters a power conservation state during wait mode. In the later case, any transmission or reception in progress stops at wait mode entry. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) addr module_en rdata wdata iic_int Freescale Semiconductor, Inc... ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG Input Sync Start Stop Arbitration Control Clock DATA_REG In/Out Data Shift Register Address Control Compare iic_scl_do iiic_scl_ind iic_sda_do iic_sda_ind Figure 87 IIC Block Diagram MC9S12DP256 — Revision 1.1 Inter-IC Bus (IIC) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Signal Descriptions Signal Descriptions The IIC is a 16-bit module. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) iic_sda_obe If the pad is controlled by the IIC, then this signal determines whether the IIC will drive iic_sda_do. Interrupt Signals The IIC has one interrupt signal iic_int. Refer to Section 6 of this document for the details regarding this signal. Freescale Semiconductor, Inc... Module Memory Map The memory map for the IIC module is given below in Table 3-1. The Address listed for each register is the address offset.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Register Quick Reference Register Quick Reference Table 83 Register Quick Reference Register name Freescale Semiconductor, Inc... IBAD IBFD IBCR IBSR IBDR Read: Write: Reset Read: Write: Reset Read: Write: Reset Read: Write: Reset Read: Write: Reset Bit 7 6 5 4 3 2 1 Bit 0 Addr.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) IIC Address Register (IBAD) Address Offset: $0000 RESET: Bit 7 6 5 4 3 2 1 Bit 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Register Descriptions IIC Frequency Divider Register (IBFD) Address Offset: $0001 Reset: Bit 7 6 5 4 3 2 1 Bit 0 IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read and write anytime IBC7–IBC0 — I-Bus Clock Rate 7–0 This field is used to prescale the clock for bit rate selection.
PAGE 472
Freescale Semiconductor, Inc. Inter-IC Bus (IIC) IBC5-3 (bin) 111 scl2tap (clocks) tap2tap (clocks) 126 128 Freescale Semiconductor, Inc... Table 85 Divider Factor IBC7-6 DIV 00 1 01 2 10 4 11 RESERVED The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Figure 84, all subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Figure 84.
PAGE 473
Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Register Descriptions IIC Control Register (IBCR) Address Offset: $0002 Reset: Bit 7 6 5 4 3 2 1 Bit 0 IBEN IBIE MS/SL Tx/Rx TXAK RSTA 0 IBSWAI 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read and write anytime IBEN — I-Bus Enable This bit controls the software reset of the entire IIC Bus module. 1 = The IIC Bus module is enabled. This bit must be set before any other IBCR bits have any effect.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) generated and the operation mode changes from master to slave. MS/SL is cleared without generating a STOP signal when the master loses arbitration. 1 = Master Mode 0 = Slave Mode Freescale Semiconductor, Inc... Tx/Rx — Transmit/Receive mode select bit This bit selects the direction of master and slave transfers. When addressed as a slave this bit should be set by software according to the SRW bit in the status register.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Register Descriptions 0 = IIC Bus module clock operates normally Freescale Semiconductor, Inc... Wait mode is entered via execution of a CPU WAI instruction. In the event that the IBSWAI bit is set, all clocks internal to the IIC will be stopped and any transmission currently in progress will halt.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) IAAS — Addressed as a slave bit Freescale Semiconductor, Inc... When its own specific address (I-Bus Address Register) is matched with the calling address, this bit is set. The CPU is interrupted provided the IBIE is set. Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly. Writing to the I-Bus Control Register clears this bit. 1 = Addressed as a slave 0 = Not addressed IBB — Bus busy bit This bit indicates the status of the bus.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Register Descriptions SRW — Slave Read/Write When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master. Freescale Semiconductor, Inc... This bit is only valid when the I-Bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master.
PAGE 478
Freescale Semiconductor, Inc. Inter-IC Bus (IIC) IIC Data I/O Register (IBDR) Address Offset: $0004 Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) I-Bus Protocol Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 88. MSB SCL Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Freescale Semiconductor, Inc... Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 88). No two slaves in the system may have the same address.
PAGE 481
Freescale Semiconductor, Inc. Inter-IC Bus (IIC) I-Bus Protocol STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical “1” (see Figure 88). Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) state during this time (see Figure 89). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Interrupt Operation Freescale Semiconductor, Inc... Interrupt Operation System Level Interrupt Sources There is one interrupt signal that is sent from the IIC to the core. Interrupt Descriptions See the Interrupts section of the End User Guide, which describes the Interrupt signals generated by the IIC Status registers. Internally there are three types of interrupts. These are generated on 1. Arbitration Lost Interrupt 2. Byte Transfer Interrupt 3.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Freescale Semiconductor, Inc... This bit must be cleared by software, by writing a low to it. Byte Transfer Interrupt After completion of byte transfer, TCF (Data Transfer) bit is set at the falling edge of the 9th clock to indicate the completion of Byte Transfer. Address Detect Interrupt When its own specific address (I-Bus Address Register) is matched with the calling address, IAAS bit in Status register is set.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Programming Programming Initialization Sequence Reset will put the IIC Control Register to its default status. Before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: Freescale Semiconductor, Inc... 1. Update the Frequency Divider Register (IBFD) and select the required division ratio to obtain SCL frequency from system clock. 2.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) An example of a program which generates the START signal and transmits the first byte of data (slave address) is shown below: CHFLAG TXSTART Freescale Semiconductor, Inc... IBFREE Post-Transfer Software Response BRSET BSET IBSR,#$20, * IBCR,#$30 MOVEB CALLING,IBDR BRCLR #5,IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR ;SET TRANSMIT AND MASTER MODE ;i.e.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Programming ISR TRANSMIT Freescale Semiconductor, Inc... Generation of STOP BCLR BRCLR BRCLR BRSET MOVB IBSR,#$02 IBCR,#$20,SLAVE IBCR,#$10,RECEIVE IBSR,#$01,END DATABUF,IBDR ;CLEAR THE IBIF FLAG ;BRANCH IF IN SLAVE MODE ;BRANCH IF IN RECEIVE MODE ;IF NO ACK, END OF TRANSMISSION ;TRANSMIT NEXT BYTE OF DATA A data transfer ends with a STOP signal generated by the ‘master’ device.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Generation of Repeated START At the end of data transfer, if the master still wants to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is as shown. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Programming Freescale Semiconductor, Inc... Arbitration Lost If several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the hardware. Their data output to the SDA line is stopped, but SCL is still generated until the end of the byte during which arbitration was lost.
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Freescale Semiconductor, Inc. Inter-IC Bus (IIC) Clear IBIF Master Mode ? Y Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. MSCAN MSCAN Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 Register Map. . . .
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Freescale Semiconductor, Inc. MSCAN MSCAN utilizes an advanced buffer arrangement resulting in a predictable real-time behavior and simplifies the application software. Features Freescale Semiconductor, Inc... The basic features of the MSCAN are as follows: • Modular architecture • Implementation of the CAN protocol – Version 2.
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Freescale Semiconductor, Inc. MSCAN Block Diagram • Global initialization of configuration registers Freescale Semiconductor, Inc... Block Diagram Message Filtering and Buffering Receive/ Transmit Engine rxcan_ind txcan_do Control and Status port_en Module Bus Interface IPbus Figure 91 MSCAN Block Diagram MC9S12DP256 — Revision 1.1 MSCAN For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. MSCAN External Pin Descriptions Freescale Semiconductor, Inc... The MSCAN uses 2 external pins, 1 input (RxCAN) and 1 output (TxCAN). The TxCAN output pin represents the logic level on the CAN: • ‘0’ is for a dominant state • ‘1’ is for a recessive state When the MSCAN is enabled (CANE=1) via the CANCTL1 register, the TxCAN and RxCAN pins will be enabled within the Port Module. This is indicated to Port Module using a dedicated enable line (ipp_port_en).
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Freescale Semiconductor, Inc. MSCAN External Pin Descriptions CAN node 2 CAN node 1 CAN node n Freescale Semiconductor, Inc... MCU CAN Controller (MSCAN) TxCAN RxCAN Transceiver CAN_H CAN_L CAN Bus Figure 92 The CAN System MC9S12DP256 — Revision 1.1 MSCAN For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. MSCAN Register Map The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. Address Offset Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. MSCAN Register Map Reserved bits within a register always read as 0 and a write is unimplemented1. Unimplemented functions are indicated by shading the bit. Register name CANCTL0 CANCTL1 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. MSCAN Register name CANIDAR1 CANIDAR2 CANIDAR3 CANIDMR0 Freescale Semiconductor, Inc... CANIDMR1 CANIDMR2 CANIDMR3 CANIDAR4 CANIDAR5 CANIDAR6 CANIDAR7 CANIDMR4 CANIDMR5 CANIDMR6 CANIDMR7 CANRXFG CANTXFG Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 6 5 4 3 2 1 Bit 0 Addr.
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Freescale Semiconductor, Inc. MSCAN Functional Description Functional Description Message Storage MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. Rx0 Rx2 Rx3 Receiver TxBG Tx0 TxFG Tx1 MSCAN TxBG Tx2 Transmitter RXF CPU bus RxFG MSCAN RxBG Freescale Semiconductor, Inc... Rx1 TXE0 PRIO TXE1 CPU bus PRIO TXE2 PRIO Figure 95 User Model for Message Buffer Organization MC9S12DP256 — Revision 1.
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Freescale Semiconductor, Inc. MSCAN Message Transmit Background Modern application layer software is built upon two fundamental assumptions: 1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus between the two messages. Such nodes arbitrate for the bus immediately after sending the previous message and only release the bus in case of lost arbitration. Freescale Semiconductor, Inc... 2.
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Freescale Semiconductor, Inc. MSCAN Functional Description Freescale Semiconductor, Inc... All three buffers have a 13 byte data structure similar to the outline of the receive buffers (see Programmer’s Model of Message Storage). An additional Transmit Buffer Priority Register (TBPR) contains an 8-bit ‘Local Priority’ field (PRIO). The remaining two bytes are used for time stamping of a message, if required (see Time Stamp Register (TSRH, TSRL)).
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Freescale Semiconductor, Inc. MSCAN Freescale Semiconductor, Inc... value of the PRIO field is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MSCAN Functional Description RxBG. After successful reception of a valid message the MSCAN shifts the content of RxBG into the receiver FIFO1, sets the RXF flag, and generates a receive interrupt (see Interrupt Operation) to the CPU2. The user’s receive handler has to read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer.
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Freescale Semiconductor, Inc. MSCAN Freescale Semiconductor, Inc... Identifier Acceptance Filter The MSCAN Identifier Acceptance Registers (see MSCAN Identifier Acceptance Registers (CANIDAR0–7)) define the acceptable patterns of the standard or extended identifier (ID10–ID0 or ID28–ID0). Any of these bits can be marked ‘don’t care’ in the MSCAN Identifier Mask Registers (see MSCAN Identifier Mask Registers (CANIDMR0–7)).
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Freescale Semiconductor, Inc. MSCAN Functional Description Freescale Semiconductor, Inc... CANIDMR0–3) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4–7, CANIDMR4–7) produces filter 2 and 3 hits. • Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard identifier or a CAN 2.0B compliant extended identifier.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MSCAN CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MSCAN Functional Description CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.
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Freescale Semiconductor, Inc. MSCAN Freescale Semiconductor, Inc... Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode.
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Freescale Semiconductor, Inc. MSCAN Functional Description MSCAN IPbus CLK IPbus Bus Interface (IPBI) CAN_CLK CLKSRC Time quanta clock (Tq) Prescaler (1... 64) CLKSRC Freescale Semiconductor, Inc... OSC_CLK Figure 99 MSCAN Clocking Scheme The Clock Source bit (CLKSRC) in the CANCTL1 register (see MSCAN Control 1 Register (CANCTL1)) defines whether the internal CAN_CLK is connected to the output of a crystal oscillator (OSC_CLK) or to the IPbus bus clock (CLK).
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Freescale Semiconductor, Inc. MSCAN SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. • Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. • Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
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Freescale Semiconductor, Inc. MSCAN Functional Description Table 86 Time Segment Syntax Freescale Semiconductor, Inc... Syntax Description SYNC_SEG System expects transitions to occur on the bus during this period. Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
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Freescale Semiconductor, Inc. MSCAN Freescale Semiconductor, Inc... Timer Stamp The MSCAN generates an internal time stamp whenever a valid frame is received or transmitted and the TIME bit is enabled. Because the CAN specification defines a frame to be valid if no errors occur before the End of Frame (EOF) field is transmitted successfully, the actual value of an internal timer is written at EOF to the appropriate time stamp position within the transmit buffer.
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Freescale Semiconductor, Inc. MSCAN Register Descriptions Read: anytime Write: anytime when out of initialization; exceptions are bits RXACT and SYNCH which are read-only and bit RXFRM which is set by the module. A write of ‘1’ to the RXFRM register clears the flag and a write of ‘0’ is ignored Freescale Semiconductor, Inc... RXFRM — Received Frame Flag This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration.
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Freescale Semiconductor, Inc. MSCAN SYNCH — Synchronized Status This flag indicates whether the MSCAN is synchronized to the CAN bus and, as such, can participate in the communication process. It is set and cleared by the MSCAN. 1 = MSCAN is synchronized to the CAN bus. 0 = MSCAN is not synchronized to the CAN bus. Freescale Semiconductor, Inc... TIME — Timer Enable This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock.
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Freescale Semiconductor, Inc. MSCAN Register Descriptions until SLPRQ is cleared by the CPU or, depending on the setting of WUPE bit, the MSCAN detects bus activity on CAN and clears the SLPRQ itself. 1 = Sleep Mode Request – The MSCAN locks in idle state. 0 = Running – The MSCAN functions normally. NOTE: The MCU cannot clear the SLPRQ bit before the MSCAN has entered Sleep Mode (SLPRQ=1 and SLPAK=1) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. MSCAN NOTE: Freescale Semiconductor, Inc... CAUTION: MSCAN Control 1 Register (CANCTL1) The MCU cannot clear the INITRQ bit before the MSCAN has entered Initialization Mode (INITRQ=1 and INITAK=1) In order to protect from accidentally violating the CAN protocol the TxCAN pin is immediately forced to a recessive state when the Initialization Mode is requested by the MCU. Thus the recommended procedure is to bring the MSCAN into Sleep Mode (SLPRQ=1 and SLPAK=1) before.
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Freescale Semiconductor, Inc. MSCAN Register Descriptions Freescale Semiconductor, Inc... LOOPB — Loop Back Self Test Mode When this bit is set, the MSCAN performs an internal loop back which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RxCAN input pin is ignored and the TxCAN output goes to the recessive state (logic ‘1’).
PAGE 518
Freescale Semiconductor, Inc. MSCAN INITRQ=1 and INITAK=1. Depending on the setting of the WUPE bit the MSCAN will clear the flag if it detects bus activity on CAN while in Sleep Mode. 1 = Sleep Mode Active – The MSCAN has entered Sleep Mode. 0 = Running – The MSCAN operates normally. Freescale Semiconductor, Inc... INITAK — Initialization Mode Acknowledge This flag indicates whether the MSCAN module is in Initialization Mode (see MSCAN Initialization Mode).
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Freescale Semiconductor, Inc. MSCAN Register Descriptions Table 87 Synchronization Jump Width SJW1 SJW0 Synchronization jump width 0 0 1 Tq clock cycle 0 1 2 Tq clock cycles 1 0 3 Tq clock cycles 1 1 4 Tq clock cycles Freescale Semiconductor, Inc... BRP[5–0] — Baud Rate Prescaler These bits determine the time quanta (Tq) clock which is used to build up the individual bit timing, as shown in Table 88.
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Freescale Semiconductor, Inc. MSCAN MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register provides for various bus timing control of the MSCAN module as described below. Address Offset: $0003 Read: Write: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. MSCAN Register Descriptions Freescale Semiconductor, Inc... Table 89 Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time segment 2 0 0 0 1 Tq clock cycle(1) 0 0 1 2 Tq clock cycles . . . . 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles 1. This setting is not valid. Please refer to Figure 101 for valid settings.
PAGE 522
Freescale Semiconductor, Inc. MSCAN MSCAN Receiver Flag Register (CANRFLG) A flag can only be cleared when the condition which caused the setting is no longer valid and can only be cleared by software (writing a ‘1’ to the corresponding bit position). Every flag has an associated interrupt enable bit in the CANRIER register. Address Offset: $0004 Read: Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. MSCAN Register Descriptions blocking interrupt. That guarantees that the Receiver / Transmitter status bits (RSTAT/TSTAT) are only updated when no CAN Status Change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted and therefore would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their old state bits until the current CSCIF interrupt is cleared again. 1 = MSCAN changed current bus status.
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Freescale Semiconductor, Inc. MSCAN RXF — Receive Buffer Full Freescale Semiconductor, Inc... The RXF flag is set by the MSCAN when a new message is available in the receiver FIFO. This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching Cyclic Redundancy Code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer.
PAGE 525
Freescale Semiconductor, Inc. MSCAN Register Descriptions Read: anytime Write: anytime when out of Initialization Mode WUPIE — Wake-up Interrupt Enable 1 = A wake-up event causes a wake-up interrupt request. 0 = No interrupt request is generated from this event. Freescale Semiconductor, Inc... NOTE: The CPU has to make sure that the Wake-up interrupt register and the WUPE register (see MSCAN Control 0 Register (CANCTL0)) is enabled, if the recovery mechanism from STOP or WAIT is required.
PAGE 526
Freescale Semiconductor, Inc. MSCAN Freescale Semiconductor, Inc... TSTATE1, TSTATE0 — Transmitter Status Change Enable These TSTAT enable bits control the sensitivity level in which transmitter state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the TSTAT flags still indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.
PAGE 527
Freescale Semiconductor, Inc. MSCAN Register Descriptions NOTE: The CANTFLG register is held in the reset state when the Initialization Mode is active (INITRQ=1 and INITAK=1). This register is writable again as soon as the Initialization Mode is left (INITRQ=0 and INITAK=0). Read: anytime Write: anytime for TXEx flags when not in Initialization Mode; write of ‘1’ clears flag, write of ‘0’ ignored Freescale Semiconductor, Inc...
PAGE 528
Freescale Semiconductor, Inc. MSCAN MSCAN Transmitter Interrupt Enable Register (CANTIER) This register contains the interrupt enable bits for the Transmit Buffer Empty interrupt flags. Address Offset: $0007 Read: Bit 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Write: Reset: 2 1 Bit 0 TXEIE2 TXEIE1 TXEIE0 0 0 0 = Unimplemented NOTE: The CANTCR register is held in the reset state when the Initialization Mode is active (INITRQ=1 and INITAK=1).
PAGE 529
Freescale Semiconductor, Inc. MSCAN Register Descriptions MSCAN Transmitter Message Abort Control (CANTARQ) The CANTARQ register provides for abort request of queued messages as described below. Address Offset: $0008 Read: Bit 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... Write: Reset: 2 1 Bit 0 ABTRQ2 ABTRQ1 ABTRQ0 0 0 0 = Unimplemented NOTE: The CANTARQ register is held in the reset state when the Initialization Mode is active (INITRQ=1 and INITAK=1).
PAGE 530
Freescale Semiconductor, Inc. MSCAN MSCAN Transmitter Message Abort Control (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register Address Offset: $0009 Freescale Semiconductor, Inc...
PAGE 531
Freescale Semiconductor, Inc. MSCAN Register Descriptions MSCAN Transmit Buffer Selection (CANTBSEL) The CANTBSEL register allows the selection of the actual transmit message buffer, which will be then accessible in the CANTXFG register space (see Programmer’s Model of Control Registers). Address Offset: $000A Read: Bit 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 Write: Reset: 2 1 Bit 0 TX2 TX1 TX0 0 0 0 Freescale Semiconductor, Inc...
PAGE 532
Freescale Semiconductor, Inc. MSCAN Freescale Semiconductor, Inc... LDAA STAA LDAA . . . LDAA STAA NOTE: MSCAN Identifier Acceptance Control Register (CANIDAC) CANTFLG CANTBSEL CANTBSEL CANTBSEL CANTFLG ; value read is 8’b0000_0110 ; value written is 8’b0000_0110 ; value read is 8’b0000_0010 ; ; Fill TxBuffer ; ; Read actual TxBuffer selection ; Transmit selected TxBuffer If all transmit message buffers are deselected no accesses are allowed to the CANTXFG registers.
PAGE 533
Freescale Semiconductor, Inc. MSCAN Register Descriptions Freescale Semiconductor, Inc... Table 91 Identifier Acceptance Mode Settings IDAM1 IDAM0 Identifier Acceptance Mode 0 0 Two 32 bit Acceptance Filters 0 1 Four 16 bit Acceptance Filters 1 0 Eight 8 bit Acceptance Filters 1 1 Filter Closed IDHIT2–IDHIT0 — Identifier Acceptance Hit Indicator The MSCAN sets these flags to indicate an identifier acceptance hit (see Identifier Acceptance Filter). Table 92 summarizes the different settings.
PAGE 534
Freescale Semiconductor, Inc. MSCAN Read: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Read: always read $00 in normal modes Write: unimplemented in normal modes Freescale Semiconductor, Inc... WARNING: MSCAN Receive Error Counter Register (CANRXERR) Writing to these registers when in special modes can alter the MSCAN functionality. This register reflects the status of the MSCAN receive error counter.
PAGE 535
Freescale Semiconductor, Inc. MSCAN Register Descriptions MSCAN Transmit Error Counter Register (CANTXERR) This register reflects the status of the MSCAN transmit error counter. Address Offset: $000F Read: Bit 7 6 5 4 3 2 1 Bit 0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 0 0 0 0 0 0 0 0 Write: Freescale Semiconductor, Inc...
PAGE 536
Freescale Semiconductor, Inc. MSCAN Bit 7 6 5 4 3 2 1 Read: Write: Reset: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 0 0 0 0 0 CANIDAR1 Address Offset: $0011 Read: Write: Freescale Semiconductor, Inc...
PAGE 537
Freescale Semiconductor, Inc. MSCAN Register Descriptions Read: anytime Write: anytime in Initialization Mode (INITRQ=1 and INITAK=1) AC7–AC0 — Acceptance Code Bits Freescale Semiconductor, Inc... AC7–AC0 comprise a user defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
PAGE 538
Freescale Semiconductor, Inc. MSCAN Bit 7 6 5 4 3 2 1 Read: Write: Reset: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 0 0 0 0 0 0 0 0 CANIDMR1 Address Offset: $0015 Read: Write: Freescale Semiconductor, Inc...
PAGE 539
Freescale Semiconductor, Inc. MSCAN Register Descriptions Read: anytime Write: anytime in Initialization Mode (INITRQ=1 and INITAK=1) Freescale Semiconductor, Inc... AM7–AM0 — Acceptance Mask Bits If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match.
PAGE 540
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
PAGE 541
Freescale Semiconductor, Inc. MSCAN Register Descriptions Register name IDR0 IDR1 IDR2 Freescale Semiconductor, Inc...
PAGE 542
Freescale Semiconductor, Inc. MSCAN Read: anytime for transmit buffers; only when RXF flag is set for receive buffers (see MSCAN Receiver Flag Register (CANRFLG)). Write: anytime for transmit buffers when TXEx flag is set (see MSCAN Transmitter Flag Register (CANTFLG)) and the corresponding transmit buffer is selected in CANTBSEL (see MSCAN Transmit Buffer Selection (CANTBSEL)); unimplemented for receive buffers Freescale Semiconductor, Inc...
PAGE 543
Freescale Semiconductor, Inc. MSCAN Register Descriptions SRR — Substitute Remote Request This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers. Freescale Semiconductor, Inc... IDE — ID Extended This flag indicates whether the extended or standard identifier format is applied in this buffer.
PAGE 544
Freescale Semiconductor, Inc. MSCAN number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 93 shows the effect of setting the DLC bits. Table 93 Data length codes Freescale Semiconductor, Inc...
PAGE 545
Freescale Semiconductor, Inc. MSCAN Register Descriptions Freescale Semiconductor, Inc... Time Stamp Register (TSRH, TSRL) If the TIME bit is enabled, the MSCAN will write a special time stamp to the respective registers in the active transmit or receive buffer as soon as a message has been acknowledged on the CAN bus (see MSCAN Control 0 Register (CANCTL0)). The time stamp is written on the bit sample point for the recessive bit of the ACK delimiter in the CAN frame.
PAGE 546
Freescale Semiconductor, Inc. MSCAN Freescale Semiconductor, Inc... Modes of Operation Normal Modes The MSCAN module behaves as described within this specification in all normal modes. Special Modes The MSCAN module behaves as described within this specification in all special modes. Emulation Modes In all emulation modes, the MSCAN module behaves just like normal modes as described within this specification.
PAGE 547
Freescale Semiconductor, Inc. MSCAN Low Power Options Low Power Options If the MSCAN is disabled (CANE=0), the MSCAN clocks are stopped for power savings. Freescale Semiconductor, Inc... If the MSCAN is enabled (CANE=1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: Sleep and Power Down Mode. In Sleep Mode power consumption is reduced by stopping all clocks except those to access the registers from the CPU side.
PAGE 548
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MSCAN CPU Run Mode As can be seen in Table 94, only MSCAN Sleep Mode is available as low power option, when CPU is in run mode. CPU Wait Mode The WAI instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set, then additional power can be saved in Power Down Mode since the CPU clocks are stopped.
PAGE 549
Freescale Semiconductor, Inc. MSCAN Low Power Options CPU Clock Domain CAN Clock Domain SLPRQ SYNC sync. SLPRQ sync. SYNC SLPAK CPU Sleep Request Freescale Semiconductor, Inc... SLPAK Flag SLPAK SLPRQ Flag MSCAN in Sleep Mode Figure 105 Sleep Request / Acknowledge Cycle CAUTION: The application software must avoid setting up a transmission (by clearing one or more TXEx flag(s)) and immediately request Sleep Mode (by setting SLPRQ).
PAGE 550
Freescale Semiconductor, Inc. MSCAN NOTE: The MCU cannot clear the SLPRQ bit before Sleep Mode (SLPRQ=1 and SLPAK=1) is active. Freescale Semiconductor, Inc... After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered.
PAGE 551
Freescale Semiconductor, Inc. MSCAN Low Power Options the MSCAN into Sleep Mode (SLPRQ=1 and SLPAK=1) before setting the INITRQ bit in the CANCTL0 register. Otherwise the abort of an ongoing message can cause an error condition and can have an impact on the other bus devices. Freescale Semiconductor, Inc... In Initialization Mode, the MSCAN is stopped. However, interface registers can still be accessed.
PAGE 552
Freescale Semiconductor, Inc. MSCAN MSCAN Power Down Mode The MSCAN is in Power Down Mode when Table 94 • the CPU is in Stop Mode or • the CPU is in Wait Mode and the CSWAI bit is set. Freescale Semiconductor, Inc... When entering the Power Down Mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations.
PAGE 553
Freescale Semiconductor, Inc. MSCAN Interrupt Operation Interrupt Operation Freescale Semiconductor, Inc... The MSCAN supports four interrupt vectors mapped onto eight different interrupt sources, any of which can be individually masked (for details see sections MSCAN Receiver Flag Register (CANRFLG) to MSCAN Transmitter Interrupt Enable Register (CANTIER)): • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission.
PAGE 554
Freescale Semiconductor, Inc. MSCAN Interrupt Acknowledge Freescale Semiconductor, Inc... CAUTION: Interrupt Sources NOTE: Interrupts are directly associated with one or more status flags in either the MSCAN Receiver Flag Register (CANRFLG) or the MSCAN Transmitter Flag Register (CANTFLG). Interrupts are pending as long as one of the corresponding flags is set. The flags in the above registers must be reset within the interrupt handler to handshake the interrupt.
PAGE 555
Freescale Semiconductor, Inc. Analog to Digital Converter Analog to Digital Converter Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 556
Freescale Semiconductor, Inc. Analog to Digital Converter Freescale Semiconductor, Inc... Features • 8/10 Bit Resolution. • 7 µsec, 10-Bit Single Conversion Time. • Sample Buffer Amplifier. • Programmable Sample Time. • Left/Right Justified, Signed/Unsigned Result Data. • External Trigger Control. • Conversion Completion Interrupt Generation. • Analog Input Multiplexer for 8 Analog Input Channels. • Analog/Digital Input Pin Multiplexing. • 1 to 8 Conversion Sequence Lengths.
PAGE 557
Freescale Semiconductor, Inc. Analog to Digital Converter Block Diagram Block Diagram Ctl Ctl MUX Timing Gen. MUX PORT PINS SAMPLE AMP MUX Sample S/H State Machine MUX Ctl Existing Approx. Freescale Semiconductor, Inc...
PAGE 558
Freescale Semiconductor, Inc. Analog to Digital Converter Functional Block Diagram The block diagram in Figure 108illustrates the functional structure of the A/D module. The functionality is divided into three submodules as denoted by the dashed lines on the figure. These are the IP Bus Interface, the Conversion Mode Control/Register File, and the Custom Analog. Freescale Semiconductor, Inc... The IP Bus Interface connects the module to the bus.
PAGE 559
Freescale Semiconductor, Inc. Analog to Digital Converter Register Map Register Map Add $00 $01 Freescale Semiconductor, Inc...
PAGE 560
Freescale Semiconductor, Inc. Analog to Digital Converter Add $13 $14 $15 $16 Freescale Semiconductor, Inc...
PAGE 561
Freescale Semiconductor, Inc. Analog to Digital Converter Functional Description Functional Description Please refer to the functional block diagram Figure 108 in reference to the functional description of the ATD module Freescale Semiconductor, Inc... Custom Analog Sample and Hold Submodule The Sample and Hold (S/H) Machine accepts analog signals from the external world and stores them as capacitor charge on a storage node in the module.
PAGE 562
Freescale Semiconductor, Inc. Analog to Digital Converter Freescale Semiconductor, Inc... The analog input multiplexer includes negative stress protection circuitry which prevents crosstalk between channels when the applied input potentials are within specification. Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential.
PAGE 563
Freescale Semiconductor, Inc. Analog to Digital Converter Functional Description When not sampling, the analog-to-digital submodule disables its own clocks at the input into this submodule. The analog electronics still draws quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Freescale Semiconductor, Inc...
PAGE 564
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Analog to Digital Converter A/D State Machine and SAR (Successive Approximation Register) The A/D state machine controls the conversion process in the A/D converter. The machine needs to know when a sample period is occurring since the sample storage node is located on the CDAC capacitor array. The machine works closely with the SAR to perform a binary search algorithm.
PAGE 565
Freescale Semiconductor, Inc. Analog to Digital Converter Functional Description reference potentials to set the sampled signal level within itself without relying on the sample machine to deliver them. Freescale Semiconductor, Inc... Mode Control organizes the conversion sequences, specifies the input sample channel, implements the external trigger mode, and move digital output data from the SAR to the result registers.
PAGE 566
Freescale Semiconductor, Inc. Analog to Digital Converter Freescale Semiconductor, Inc... Table 96 External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description X X 0 0 Ignores external trigger. Performs one conversion sequence and stops. X X 0 1 Ignores external trigger. Performs continuous conversion sequences. 0 0 1 X Falling edge triggered. Performs one conversion sequence per trigger. 0 1 1 X Rising edge triggered. Performs one conversion sequence per trigger.
PAGE 567
Freescale Semiconductor, Inc. Analog to Digital Converter Functional Description Freescale Semiconductor, Inc... The external trigger input is enabled by the ETRIGE, ETRIGP, ETRIGLE control bits in ATDCTL2. When ETRIGE is first enabled, a conversion sequence is initiated by an external event transitioning the ETRIG pin. Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally.
PAGE 568
Freescale Semiconductor, Inc. Analog to Digital Converter the input pins at the digital sampling time that don’t meet the VIL or VIH specification will return unknown digital values. A read of the PORTAD1 may affect the accuracy of an in progress sample period but will not affect an in progress A/D conversion. Freescale Semiconductor, Inc... There is a digital, 8-bit, input-only port associated with the ATD. It is accessed through the 8-bit Port Data Register (PORTAD1).
PAGE 569
Freescale Semiconductor, Inc. Analog to Digital Converter Functional Description PR0–PR4 ATD Module Clock Modulus Counter DIVIDE BY 2 ATD Conversion CLOCK Freescale Semiconductor, Inc... Figure 109 ATD Clock Select/Prescale. Power Down Mode The ATD module can be powered down under program control. This is done by turning the clock signals off to the digital electronics of the module and eliminating the quiescent current draw of the analog electronics.
PAGE 570
Freescale Semiconductor, Inc. Analog to Digital Converter Freescale Semiconductor, Inc... Background Debug (ATD FREEZE) Mode When debugging an application, it is useful to have the ATD pause when a breakpoint is encountered. To accommodate this, there are two FREEZE bits in the ATDCTL3 register used to select one of three responses: First, the ATD module may ignore the background signal.
PAGE 571
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Analog to Digital Converter Functional Description Note that when the module powers up via the ipg_wait signal that the ATD is not reset; ATD operation proceeds as it was prior to entering the wait. Freezing the module does not cause it to be reset. If a freeze mode is entered and defines that the current conversion be terminated, then this is done and the module will be idle after exiting the freeze state, but the module is not initialized.
PAGE 572
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions Freescale Semiconductor, Inc... Register Arrangement and IP Address Mapping The base address of the module is hardware programmable. The ATD register map is fixed and begins at the module’s base address. Figure 111 summarizes the ATD module’s address space. The following subsections describe the bit-level arrangement and functionality of each register. The ATD module is clocked by the ATD module clock.
PAGE 573
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
PAGE 574
Freescale Semiconductor, Inc. Analog to Digital Converter ATD Control Register 2 & 3 (ATDCTL2, ATDCTL3) The ATD control register 2 & 3 are used to select the power up mode, fast flag clear mode, wait mode, 1 to 8 channel mode, interrupt control, and freeze control. Writes to these registers will not abort current conversion sequence nor start a new sequence. Freescale Semiconductor, Inc...
PAGE 575
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions Freescale Semiconductor, Inc... conversion sequence is begun by writing to control register ATDCTL4/5. In application where the ATD module is being polled to determine if an ATD conversion is complete, this feature provides a convenient way of clearing the status register conversion complete flag.
PAGE 576
Freescale Semiconductor, Inc. Analog to Digital Converter External trigger mode allows the user to synchronize sample and ATD conversions processes with external events. Freescale Semiconductor, Inc... External Gated Continuous-Scan Mode is defined when the SCAN and ETRIGLE bits are set. It allows the user to synchronize the conversion process with external events and control the number of conversion performed in sequence.
PAGE 577
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions The sequence complete interrupt flag. This flag is not cleared until the interrupt is serviced (by reading the result data in such a way that the conversion complete flag is cleared), a new conversion sequence is initiated, or the module is reset. This bit is not writable in any mode. S8C/S4C/S2C/S1C — Conversion Sequence Length Freescale Semiconductor, Inc...
PAGE 578
Freescale Semiconductor, Inc. Analog to Digital Converter Freescale Semiconductor, Inc... The result register assignments made to a conversion sequence follow a few simple rules. Normally, the first result is placed in the first register; the second result is placed in the second register, and so on. Table 99 presents the result register assignments for the various conversion lengths that are normally made. If FIFO mode is used, the result register assignments differ.
PAGE 579
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions Freescale Semiconductor, Inc... conversion counter value in ATDSTAT0 can be used to determine where in the result register file, the next conversion result will be placed. The results register counter is initialized to zero on three events: on reset, the beginning of a normal (non-FIFO) conversion sequence, and the end of a normal (non-FIFO) conversion sequence.
PAGE 580
Freescale Semiconductor, Inc. Analog to Digital Converter ATD Control Register 4 (ATDCTL4) ATD control register 4 is used to select the ATD conversion clock frequency (based on the ATD module clock), select the length of the third phase of the sample period, and set the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). All writes to this register have an immediate effect. If a conversion is in progress, the entire conversion sequence is aborted. Freescale Semiconductor, Inc...
PAGE 581
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions Freescale Semiconductor, Inc... external analog signal directly to the storage node for final charging and high accuracy. Table 101 lists the lengths available for the third sample phase.
PAGE 582
Freescale Semiconductor, Inc.
PAGE 583
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions sequence is aborted. A write to this register (or ATDCTL4) initiates a new conversion sequence. Address Offset: $0005 Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 DJM DSGN SCAN MULT 0 CC CB CA 0 0 0 0 0 0 0 0 DJM — Result Register Data Justification Mode 1 = Right justified mode. 0 = Left justified mode.
PAGE 584
Freescale Semiconductor, Inc. Analog to Digital Converter Table 104 illustrates the difference between the signed and unsigned, left justified output codes for an input signal range between 0 and 5.1 Volts. Freescale Semiconductor, Inc... Table 103 Result Data Formats Available.
PAGE 585
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions Freescale Semiconductor, Inc... If this control bit is 1, a single conversion sequence initiation will result in continuously executed conversion sequence. When a conversion sequence completes, the sequence complete flag (SCF) is set and a new sequence is immediately begun. The conversion mode characteristics of each sequence are identical.
PAGE 586
Freescale Semiconductor, Inc. Analog to Digital Converter Freescale Semiconductor, Inc... Table 105 Analog Input Channel Select Coding A/D Status Register (ATDSTAT) CC CB CA Analog Input Channel 0 0 0 AD0 0 0 1 AD1 0 1 0 AD2 0 1 1 AD3 1 0 0 AD4 1 0 1 AD5 1 1 0 AD6 1 1 1 AD7 The ATD Status registers contain the conversion complete flags and the conversion sequence counter. The status registers are normally read-only.
PAGE 587
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions ETORF — External Trigger Overrun Flag While in edge trigger mode, if additional active edges are detected while a conversion sequence is in process the overrun flag is set. 1 = External trigger overrun error has occurred 0 = No External trigger overrun error has occurred Freescale Semiconductor, Inc... FIFOR — FIFO Over Run Flag.
PAGE 588
Freescale Semiconductor, Inc. Analog to Digital Converter Freescale Semiconductor, Inc... cleared during a subsequent access to the result register. This provides a convenient method for clearing the conversion complete flag when the user is polling the ATD module; it ensures the user is signaled as to the availability of new data and avoids having to have the user clear the flag explicitly.
PAGE 589
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions ATD TEST Module Test Register (ATDTEST) The test registers implement various special (test) modes used to test the ATD module. The reset bit in ATDTEST1 is always read/write. The SAR (successive approximation register) can always be read but only written in special (test) mode. Freescale Semiconductor, Inc... When writing to the SAR in special (test) mode, it is advised to use 16 bit write.
PAGE 590
Freescale Semiconductor, Inc. Analog to Digital Converter Resetting to idle mode defines the only exception of the reset control bit condition to the general (bus) reset condition. The reset control bit does not initialize the ADPU bit to its reset condition and therefore does not power down the module. This exception allows the module to remain active for other test operations. Freescale Semiconductor, Inc...
PAGE 591
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions ATD Input Enable Mask Register (ATDDIEN) Address Offset: $000D Freescale Semiconductor, Inc... Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 This register is added for controlling the PORTAD1.
PAGE 592
Freescale Semiconductor, Inc. Analog to Digital Converter Port Data Register (PORTAD1) The input data port associated with the ATD module is input-only. The port pins are shared with the analog A/D inputs. Address Offset: $000F Freescale Semiconductor, Inc...
PAGE 593
Freescale Semiconductor, Inc. Analog to Digital Converter Register Descriptions ATDDRx A/D Conversion Result Registers (ATDDR0Ð15) Left Justified Result Data Freescale Semiconductor, Inc...
PAGE 594
Freescale Semiconductor, Inc. Analog to Digital Converter this selection is made using the DSGN control bit in ATDCTL2. Note that the signed data is stored in 2s complement format. Note that signed data only exists in left justified format so that no sign extension hardware is required. Signed data selected for right justified format is ignored. Freescale Semiconductor, Inc...
PAGE 595
Freescale Semiconductor, Inc. Analog to Digital Converter External Pin Descriptions External Pin Descriptions Freescale Semiconductor, Inc... The basic ATD requires a total of 12 pins to implement the 8 input channel A/D converter. The pins fall into four categories: channel input pins (one of the channel input pins is muxed with the ETRIG input), reference potential pins (VRL and VRH), and analog supply potential pins (VDDA and VSSA). These pins are described below.
PAGE 596
Freescale Semiconductor, Inc. Analog to Digital Converter Analog Reference Pins These two pins serve as the source for the high (VRH) and low (VRL) reference potentials for the converter. Freescale Semiconductor, Inc... Separation from the power supply pins accommodates the filtering necessary to achieve the accuracy of which the system is capable. Dedicated Analog Supply Pins These two pins are used to supply power (VDDA and VSSA) to the analog section of the chip.
PAGE 597
Freescale Semiconductor, Inc. Analog to Digital Converter Modes of Operation Freescale Semiconductor, Inc... Modes of Operation Analog to digital conversions in this module are performed in sequences. There are a variety of different sequences that are programmable; these different sequences are referred to as conversion modes1.
PAGE 598
Freescale Semiconductor, Inc. Analog to Digital Converter determine when the result registers have been filled. The SCF bit is set after the completion of each sequence. The CCF bit associated with each result register is set when that register is loaded with result data. Freescale Semiconductor, Inc...
PAGE 599
Freescale Semiconductor, Inc. Analog to Digital Converter Sample Conversion clocks are disabled to most of the module and the analog quiescent current draw is turned off; this places the module into its power down state. This mode is equivalent to clearing the ADPU control bit in ATDCTL2. The module is released from STOP mode when the ipg_stop signal is released. Freescale Semiconductor, Inc... In this mode, the MCU still has access to the control, status, and result registers.
PAGE 600
Freescale Semiconductor, Inc. Analog to Digital Converter ATD Clocks Freescale Semiconductor, Inc... 1 cycle Initial Program- Sample able Period Sample Period 1 1 1 1 1 1 1 1 1 cycle cycle cycle cycle cycle cycle cycle cycle cycle Successive Approximation Sequence (Resolution Period) CCF Flag set here and sequence ends if in the 8-channel mode Figure 112 ATD Sample/Conversion Timing – 10 bit conversion, 2 cycle programmable sample period MC9S12DP256 — Revision 1.
PAGE 601
Freescale Semiconductor, Inc. Analog to Digital Converter Sample Conversion C B +10 mV (2 counts) 10 bit absolute error boundary Freescale Semiconductor, Inc... A 9 8 7 6 5 C Ideal transfer curve B 4 3 2 A 10 bit transfer curve 1 0 -10 mV (2 counts) 10 bit absolute error boundary 20 40 60 Figure 113 ATD Accuracy Definitions NOTES Example: 1) Input in milliVolts, VREFH-VREFL = 5.120 Volts 2) one 10-Bit count = 5 mV. 3) A = inherent 10-Bit quantization error OF 2.
PAGE 602
Freescale Semiconductor, Inc. Analog to Digital Converter General Purpose Input Ports Freescale Semiconductor, Inc... The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external input data that can be accessed through the digital port registers. Each digital input is individually enabled by each bit of the register ATDDIEN.
PAGE 603
Freescale Semiconductor, Inc. Byte Data Link Controller Module Byte Data Link Controller Module Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 Register Map. . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Byte Data Link “SAE Standard J1850 Class B Data Communications Network Interface” prior to proceeding with this specification. The BDLC module is designed in a modular structure for use as an IP block. Freescale Semiconductor, Inc... Features Features of the BDLC module include the following: • SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low-Speed (≤125 Kbps) Serial Data Communications in Automotive Applications • 10.
PAGE 605
Freescale Semiconductor, Inc. Byte Data Link Controller Module Block Diagram Block Diagram To J1850 Bus Physical Interface Port Integration Module Freescale Semiconductor, Inc... MUX Interface Protocol Handler Rx/Tx Buffers BDLC Core IP Bus Interface BDLC To IP Bus Figure 114 BDLC Block Diagram Figure 107 shows the organization of the BDLC module. The IP Bus Interface provides the link between the IP Bus and the Buffers.
PAGE 606
Freescale Semiconductor, Inc.
PAGE 607
Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description Functional Description Mux Interface The MUX Interface is responsible for bit encoding/decoding and digital noise filtering between the Protocol Handler and the Physical Interface. Freescale Semiconductor, Inc...
PAGE 608
Freescale Semiconductor, Inc. Byte Data Link Input Sync Freescale Semiconductor, Inc... Rx Data from RxP pad 4-Bit Up/Down Counter 4 d q up/down out Edge & Count Comparator Filtered Rx Data Out d q MUX Interface Clock Figure 116 BDLC Rx Digital Filter Block Diagram Operation The clock for the digital filter is provided by the MUX Interface clock.At each positive edge of the clock signal, the current state of the Receiver input signal from the RxP pad is sampled.
PAGE 609
Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description The Data Latch will retain its value until the counter next reaches the opposite end point, signifying a definite transition of the RxP signal. Performance The performance of the digital filter is best described in the time domain rather than the frequency domain. Freescale Semiconductor, Inc...
PAGE 610
Freescale Semiconductor, Inc. Byte Data Link SOF Priority (Data0) Message ID (Data1) Datan CRC IFR EOF IFS Idle EOD Optional Idle Figure 117 J1850 Bus Message Format (VPW) Freescale Semiconductor, Inc... SAE J1850 states that each message has a maximum length of 101 bit times or 12 bytes (excluding SOF, EOD, NB and EOF). SOF – Start of Frame Symbol All messages transmitted onto the J1850 bus must begin with an long active SOF symbol.
PAGE 611
Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description becomes the 8-bit CRC byte, which is appended to the message after the data bytes, in MSB to LSB order. Freescale Semiconductor, Inc... When receiving a message, the BDLC uses the same divisor polynomial. All data bytes, excluding the SOF and EOD symbols, but including the CRC byte, are used to check the CRC.
PAGE 612
Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... A rising edge may occur during the IFS period because of varying clock tolerances and loading of the J1850 bus, causing different nodes to observe the completion of the IFS period at different times. Receivers must synchronize to any SOF occurring during an IFS period to allow for individual clock tolerances.
PAGE 613
Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description Active 128µs OR 64µs OR 64µs Passive Logic “0” (a) Active Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link Logic “1” A logic one is defined as either an active to passive transition followed by a passive period 128µs in length, or a passive to active transition followed by an active period 64µs in length (Figure 118(b)). NB – Normalization Bit The NB symbol has the same property as a logic “1” or a logic “0”.It is only used in IFR message responses.
PAGE 615
Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description (tbdlc) an apparent separation in these maximum time/minimum time concurrences equal to one cycle of tbdlc occurs. Freescale Semiconductor, Inc... This one clock resolution allows the BDLC to properly differentiate between the different bits and symbols, without reducing the valid window for receiving bits and symbols from transmitters onto the J1850 bus having varying oscillator frequencies.
PAGE 616
Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... integer bus frequencies (CLKS = 0) and binary bus frequencies (CLKS = 1), respectively. The values specified in the tables are for the symbols appearing on the SAE J1850 bus. These values assume the BDLC is communicating on the SAE J1850 bus using an external analog transceiver, and that the BDLC analog roundtrip delay value programed into the DLCBARD register is the appropriate value for the transceiver being used.
PAGE 617
Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description . Table 109 BDLC Transmitter VPW Symbol Timing for Binary Frequencies Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Table 111 BDLC Receiver VPW Symbol Timing for Binary Frequencies Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description Table 112 BDLC Receiver VPW 4X Symbol Timing for Integer Frequencies Freescale Semiconductor, Inc... Number Characteristic Symbol1 Min Typ Max Unit 7 End of Frame (EOF) Trv4 60 70 74 tbdlc 8 Inter-Frame Separator (IFS) Trv5 75 --- --- tbdlc 9 Break Signal (BREAK) Trv6 60 --- --- tbdlc NOTE: 1.
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Freescale Semiconductor, Inc. Byte Data Link Invalid Passive Bit If the passive to active transition beginning the next data bit or symbol occurs between the active to passive transition beginning the current data bit or symbol and Trvp1(Min), the current bit would be invalid. See Figure 119(1). 200µs 128µs Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description Valid EOD Symbol If the passive to active transition beginning the next data bit or symbol occurs between Trvp3(Min) and Trvp3(Max), the current symbol would be considered a valid EOD symbol.See Figure 119(4). 300µs Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link 200µs 128µs 64µs Active (1) Invalid Active Bit Passive Active Trva2(Min) Freescale Semiconductor, Inc...
PAGE 623
Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description 240µs Active (2) Valid BREAK Symbol Passive Trv6(Min) Freescale Semiconductor, Inc... Figure 122 J1850 VPW BREAK Symbol Valid BREAK Symbol If the next active to passive transition does not occur until after Trv6(Min), the current symbol will be considered a valid BREAK symbol. A BREAK symbol should be followed by a SOF symbol beginning the next message to be transmitted onto the J1850 bus. See Figure 122.
PAGE 624
Freescale Semiconductor, Inc. Byte Data Link “0” “1” “1” “0” “1” “1” “1” Transmitter A detects an active state on the bus, and stops transmitting Active Transmitter A Passive “0” “0” Freescale Semiconductor, Inc...
PAGE 625
Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description Protocol Handler The Protocol Handler is responsible for framing, collision detection, arbitration, CRC generation/checking, and error detection. The Protocol Handler conforms to SAE J1850 – Class B Data Communications Network Interface. To J1850 Bus Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link To Pad Drivers TxP RxP BDLC TxP DIGITAL FILTER IN Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description Freescale Semiconductor, Inc... Rx & Tx Shadow Registers Immediately after the Rx Shift Register has completed shifting in a byte of data, this data is transferred to the Rx Shadow Register and RDRF or RXIFR is set and interrupt is generated if the interrupt enable bit (IE) in BCR1 is set.
PAGE 628
Freescale Semiconductor, Inc. Byte Data Link contains an indefinite number of data bytes. All of the other features of the frame remain the same, including the SOF, CRC, and EOD symbols. Freescale Semiconductor, Inc... Another node wishing to send a Block Mode transmission must first inform all other nodes on the network that this is about to happen. This is usually accomplished by sending a special predefined message.
PAGE 629
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link Controller Module Functional Description Symbol Error A symbol error is detected when an abnormal (invalid) symbol is detected in a message being received from the J1850 bus. See sections Invalid Passive Bit and Invalid Active Bit which define invalid symbols.The symbol invalid or out of range flag (in DLCBSVR) is set when a symbol error is detected.
PAGE 630
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link short to ground would not allow the bus to be driven to the active (dominant) state. The BDLC will wait for assertion of the receive pin for (64 - analog round trip delay) tbdlc cycles, after assertion of the transmit pin, before detecting the error. If the transmission is an IFR, the BDLC will wait for (280 - analog round trip delay) tbdlc cycles before detecting an error.
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Functional Description Table 114 BDLC J1850 Error Summary Freescale Semiconductor, Inc... Error Condition BDLC Function Transmission Error BDLC will immediately cease transmitting. Further transmission and reception will be disabled until a valid EOF symbol is detected. The symbol invalid or out of range flag will be set and interrupt generated if enabled.
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Freescale Semiconductor, Inc. Byte Data Link IP Bus Interface To J1850 Bus Physical Interface Port Integration Module Freescale Semiconductor, Inc... MUX Interface Protocol Handler Rx/Tx Buffers BDLC Core IP Bus Interface BDLC To IP Bus Figure 126 BDLC Block Diagram - IP Bus Interface The IP Bus Interface provides the interface between the IP Bus and the rest of the BDLC. The address space of the BDLC is continuous, consisting of 8 bytes starting at the base address.
PAGE 633
Freescale Semiconductor, Inc. Byte Data Link Controller Module Register Descriptions Register Descriptions NOTE: Freescale Semiconductor, Inc... BDLC Control Register 1 (DLCBCR1) All bits of all registers in this module are completely synchronous to internal clocks during a register read. This register is used to configure and control the BDLC.
PAGE 634
Freescale Semiconductor, Inc. Byte Data Link 0 = Enable DLCBSVR Updates. This bit is automatically cleared by the reception of a SOF symbol or a BREAK symbol. It will then allow updates of the state vector register to occur. Freescale Semiconductor, Inc... There are two situations in which interrupts will not be masked by the IMSG bit: when a wakeup interrupt occurs; and when a receiver error occurs which causes a byte pending transmission to be flushed from the transmit shadow register.
PAGE 635
Freescale Semiconductor, Inc. Byte Data Link Controller Module Register Descriptions If the programmer does not wish to use the interrupt capability of the BDLC, the BDLC State Vector Register (DLCBSVR) can be polled periodically by the programmer to determine BDLC states. Refer to BDLC State Vector Register (DLCBSVR) for a description of DLCBSVR register and how to clear interrupt requests. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Register Descriptions JMP END SERVE8 Service condition #8 Freescale Semiconductor, Inc... Note that the NOPs are just used to align the JMPs onto 4-byte boundaries so that the value in the DLCBSVR may be used intact. Each of the service routines must end with an ‘RTI’ instruction to guarantee correct continued operation of the device. Note also that the first entry can be omitted since it corresponds to no interrupt occurring.
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Freescale Semiconductor, Inc. Byte Data Link 0 = Clearing SMRST after it has been set will cause the generation of a state machine reset.After SMRST is cleared, the BDLC requires the bus to be idle for a minimum of an End of Frame symbol (EOF) time before allowing the reception of a message. The BDLC requires the bus to be idle for a minimum of an Inter-Frame Separator symbol (IFS) time before allowing any message to be transmitted. DLOOP — Digital Loopback Mode (Bit 6) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Register Descriptions Freescale Semiconductor, Inc... RX4XE — Receive 4X Enable (Bit 5) This bit determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature is useful for fast download of data into a J1850 node for diagnostic or factory programming of the node. 1 = When set, the BDLC is put in 4X (41.6 kbps) receive only operation.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link Shadow Register have been transmitted. Once TEOD is set, the transmit data register empty flag (TDRE) in the BDLC State Vector Register (DLCBSVR) is cleared to allow lower priority interrupts to occur. This bit is also used to end an IFR. Bits TSIFR, TMIFR1, and TMIFR0 determine whether a CRC byte is appended before EOD transmission for IFRs. 1 = Transmit EOD symbol.
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Freescale Semiconductor, Inc. The BDLC supports the In-frame Response (IFR) feature of J1850 by setting these bits correctly. The four types of J1850 IFR are shown in Types of In-Frame Response. The purpose of the in-frame response modes is to allow single or multiple nodes to acknowledge receipt of the data by responding to a received message after they have seen the EOD symbol.
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Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... 0 = The TSIFR bit will be automatically cleared once the EOD following one or more IFR bytes has been received or an error is detected on the bus. The user must set the TSIFR bit before the EOF following the main part of the message frame is received, or no IFR transmit attempts will be made for the current message.
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Register Descriptions Freescale Semiconductor, Inc... 0 = The TMIFR1 bit will be automatically cleared once the BDLC has successfully transmitted the CRC byte and EOD symbol, by the detection of an error on the multiplex bus, a transmitter underrun, or loss of arbitration.
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Freescale Semiconductor, Inc. Byte Data Link If a loss of arbitration occurs when the BDLC is transmitting a multiple byte IFR with CRC, the BDLC will go to the loss of arbitration state, set the appropriate flag and cease transmission. The TMIFR1 bit will be cleared and no attempt will be made to retransmit the byte in the DLCBDR. If loss of arbitration occurs in the last bit of the IFR byte, two additional one bits (a passive long followed by an active short) will be sent out.
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Register Descriptions However, if the programmer wishes to transmit a single byte, the programmer should load the byte into the DLCBDR and then set the TMIFR0 bit before the EOD symbol has been received. Once the TDRE flag is set and interrupt occurs (if enabled), the programmer should then set the TEOD bit in DLCBCR2. This will result in the byte in the DLCBDR being the only byte transmitted. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link BDLC Data Register (DLCBDR) This register is used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC. It is also used to pass data received from the J1850 bus to the CPU. Address Offset: $0003 Read: Write: Freescale Semiconductor, Inc...
PAGE 647
Freescale Semiconductor, Inc. Byte Data Link Controller Module Register Descriptions Freescale Semiconductor, Inc... If the user writes the first byte of a message to be transmitted to the DLCBDR and then determines that a different message should be transmitted, the user can write a new byte to the DLCBDR up until the transmission begins.This new byte will replace the original byte in the DLCBDR.
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Freescale Semiconductor, Inc. Byte Data Link BDLC Analog Round Trip Delay Register (DLCBARD) This register is used to program the BDLC so that it compensates for the round trip delays of different external transceivers. Also the polarity of the receive pin (RxP) is set in this register. Address Offset: $0004 Bit 7 Read: 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Register Descriptions the expected rountrip delay through both the transmitter and the receiver. The sum of these two delays makes up the total roundtrip delay value. Freescale Semiconductor, Inc... Table 117 BARD Values vs.
PAGE 650
Freescale Semiconductor, Inc. Byte Data Link BDLC Rate Select Register (DLCBRSR) This register determines the divider prescaler value for the mux interface clock (fbdlc). Address Offset: $0005 Bit 7 6 Read: 0 0 Write: Unimplemented Reset: 0 0 5 4 3 2 1 Bit 0 R5 R4 R3 R2 R1 R0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Unimplemented READ: any time WRITE: write once in normal and emulation modes. Register functionality modified in special test mode.
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Register Descriptions NOTE: The BRSR is always loaded with “desired divisor” -1 and comes out of reset programmed for a divide by 1 clock rate (BRSR = $00). Freescale Semiconductor, Inc... Table 118 BDLC Rate Selection for Binary Frequencies IP bus clock frequency R[5:0] division fbdlc fCLOCK=1.048576 MHz $00 1 1.048576 MHz fCLOCK=2.09715 MHz $01 2 1.048576 MHz fCLOCK=3.14573 MHz $02 3 1.048576 MHz fCLOCK=4.
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Freescale Semiconductor, Inc. Byte Data Link BDLC Control Register (DLCSCR) The following register enables the BLDC_IP. Address Offset: $0006 Read: Bit 7 6 5 0 0 0 0 0 0 Write: Reset: 4 BDLCE 0 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... = Unimplemented READ: any time WRITE: any time BDLCE — BDLC Enable (Bit 4) This bit serves as a mux interface clock (fbdlc) enable/disable for power savings.
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Freescale Semiconductor, Inc. Byte Data Link Controller Module External Pin Descriptions Register functionality is modified in special test mode. IDLE Idle (Bit 0) This bit indicates when the BDLC is idle. 1 = BDLC has received IFS and no data is being transmitted or received. 0 = BDLC is either transmitting or receiving data. Freescale Semiconductor, Inc... NOTE: BDLC is only idle after receiving IFS. The IDLE bit is 0 during reset since the BDLC needs to wait for an IFS before becoming idle.
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Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... entail change of state indications in the DLCBSVR which must be dealt with. Once this is complete, CPU interrupts can be enabled (if desired), and then the BDLC module is capable of SAE J1850 serial network communication. For an illustration of the sequence necessary for initializing the BDLC, refer to Figure 128.
PAGE 655
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link Controller Module Reset Initialization/Basic Operation Step 4- Initialize DLCBCR1 The next step in BDLC initialization is to write the configuration bits in DLCBCR1. The CLKS bit should be written to its desired values at this time, following which it will become read-only. The IE bit should be written as a logic zero at this time so BDLC interrupts of the CPU will remain masked for the time being.
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Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... Step 7- Clear Pending BDLC Interrupts In order to ensure that the BDLC does not immediately generate a CPU interrupt when interrupts are enabled, the user should read the DLCBSVR to determine if any BDLC interrupt sources are pending before setting the IE bit in the BCR1. If the BSVR reads as a%00000000, no interrupts are pending and the user is free to enable BDLC interrupts, if desired.
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Reset Initialization/Basic Operation BDLC enters Run mode from Reset mode Write desired config. data into DLCBARD Freescale Semiconductor, Inc... Write desired divisor - 1 into DLCBRSR Write desired config. data into DLCBCR2 Write desired config.
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Freescale Semiconductor, Inc. Byte Data Link Transmitting A Message Freescale Semiconductor, Inc... The design of the BDLC module enables the user to easily handle message reception and message transmission separately. This can greatly simplify the communication software, as all received messages can be handled virtually the same, regardless of their origin.
PAGE 659
Freescale Semiconductor, Inc. Byte Data Link Controller Module Transmitting A Message DLCBDR by the CPU. For an illustration of the DLCBDR, refer to BDLC Data Register (DLCBDR). Freescale Semiconductor, Inc... Transmitting a Message with the BDLC NOTE: Step 1: Write the First Byte into the DLCBDR To transmit a message using the BDLC, the user just writes the first byte of the message to be transmitted into the DLCBDR, initiating the transmission process.
PAGE 660
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link Step 2: When TDRE is Indicated, Write the Next Byte into the DLCBDR When a TDRE state is reflected in the BSVR, the CPU writes the next byte to be transmitted into the BDR. This step is repeated until the last byte to be transmitted is written to the DLCBDR.
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Transmitting A Message network. For the transmit routine, either of these events can be dealt with in a similar manner. Freescale Semiconductor, Inc... Loss of Arbitration If a loss of arbitration (LOA) occurs while the BDLC is transmitting onto the SAE J1850 bus, the BDLC will immediately stop transmitting, and a LOA status will be reflected in the DLCBSVR.
PAGE 662
Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... error which will be indicated in the DLCBSVR. As with the other errors, it is up to the user’s software to determine if another transmission attempt should be made. In-Frame Response to a Transmitted Message If an In-Frame Response (IFR) is received following the transmission of a message, the status indicating that an IFR byte has been received will be indicated in the DLCBSVR before an EOF is indicated.
PAGE 663
Freescale Semiconductor, Inc. Byte Data Link Controller Module Transmitting A Message Enter BDLC Transmit Routine C A Write first message byte to be transmitted into DLCBDR Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Receiving A Message Freescale Semiconductor, Inc... The design of the BDLC makes it especially easy to use for receiving messages off of the SAE J1850 bus. When the first byte of a message comes in, the DLCBSVR will indicate to the CPU that a byte has been received. As each successive byte is received, that will in turn be reflected in the DLCBSVR.
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Receiving A Message Receiving a Message with the BDLC Receiving a message using the BDLC is extremely straight-forward. As each byte of a message is received and placed into the DLCBDR, the BDLC will indicate this to the CPU with an Rx Data Register Full (RDRF) status in the DLCBSVR. When an EOF symbol is received, indicating to the CPU that the message is complete, this too will be reflected in the DLCBSVR. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Byte Data Link Once the EOF state is reflected in the DLCBSVR, this indicates to the user that the message is complete, and that when another byte is received it is the first byte of a new message. Freescale Semiconductor, Inc... Filtering Received Messages No message filtering hardware is included on the BDLC, so all message filtering functions must be performed in software.
PAGE 667
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link Controller Module Receiving A Message CRC Error If a CRC error is detected during a message reception, this will be reflected in the BSVR once an EOD time is recognized by the BDLC. Since all bytes of the message will have been received when this error is detected, it is up to the user to ensure that all the received message bytes are discarded.
PAGE 668
Freescale Semiconductor, Inc. Byte Data Link Enter BDLC Receive Routine Is DLCBSVR = $1C/$18? (Error Detected) Yes Go to BDLC BREAK/Error Handling Routine B Freescale Semiconductor, Inc...
PAGE 669
Freescale Semiconductor, Inc. Byte Data Link Controller Module Transmitting An In-Frame Response (IFR) Transmitting An In-Frame Response (IFR) Freescale Semiconductor, Inc... The BDLC can be used to transmit all four types of In-Frame Response (IFR) which are defined in SAE J1850. A very brief definition of each IFR type is given below. For a more detailed description of each, refer the SAE J1850 document.
PAGE 670
Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... receivers for a message but the transmitter only wants to know that at least one node received it. In this case, all receivers will begin transmitting their node ID following the EOD. Since all nodes on an SAE J1850 network have a unique node ID, if multiple nodes begin transmitting their node ID simultaneously, arbitration takes place.
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Freescale Semiconductor, Inc. Byte Data Link Controller Module Transmitting An In-Frame Response (IFR) initial portion of the message, and the intended receiver responds by transmitting the desired data in an IFR. In most cases, the original message requiring a Type 3 IFR is addressed to one particular node, so no arbitration should take place during the IFR portion of the message. Freescale Semiconductor, Inc...
PAGE 672
Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... Transmit Single Byte IFR The Transmit Single Byte IFR (TSIFR) bit in DLCBCR2 is used to transmit Type 1 and Type 2 IFRs onto the SAE J1850 bus. If this bit is set after a byte is loaded into the BDR, the BDLC will attempt to send that byte, preceded by the appropriate Normalization Bit, as a single byte IFR without a CRC.
PAGE 673
Freescale Semiconductor, Inc. Byte Data Link Controller Module Transmitting An In-Frame Response (IFR) timely manner. If a loss of arbitration occurs while the Type 3 IFR is being transmitted, transmission will halt immediately and the loss of arbitration will be indicated in the DLCBSVR. Freescale Semiconductor, Inc... Transmit Multi-Byte IFR 0 The Transmit Multi-Byte IFR 0 (TMIFR0) bit is used to transmit an SAE J1850 Type 3 IFR without a CRC byte appended.
PAGE 674
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link Transmitting a Type 1 IFR To transmit a Type 1 IFR, the user loads the byte to be transmitted into the DLCBDR and sets both the TSIFR bit and the TEOD bit. This will direct the BDLC to attempt transmitting the byte written to the DLCBDR one time, preceded by the appropriate Normalization Bit. If the transmission is not successful, the byte will be discarded and no further transmission attempts will be made.
PAGE 675
Freescale Semiconductor, Inc. Byte Data Link Controller Module Transmitting An In-Frame Response (IFR) Enter Type 1 IFR Transmit Routine Freescale Semiconductor, Inc...
PAGE 676
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link Step 2: Set the TSIFR Bit The second step necessary for transmitting a Type 2 IFR is to set the TSIFR bit in DLCBCR2. Setting this bit will direct the BDLC to attempt to transmit the byte in the DLCBDR as an IFR until it is successful. If the byte is transmitted successfully, or if an error or loss of arbitration occurs, TSIFR will be cleared and no further transmit attempts will be made.
PAGE 677
Freescale Semiconductor, Inc. Byte Data Link Controller Module Transmitting An In-Frame Response (IFR) Enter Type 2 IFR Transmit Routine Freescale Semiconductor, Inc...
PAGE 678
Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... last byte is written to the BDR, the TEOD bit is set, and a CRC byte (if desired) and an EOD are then transmitted. Because the two versions of the Type 3 IFR are transmitted identically, the description which follows will discuss both. For an illustration of the Type 3 IFR transmit sequence, refer to Transmitting A Type 3 IFR.
PAGE 679
Freescale Semiconductor, Inc. Byte Data Link Controller Module Transmitting An In-Frame Response (IFR) Freescale Semiconductor, Inc... NOTE: Step 4: Write the Last IFR Byte into the DLCBDR and Set TEOD As when transmitting a message, when transmitting a Type 3 IFR the user may write two, or possibly even three of the bytes to be transmitted into the DLCBDR before the first RxIFR interrupt occurs.
PAGE 680
Freescale Semiconductor, Inc. Byte Data Link Enter Type 3 IFR Transmit Routine Write first IFR byte to be transmitted into DLCBDR Freescale Semiconductor, Inc...
PAGE 681
Freescale Semiconductor, Inc. Byte Data Link Controller Module Receiving An In-Frame Response (IFR) Receiving An In-Frame Response (IFR) Freescale Semiconductor, Inc... Receiving an In-Frame Response with the BDLC is very similar to receiving a message frame. As each byte of an IFR is received, the DLCBSVR will indicate this to the CPU. An EOF indication in the DLCBSVR indicates that the IFR (and message) is complete.
PAGE 682
Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... When an EOF is Received, the IFR (and Message) is Complete Once all IFR bytes (including the possible CRC byte) have been received from the bus, the bus will again be idle for a time period equal to an EOD symbol. Following this, the BDLC will determine whether or not the last byte of the IFR is a CRC byte, and if so verify that the CRC byte is correct. If the CRC byte is not correct, this will be reflected in the DLCBSVR.
PAGE 683
Freescale Semiconductor, Inc. Byte Data Link Controller Module Special BDLC Operations Freescale Semiconductor, Inc... Receiving IFR Exceptions This basic IFR receiving flow can be interrupted for the same reasons as a normal message reception. The IFR receiving process can be adversely affected due to a CRC error, an Invalid or Out of Range Symbol or due to a receiver overrun caused by the CPU failing to service an RxIFR interrupt in a timely fashion.
PAGE 684
Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... Receiving A Message In 4X Mode In a diagnostic or production environment large amounts of data may need to be downloaded across the network to a component or module. This data is often sent in a large “Block Mode” message (see above) which violates the SAE J1850 limit for message length.
PAGE 685
Freescale Semiconductor, Inc. Byte Data Link Controller Module Modes of Operation Power Off Vdd > Vdd(Min.) and Any MCU reset source asserted Vdd ≤ Vdd(Min.) Freescale Semiconductor, Inc...
PAGE 686
Freescale Semiconductor, Inc. Byte Data Link Freescale Semiconductor, Inc... and some MCU reset source is asserted. To prevent the BDLC from entering an unknown state, the internal MCU reset is asserted while powering up the BDLC. BDLC Reset mode is also entered from any other mode as soon as one of the MCU’s possible reset sources (e.g. LVR, POR, COP watchdog, Reset pin etc.) is asserted.
PAGE 687
Freescale Semiconductor, Inc. Byte Data Link Controller Module Modes of Operation Freescale Semiconductor, Inc... bit in the DLCBCR1 register is previously cleared. In this mode, the BDLC internal clocks continue to run. Any activity on the J1850 network will cause the BDLC to exit BDLC Wait mode and generate an unmaskable interrupt of the CPU. This Wakeup interrupt state is reflected in the DLCBSVR, encoded as the highest priority interrupt.
PAGE 688
Freescale Semiconductor, Inc. Byte Data Link Wakeup from BDLC Stop with CPU in WAIT Freescale Semiconductor, Inc... NOTE: If the CPU executes the WAIT instruction and the BDLC enters the Stop mode (WCM = 1), the clocks to the BDLC are turned off, but the clocks in the MCU continue to run. Therefore, the message which wakes up the BDLC from Stop and the CPU from WAIT mode will be received correctly by the BDLC.
PAGE 689
Freescale Semiconductor, Inc. Byte Data Link Controller Module Interrupt Operation Interrupt Operation Freescale Semiconductor, Inc... The BDLC will generate an Interrupt Request to the CPU when a BDLC interrupt source is pending in the DLCBSVR. All DLCBSVR interrupts except the Wakeup Interrupt (DLCBSVR=$20) can be masked by clearing the IE bit in DLCBCR1. Refer to BDLC State Vector Register (DLCBSVR) for a description of the BDLC interrupt sources and how to service them.
PAGE 690
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Byte Data Link MC9S12DP256 — Revision 1.1 Byte Data Link Controller Module For More Information On This Product, Go to: www.freescale.
PAGE 691
Freescale Semiconductor, Inc. Background Debug Module (BDM) Background Debug Module (BDM) Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 692
Freescale Semiconductor, Inc. Background Debug Module • Block Diagram BDM disabled when secure feature is enabled The block diagram of the BDM is shown in Figure 136 below. HOST SYSTEM 16-BIT SHIFT REGISTER BKGD Freescale Semiconductor, Inc...
PAGE 693
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Background Debug Module (BDM) Registers High Byte Instruction Tagging Pin (TAGHI) This pin is used to tag the high byte of an instruction. When instruction tagging is on, a logic 0 at the falling edge of the external clock (ECLK) tags the high half of the instruction word being read into the instruction queue. Low Byte Instruction Tagging Pin (TAGLO) This pin is used to tag the low byte of an instruction.
PAGE 694
Freescale Semiconductor, Inc. Background Debug Module Address Register Name Bit 7 $FF06 BDMCCR Read: CCR7 Write: $FF07 BDMINR Read: REG15 Write: 6 5 4 3 2 1 Bit 0 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 REG14 REG13 REG12 REG11 0 0 0 Freescale Semiconductor, Inc...
PAGE 695
Freescale Semiconductor, Inc. Background Debug Module (BDM) Registers – ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in Special Single Chip Mode). Freescale Semiconductor, Inc... ENBDM — Enable BDM This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are still allowed.
PAGE 696
Freescale Semiconductor, Inc. Background Debug Module cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware to control program flow execution. 1 = Data phase of command is complete 0 = Data phase of command not complete Freescale Semiconductor, Inc... TRACE — TRACE1 BDM firmware command is being executed This bit gets set when a BDM TRACE1 firmware command is first recognized.
PAGE 697
Freescale Semiconductor, Inc. Background Debug Module (BDM) Registers The secure BDM firmware lookup table verifies that the on-chip EEPROM and Flash EEPROM are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. 1 = the system is in a unsecured mode 0 = the system is in a secured mode Freescale Semiconductor, Inc...
PAGE 698
Freescale Semiconductor, Inc. Background Debug Module BDM Internal Register Position Register (BDMINR) ( Address: $FF07 Read: Bit 7 6 5 4 3 2 1 Bit 0 REG15 REG14 REG13 REG12 REG11 0 0 0 0 0 0 0 0 0 0 0 Write: Freescale Semiconductor, Inc... Reset: = Unimplemented Read: All modes Write: Never REG15–REG11 — Internal register map position These five bits show the state of the upper five bits of the base address for the system’s relocatable register block.
PAGE 699
Freescale Semiconductor, Inc. Background Debug Module (BDM) Operation Freescale Semiconductor, Inc... Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted in Modes of Operation below. Firmware commands can only be executed when the system is in active background debug mode (BDM).
PAGE 700
Freescale Semiconductor, Inc. Background Debug Module NOTE: If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. Freescale Semiconductor, Inc... In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses $FF00 to $FFFF. BDM registers are mapped to addresses $FF00 to $FF07.
PAGE 701
Freescale Semiconductor, Inc. Background Debug Module (BDM) Operation The BDM hardware commands are listed in Table 121. Table 121 Hardware Commands Opcode (hex) Data BACKGROUND 90 None READ_BD_BYTE E4 Read from memory with standard BDM firmware lookup table 16-bit address in map. Odd address data on low byte; even address data on 16-bit data out high byte READ_BD_WORD EC 16-bit address Read from memory with standard BDM firmware lookup table 16-bit data out in map. Must be aligned access.
PAGE 702
Freescale Semiconductor, Inc. Background Debug Module instruction execution is suspended while the CPU executes the firmware located in the standard BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM. Freescale Semiconductor, Inc... As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become visible in the on-chip memory map at $FF00-$FFFF, and the CPU begins executing the standard BDM firmware.
PAGE 703
Freescale Semiconductor, Inc. Background Debug Module (BDM) Operation Freescale Semiconductor, Inc... BDM Command Structure Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. NOTE: 8-bit reads return 16-bits of data, of which, only one byte will contain valid data.
PAGE 704
Freescale Semiconductor, Inc. Background Debug Module and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. Freescale Semiconductor, Inc... Figure 138 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state.
PAGE 705
Freescale Semiconductor, Inc. Background Debug Module (BDM) Operation Freescale Semiconductor, Inc... The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit.
PAGE 706
Freescale Semiconductor, Inc. Background Debug Module CLOCK TARGET SYSTEM HOST TRANSMIT 1 Freescale Semiconductor, Inc... HOST TRANSMIT 0 PERCEIVED START OF BIT TIME TARGET SENSES BIT 10 CYCLES SYNCHRONIZATION UNCERTAINTY EARLIEST START OF NEXT BIT Figure 139 BDM Host-to-Target Serial Bit Timing The receive cases are more complicated. Figure 140 shows the host receiving a logic 1 from the target system.
PAGE 707
Freescale Semiconductor, Inc. Background Debug Module (BDM) Operation CLOCK TARGET SYSTEM HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE TARGET SYSTEM SPEEDUP PULSE HIGH-IMPEDANCE HIGH-IMPEDANCE PERCEIVED START OF BIT TIME Freescale Semiconductor, Inc... R-C RISE BKGD PIN 10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT HOST SAMPLES BKGD PIN Figure 140 BDM Target-to-Host Serial Bit Timing (Logic 1) Figure 141 shows the host receiving a logic 0 from the target.
PAGE 708
Freescale Semiconductor, Inc. Background Debug Module CLOCK TARGET SYS. HOST DRIVE TO BKGD PIN HIGH-IMPEDANCE SPEEDUP PULSE Freescale Semiconductor, Inc... TARGET SYS.
PAGE 709
Freescale Semiconductor, Inc. Background Debug Module (BDM) Operation The tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue, the CPU enters active BDM rather than executing the instruction. NOTE: Tagging is disabled when BDM becomes active and BDM serial commands are not processed while tagging is active. Freescale Semiconductor, Inc... Executing the BDM TAGGO command configures two system pins for tagging.
PAGE 710
Freescale Semiconductor, Inc. Background Debug Module Modes of Operation BDM is available in all operating modes but must be enabled before firmware commands are executed. Freescale Semiconductor, Inc... Some system peripherals may have a control bit which allows suspending the peripheral function during background debug mode. In special single-chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory.
PAGE 711
Freescale Semiconductor, Inc. Background Debug Module (BDM) Low-Power Options Freescale Semiconductor, Inc... Low-Power Options Run Mode The BDM does not include disable controls that would conserve power during run mode. Wait Mode The BDM cannot be used in wait mode if the system disables the clocks to the BDM. Stop Mode The BDM is completely shutdown in stop mode. Interrupt Operation The BDM does not generate interrupt requests. MC9S12DP256 — Revision 1.
PAGE 712
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Background Debug Module MC9S12DP256 — Revision 1.1 Background Debug Module (BDM) For More Information On This Product, Go to: www.freescale.
PAGE 713
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Breakpoint (BKP) Module Freescale Semiconductor, Inc... Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 External Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 714
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Freescale Semiconductor, Inc... There are two types of breakpoints: tagged and forced. Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow breaking just before a specific instruction executes. Tagged breakpoints will only occur on addresses. Tagging on data is not allowed; however, if this occurs, nothing will occur within the BKP module.
PAGE 715
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Block Diagram Block Diagram C Freescale Semiconductor, Inc...
PAGE 716
Freescale Semiconductor, Inc. Breakpoint (BKP) Module External Pin Descriptions The BKP sub-block does not access any external pins. Register Descriptions Freescale Semiconductor, Inc... There are eight 8-bit registers in the BKP module. NOTE: Breakpoint Control Register 0 (BKPCT0) Address Read: Write: Reset: All bits of all registers in this module are completely synchronous to internal clocks during a register read. This register is used to set the breakpoint modes. Read and write: anytime.
PAGE 717
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Register Descriptions BKBDM — Breakpoint Background Debug Mode Enable This bit determines if the breakpoint causes the part to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI) 0 = Go to Software Interrupt on a compare. 1 = Go to BDM on a compare. Freescale Semiconductor, Inc...
PAGE 718
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Freescale Semiconductor, Inc... Table 124 Breakpoint Mask Bits for First Address BK0MBH:BK0MBL Address Compare BKP0X BKP0H BKP0L x:0 Full Address Compare Yes(1) Yes Yes 0:1 256 byte Address Range Yes(1) Yes No 1:1 16K byte Address Range Yes(1) No No 1. If page is selected. The x:0 case is for a Full Address Compare.
PAGE 719
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Register Descriptions BK1MBH:BK1MBL — Breakpoint Mask High Byte and Low Byte of Data (Second Address) In Dual Mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the second address breakpoint. (See Table 125.). Freescale Semiconductor, Inc...
PAGE 720
Freescale Semiconductor, Inc. Breakpoint (BKP) Module In Full Mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the data breakpoint. (See Table 126.). Freescale Semiconductor, Inc... Table 126 Breakpoint Mask Bits for Data Breakpoints (Full Mode) BK1MBH:BK1MBL Data Compare BKP1X BKP1H BKP1L 0:0 High and Low Byte Compare No(1) Yes Yes 0:1 High Byte No(1) Yes No 1:0 Low Byte No(1) No Yes 1:1 No Compare No(1) No No 1.
PAGE 721
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Register Descriptions BK1RW — R/W Compare Value Freescale Semiconductor, Inc... When BK1RWE=1, this bit determines the type of bus cycle to match on the second address breakpoint.When BK1RWE=0, this bit has no effect. 0 = Write cycle will be matched. 1 = Read cycle will be matched.
PAGE 722
Freescale Semiconductor, Inc. Breakpoint (BKP) Module This register is used to set the breakpoint when compared against the low byte of the address. First Address Low Byte Breakpoint Register (BKP0L) Address Read: Write: Read and write: anytime $__04 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc...
PAGE 723
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Functional Description Data (Second Address) Low Byte Breakpoint Register (BKP1L) Address Read: Write: Freescale Semiconductor, Inc... Reset: In Dual Mode, this register is used to compare against the low order address lines. In Full Mode, this register is used to compare against the low order data lines.
PAGE 724
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Breakpoint Operating Modes Freescale Semiconductor, Inc... Dual Address Mode When Dual Address Mode is enabled, two address breakpoints can be set. Each breakpoint can cause a software interrupt (SWI) or cause the part to enter BDM. The BDM requests have a higher priority than the SWI requests. No data breakpoints are allowed. The BKTAG bit in the BKPCT0 register selects whether the breakpoint mode is force or tag.
PAGE 725
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Breakpoint Types Breakpoint Types The priority of the breakpoint types is as follows. The Breakpoint module gives priority to BDM requests over SWI requests. The external bus interface tags that pass through the BKP module can only assert BDM requests. Freescale Semiconductor, Inc...
PAGE 726
Freescale Semiconductor, Inc. Breakpoint (BKP) Module Low Power Options Freescale Semiconductor, Inc... Low power options are available in the BKP sub-block. Run Mode In run mode, if BKEN=0, all clocks to the breakpoint system are disabled. Wait Mode Wait mode power savings can be achieved by having the clock generator shut down the core clock if the BDM is not used. Stop Mode The BKP sub-block will be completely shutdown during a STOP instruction.
PAGE 727
Freescale Semiconductor, Inc. Revision History Revision History Freescale Semiconductor, Inc... This section lists the revision history of the document since Rev 1.0 (the first general release). Data for previous revisions is unavailable. Changes from Rev 1.0 to Rev 1.1 Section Page (in Rev 1.
PAGE 728
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Revision History MC9S12DP256 — Revision 1.1 Revision History For More Information On This Product, Go to: www.freescale.
PAGE 729
Freescale Semiconductor, Inc. Glossary Glossary Freescale Semiconductor, Inc... A — See “accumulators (A and B or D).” accumulators (A and B or D) — Two 8-bit (A and B) or one 16-bit (D) general-purpose registers in the CPU. The CPU uses the accumulators to hold operands and results of arithmetic and logic operations. acquisition mode — A mode of PLL operation with large loop bandwidth. Also see ’tracking mode’. address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
PAGE 730
Freescale Semiconductor, Inc. Glossary B — See “accumulators (A and B or D).” baud rate — The total number of bits transmitted per unit of time. BCD — See “binary-coded decimal (BCD).” Freescale Semiconductor, Inc... binary — Relating to the base 2 number system. binary number system — The base 2 number system, having two digits, 0 and 1. Binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high.
PAGE 731
Freescale Semiconductor, Inc. Glossary break interrupt — A software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus — A set of wires that transfers logic signals. bus clock — See "CPU clock". byte — A set of eight bits. Freescale Semiconductor, Inc... CAN — See "Motorola scalable CAN." CCR — See “condition code register.” central processor unit (CPU) — The primary functioning unit of any computer system.
PAGE 732
Freescale Semiconductor, Inc. Glossary condition code register (CCR) — An 8-bit register in the CPU that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. Freescale Semiconductor, Inc... control bit — One bit of a register manipulated by software to control the operation of the module. control unit — One of two major units of the CPU. The control unit contains logic functions that synchronize the machine and direct various operations.
PAGE 733
Freescale Semiconductor, Inc. Glossary CPU registers — Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC12 are: • A (8-bit accumulator) • B (8-bit accumulator) Freescale Semiconductor, Inc...
PAGE 734
Freescale Semiconductor, Inc. Glossary EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. enhanced capture timer (ECT) — The HC12 Enhanced Capture Timer module has the features of the HC12 Standard Timer module enhanced by additional features in order to enlarge the field of applications. Freescale Semiconductor, Inc...
PAGE 735
Freescale Semiconductor, Inc. Glossary hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A through F. high byte — The most significant eight bits of a word. illegal address — An address not within the memory map Freescale Semiconductor, Inc... illegal opcode — A nonexistent opcode. index registers (IX and IY) — Two 16-bit registers in the CPU. In the indexed addressing modes, the CPU uses the contents of IX or IY to determine the effective address of the operand.
PAGE 736
Freescale Semiconductor, Inc. Glossary latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency — The time lag between instruction completion and data movement. least significant bit (LSB) — The rightmost digit of a binary number. Freescale Semiconductor, Inc... logic 1 — A voltage level approximately equal to the input power voltage (VDD). logic 0 — A voltage level approximately equal to the ground voltage (VSS).
PAGE 737
Freescale Semiconductor, Inc. Glossary Freescale Semiconductor, Inc... memory location — Each M68HC12 memory location holds one byte of data and has a unique address. To store information in a memory location, the CPU places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. To read information from a memory location, the CPU places the address of the location on the address bus and asserts the read signal.
PAGE 738
Freescale Semiconductor, Inc. Glossary MSI — See "multiple serial interface". multiple serial interface — A module consisting of multiple independent serial I/O sub-systems, e.g. two SCI and one SPI. multiplexer — A device that can select one of a number of inputs and pass the logic level of that input on to the output. Freescale Semiconductor, Inc... nibble — A set of four bits (half of a byte).
PAGE 739
Freescale Semiconductor, Inc. Glossary overflow — A quantity that is too large to be contained in one byte or one word. Freescale Semiconductor, Inc... page zero — The first 256 bytes of memory (addresses $0000–$00FF). parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even parity system, every byte should have an even number of logic 1s.
PAGE 740
Freescale Semiconductor, Inc. Glossary polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, VDD and VSS. polling — Periodically reading a status bit to monitor the condition of a peripheral device. port — A set of wires for communicating with off-chip devices. Freescale Semiconductor, Inc... prescaler — A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc.
PAGE 741
Freescale Semiconductor, Inc. Glossary RAM — Random access memory. All RAM locations can be read or written by the CPU. The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off. RC circuit — A circuit consisting of capacitors and resistors having a defined time constant. read — To copy the contents of a memory location to the accumulator. Freescale Semiconductor, Inc... register — A circuit that stores a group of bits.
PAGE 742
Freescale Semiconductor, Inc. Glossary set — To change a bit from logic 0 to logic 1; opposite of clear. shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. Freescale Semiconductor, Inc... signed — A binary number notation that accommodates both positive and negative numbers.
PAGE 743
Freescale Semiconductor, Inc. Glossary Freescale Semiconductor, Inc... stop bit — A bit that signals the end of an asynchronous serial transmission. subroutine — A sequence of instructions to be used more than once in the course of a program. The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or BSR) instruction is used to call the subroutine.
PAGE 744
Freescale Semiconductor, Inc. Glossary variable — A value that changes during the course of program execution. VCO — See "voltage-controlled oscillator." vector — A memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. Freescale Semiconductor, Inc... voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input.
PAGE 745
Freescale Semiconductor, Inc. Literature Updates Literature Updates Freescale Semiconductor, Inc... This document contains the latest data available at publication time. For updates, contact one of the centers listed below: Literature Distribution Centers Order literature by mail or phone. USA/Europe Motorola Literature Distribution P.O. Box 5405 Denver, Colorado, 80217 Phone 1-303-675-2140 Japan Motorola Japan Ltd.
PAGE 746
Freescale Semiconductor, Inc. Literature Updates Customer Focus Center 1-800-521-6274 Freescale Semiconductor, Inc... Microcontroller DivisionÕs Web Site Directly access the Microcontroller Division’s web site with the following URL: http://www.motorola.com/semiconductors MC9S12DP256 — Revision 1.1 Literature Updates For More Information On This Product, Go to: www.freescale.
PAGE 747
Freescale Semiconductor, Inc. 1 2 3 4 5 Freescale Semiconductor, Inc... 6 7 8 9 10 11 12 13 14 15 For More Information On This Product, Go to: www.freescale.
PAGE 748
Freescale Semiconductor, Inc. 1 2 3 4 5 Freescale Semiconductor, Inc... 6 7 8 9 0 1 2 3 4 5 Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.