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HCS12X

Microcontrollers

freescale.com

MC9S12XDP512

Data Sheet

Covers

S12XD, S12XB & S12XA Families

MC9S12XDP512RMV2

Rev. 2.21

October 2009

Summary of content (1348 pages)

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MC9S12XDP512 Data Sheet Covers S12XD, S12XB & S12XA Families HCS12X Microcontrollers MC9S12XDP512RMV2 Rev. 2.21 October 2009 freescale.
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MC9S12XDP512RMV2 Data Sheet MC9S12XDP512RMV2 Rev. 2.
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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices. Read page 29 first to understand the maskset specific chapters of this document This document contains information for all constituent modules, with the exception of the S12X CPU.
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Revision History Date Revision Level April, 2005 02.07 New Book May, 2005 02.08 Minor corrections May, 2005 02.09 removed ESD Machine Model from electrical characteristics added thermal characteristics added more details to run current measurement configurations VDDA supply voltage range 3.15V - 3.6V fot ATD Operating Characteristics I/O Chararcteristics for alll pins except EXTAL, XTAL .... corrected VREG electrical spec IDD wait max 95mA May 2005 02.
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MC9S12XDP512 Data Sheet, Rev. 2.
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Section Number Title Page Chapter 1 Device Overview MC9S12XD-Family . . . . . . . . . . . . . . . . . . . . 31 Chapter 2 Clocks and Reset Generator (S12CRGV6) . . . . . . . . . . . . . . . . 79 Chapter 3 Pierce Oscillator (S12XOSCLCPV1) . . . . . . . . . . . . . . . . . . . . 119 Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description125 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) . . . . . . . . . . 159 Chapter 6 XGATE (S12XGATEV2). . . . . . . . . . . . . . . . . . . .
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Section Number Title Page Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) . . . . . . . . . . . . 1039 Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) . . . . . . . . . . . . 1073 Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2). . . . . . . . . . . . 1107 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1). . . . . . . . . . . . 1149 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1). . . . . . . . . . . . 1191 Chapter 30 Security (S12X9SECV2) . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page Chapter 1Device Overview MC9S12XD-Family 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.1 MC9S12XD/B/A Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 2.5 2.6 Title Page Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.5.2 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.5.3 Computer Operating Properly Watchdog (COP) Reset . . . . .
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Section Number 4.4 4.5 4.6 Title Page 4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.4.1 Analog Sub-block . . . . . . . . . . . . . . . . . . . . . .
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Section Number 6.5 6.6 6.7 6.8 6.9 Title Page 6.4.4 Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 6.4.5 Software Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.5.1 Incoming Interrupt Requests . . . .
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Section Number Title Page 7.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.1 8.2 8.3 8.4 8.5 8.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 9.5 9.6 9.7 Title Page 9.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 Initialization/Application Information .
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Section Number Title Page 11.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 12.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 13.1.
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Section Number Title Page 14.4.7 Autonomous Periodical Interrupt (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 14.4.8 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.4.9 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 14.4.10Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 16.4.3 XGATE Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 16.4.4 Priority Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 16.4.5 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 16.4.6 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 18.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 18.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 18.4.3 Chip Access Restrictions . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 20.4.1 S12XDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 20.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 20.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 22.4.2 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883 22.4.3 Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887 22.4.4 Expanded Bus Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888 22.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 25.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number Title Page 26.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104 26.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104 26.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104 26.5.3 Background Debug Mode . . . . . . . . . . . . . . . .
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Section Number Title Page Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 28.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 28.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number 29.5 29.6 29.7 29.8 Title Page 29.4.3 Illegal Flash Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 29.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 29.5.2 Stop Mode . . . . . . . . . . . . . . . .
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Section Number Title Page A.3 NVM, Flash, and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259 A.3.1 NVM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259 A.3.2 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section Number E.7 Title Page Pinout explanations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307 Appendix F Ordering Information Appendix G Detailed Register Map MC9S12XDP512 Data Sheet, Rev. 2.
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Section Number Title Page MC9S12XDP512 Data Sheet, Rev. 2.
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NOTE This documentation covers all devices in the S12XD, S12XB and S12XA families. A full list of these devices and their features can be found in the following chapters: • E.1 Memory Sizes and Package Options S12XD - Family • E.2 Memory Sizes and Package Options S12XA & S12XB Family • E.5 Peripheral Sets S12XD - Family • E.
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Chapter 1 Device Overview MC9S12XD-Family describes pinouts, detailed pin description , interrupts and register map of the cover part MC9S12XDP512 (maskset L15Y). For availability of the modules on other members of the S12XA, S12XB and S12XD families please refer to Appendix E Derivative Differences. For pinout explanations of the different parts refer to E.7 Pinout explanations:. For a list of available partnames /masksets refer to Table 1-6. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 1 Device Overview MC9S12XD-Family Chapter 1 Device Overview MC9S12XD-Family 1.1 Introduction The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family. Based around an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.
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Chapter 1 Device Overview MC9S12XD-Family 1.1.1 MC9S12XD/B/A Family Features This section lists the features which are available on MC9S12XDP512RMV2. See Appendix E Derivative Differences for availability of features and memory sizes on other family members.
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Chapter 1 Device Overview MC9S12XD-Family • • • • • • — 10-bit resolution — External and internal conversion trigger capabilityFiveFourTwo 1M bit per second, CAN 2.
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Chapter 1 Device Overview MC9S12XD-Family • 1.1.2 Development support — Single-wire background debug™ mode (BDM) — Four on-chip hardware breakpoints Modes of Operation Normal expanded mode, Emulation of single-chip mode and Emulation of expanded mode are ony available on family members with an external bus interface in 144-pin LQFP. See Appendix E Derivative Differences for package options.
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Chapter 1 Device Overview MC9S12XD-Family SCI1 SPI0 DDRA PTA Timer 4-Channel 16-Bit with Prescaler for Internal Timebases Non-Multiplexed External Bus Interface (EBI) DDRB DDRC DDRD PTB SCI3 RXD TXD Digital Supply 2.5 V VDD1,2 VSS1,2 PLL Supply 2.
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Chapter 1 Device Overview MC9S12XD-Family XGATE Peripheral Co-Processor SCI1 CAN4 RXCAN TXCAN Digital Supply 2.5 V VDD1,2 VSS1,2 Analog Supply 3-5 V VDDA VSSA IIC0 PWM I/O Supply 3-5 V VDDX VSSX Voltage Regulator 3-5 V VDDR VSSR PTAD1 PJ0 PJ1 DDRJ PLL Supply 2.
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Chapter 1 Device Overview MC9S12XD-Family 1.1.4 Device Memory Map Table 1-1shows the device register memory map of the MC9S12XDP512. Available modules on other Family members please refer to Appendix E Derivative Differences Unimplemented register space shown in Table 1-1 is not allocated to any module. Writing to these locations have no effect. Read access to these locations returns zero. Figure 1-1 shows the global address mapping for the parts listed in Table 1-2. Table 1-1.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-1.
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Chapter 1 Device Overview MC9S12XD-Family CPU and BDM Local Memory Map Global Memory Map 0x00_0000 0x00_07FF 2K REGISTERS CS3 Unimplemented RAM 0x0800 0x0C00 0x1000 RAM 2K REGISTERS 1K EEPROM window EPAGE 0x0F_FFFF 1K EEPROM 4K RAM window Unimplemented EEPROM RPAGE CS2 0x0000 RAMSIZE RAM_LOW 8K RAM EEPROM_LOW EEPROM 0x4000 0x13_FFFF CS2 Unpaged 16K FLASH EEPROMSIZE 0x2000 0x1F_FFFF External Space CS1 0x8000 PPAGE 0x3F_FFFF 0xC000 CS0 16K FLASH window Unimplemented FLASH Unpag
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Chapter 1 Device Overview MC9S12XD-Family Table 1-2.
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Chapter 1 Device Overview MC9S12XD-Family CPU and BDM Local Memory Map Global Memory Map 0x00_0000 0x00_07FF 2K REGISTERS CS3 Unimplemented RAM 0x0800 0x0C00 0x1000 RAM 2K REGISTERS 1K EEPROM window EPAGE 0x0F_FFFF 1K EEPROM 4K RAM window Unimplemented EEPROM RPAGE CS2 0x0000 RAMSIZE RAM_LOW 8K RAM EEPROM_LOW EEPROM 0x4000 0x13_FFFF CS2 Unpaged 16K FLASH EEPROMSIZE 0x2000 0x1F_FFFF External Space CS1 0x8000 PPAGE 0x3F_FFFF 0xC000 CS0 16K FLASH window Unimplemented FLASH Unpag
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Chapter 1 Device Overview MC9S12XD-Family Table 1-3.
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Chapter 1 Device Overview MC9S12XD-Family XGATE Local Memory Map Figure 1-5. GATE Global Address Mapping Global Memory Map 0x00_0000 Registers 0x00_07FF XGRAM_LOW 0x0800 RAM 0x0F_FFFF RAMSIZE Registers XGRAMSIZE 0x0000 FLASH RAM 0x78_0800 0xFFFF FLASHSIZE FLASH XGFLASH_HIGH 0x7F_FFFF MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-4. XGATE Resources (see Figure 1-5) Device 1 XGRANMSIZE XGRAM_LOW 9S12XDP512 32K 0x0F_8000 9S12XDT512 20K 0x0F_B000 9S12XDT384 20K 0x0F_B000 9S12XA512 32K 0x0F_8000 9S12XDQ256 16K 0x0F_C000 9S12XD256 14K 0x0F_C800 9S12XB256 10K 0x0F_D800 9S12XA256 16K 0x0F_C000 XGFLASHSIZE1 XGFLASH_HIGH 30K 0x78_7FFF Available Flah Memory 30K on all listed parts MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 1 Device Overview MC9S12XD-Family XGATE Local Memory Map Figure 1-6. XGATE Global Address Mapping Global Memory Map 0x00_0000 Registers 0x00_07FF XGRAM_LOW 0x0800 RAM 0x0F_FFFF RAMSIZE Registers XGRAMSIZE 0x0000 RAM 0xFFFF 0x7F_FFFF MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-5. XGATE Resources (see Figure 1-6) Device XGRAMSIZE XGRAM_LOW 9S12XDG128 12K 0x0F_D000 3S12XDG128 12K 0x0F_D000 9S12XD128 8K 0x0F_E000 9S12XD64 4K 0x0F_F000 9S12XB128 6K 0x0F_E800 9S12XA128 12K 0x0F_D000 MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 1 Device Overview MC9S12XD-Family 1.1.5 Part ID Assignments & Maskset Numbers The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. Table 1-6 shows the assigned part ID number and Mask Set number. Table 1-6.
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Chapter 1 Device Overview MC9S12XD-Family The S12XD, S12XA and S12XB family devices are offered in the following packages: • 144-pin LQFP package with an external bus interface (address/data bus) • 112-pin LQFP without external bus interface • 80-pin QFP without external bus interface See Appendix E Derivative Differences for package options. CAUTION Most the I/O Pins have different functionality depending on the module configuration. Not all functions are shown in the following pinouts.
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144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ROMCTL/EWAIT VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ4/KWJ4/SDA1/CS0 PJ5/KWJ5/SCL1/CS2 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MI
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MC9S12XD-Family 112-Pin LQFP Pins shown in BOLD are not available on the 80-Pin QFP package option 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC9S12XD-Family 80-Pin QFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB6 PB7 XCLKS/PE7 PE6 PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PE3 PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/
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Chapter 1 Device Overview MC9S12XD-Family 1.2.2 Signal Properties Summary Table 1-7 summarizes the pin functionality of the MC9S12XDP512. For available modules on other parts of the S12XD, S12XB and S12XA family please refer to Appendix E Derivative Differences. Table 1-7.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-7.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-7.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-7.
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Chapter 1 Device Overview MC9S12XD-Family 1.2.3.3 TEST — Test Pin This input only pin is reserved for test. This pin has a pulldown device. NOTE The TEST pin must be tied to VSS in all applications. 1.2.3.4 VREGEN — Voltage Regulator Enable Pin This input only pin enables or disables the on-chip voltage regulator. The input has a pullup device. 1.2.3.5 XFC — PLL Loop Filter Pin Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements.
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Chapter 1 Device Overview MC9S12XD-Family 1.2.3.10 PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins PA[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are used for the external address bus. In MCU emulation modes of operation, these pins are used for external address bus and internal visibility read data. 1.2.3.11 PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins PB[7:1] are general-purpose input or output pins.
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Chapter 1 Device Overview MC9S12XD-Family The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check is ongoing. This is the case for: • Power on reset or low-voltage reset • Clock monitor reset • Any reset while in self-clock mode or full stop mode The selected oscillator configuration is frozen with the rising edge of reset. The pin can be configured to drive the internal system clock ECLKX2.
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Chapter 1 Device Overview MC9S12XD-Family pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the instruction word being read into the instruction queue. The input voltage threshold for PE6 can be configured to reduced levels, to allow data from an external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PE6 is configured to reduced levels out of reset in expanded and emulation modes. 1.2.3.
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Chapter 1 Device Overview MC9S12XD-Family 1.2.3.25 PH7 / KWH7 / SS2 / TXD5 — Port H I/O Pin 7 PH7 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as slave select pin SS of the serial peripheral interface 2 (SPI2). It can be configured as the transmit pin TXD of serial communication interface 5 (SCI5). 1.2.3.26 PH6 / KWH6 / SCK2 / RXD5 — Port H I/O Pin 6 PH6 is a general-purpose input or output pin.
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Chapter 1 Device Overview MC9S12XD-Family 1.2.3.32 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 PH0 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 1 (SPI1). 1.2.3.33 PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0— PORT J I/O Pin 7 PJ7 is a general-purpose input or output pin.
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Chapter 1 Device Overview MC9S12XD-Family 1.2.3.40 PK7 / EWAIT / ROMCTL — Port K I/O Pin 7 PK7 is a general-purpose input or output pin. During MCU emulation modes and normal expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. The EWAIT input signal maintains the external bus access until the external device is ready to capture data (write) or provide data (read).
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Chapter 1 Device Overview MC9S12XD-Family 1.2.3.47 PM4 / RXCAN0 / RXCAN2 / RXCAN4 / MOSI0 — Port M I/O Pin 4 PM4 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the scalable controller area network controllers 0, 2, or 4 (CAN0, CAN2, or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the serial peripheral interface 0 (SPI0). 1.2.3.
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Chapter 1 Device Overview MC9S12XD-Family be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 2 (SPI2). 1.2.3.55 PP4 / KWP4 / PWM4 / MISO2 — Port P I/O Pin 4 PP4 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 4 output.
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Chapter 1 Device Overview MC9S12XD-Family 1.2.3.62 PS5 / MOSI0 — Port S I/O Pin 5 PS5 is a general-purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0). 1.2.3.63 PS4 / MISO0 — Port S I/O Pin 4 PS4 is a general-purpose input or output pin.
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Chapter 1 Device Overview MC9S12XD-Family 1.2.4.2 VDDR1, VDDR2, VSSR1, VSSR2 — Power and Ground Pins for I/O Drivers and for Internal Voltage Regulator External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-8. MC9S12XD Family Power and Ground Connection Summary Pin Number Mnemonic Nominal Voltage 144-Pin LQFP 112-Pin LQFP 80-Pin QFP VDD1, 2 15, 87 13, 65 9, 49 2.5 V VSS1, 2 16, 88 14, 66 10, 50 0V VDDR1 53 41 29 5.0 V VSSR1 52 40 28 0V VDDX1 139 107 77 5.0 V VSSX1 138 106 76 0V VDDX2 26 N.A. N.A. 5.0 V VSSX2 27 N.A. N.A. 0V VDDR2 82 N.A. N.A. 5.0 V VSSR2 81 N.A. N.A. 0V VDDA 107 83 59 5.
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Chapter 1 Device Overview MC9S12XD-Family 1.3 System Clock Description The clock and reset generator module (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-12 shows the clock connections from the CRG to all modules. See 79Chapterf or details on clock generation. SCI Modules SPI Modules CAN Modules IIC Modules ATD Modules Bus Clock PIT EXTAL Oscillator Clock ECT CRG PIM XTAL Core Clock RAM S12X XGATE FLASH EEPROM Figure 1-14.
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Chapter 1 Device Overview MC9S12XD-Family The CAN modules may be configured to have their clock sources derived either from the bus clock or directly from the oscillator clock. This allows the user to select its clock based on the required jitter performance. Consult MSCAN block description for more details on the operation and configuration of the CAN blocks. In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the output of the oscillator.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-9.
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Chapter 1 Device Overview MC9S12XD-Family 1.5 1.5.1 1.5.1.1 Modes of Operation User Modes Normal Expanded Mode Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data bus, and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the internal bus rate. 1.5.1.
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Chapter 1 Device Overview MC9S12XD-Family 1.5.2.1 System Stop Modes The system stop modes are entered if the CPU executes the STOP instruction and the XGATE doesn’t execute a thread and the XGFACT bit in the XGMCTL register is cleared. Depending on the state of the PSTP bit in the CLKSEL register the MCU goes into pseudo stop mode or full stop mode. Please refer to CRG section. Asserting RESET, XIRQ, IRQ or any other interrupt ends the system stop modes. 1.5.2.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-12.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-12.
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Chapter 1 Device Overview MC9S12XD-Family Table 1-12.
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Chapter 1 Device Overview MC9S12XD-Family 1.6.2 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block Guides for register reset states. 1.6.2.1 I/O Pins Refer to the PIM Block Guide for reset configurations of all peripheral module ports. 1.6.2.2 Memory The RAM array is not initialized out of reset. 1.
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Chapter 1 Device Overview MC9S12XD-Family 1.8 ATD0 External Trigger Input Connection The ATD_10B8C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG, and ETRIG3. The external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-15 shows the connection of the external trigger inputs on MC9S12XDP512RMV2. Table 1-15. ATD0 External Trigger Sources External Trigger Input Connected to . .
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Chapter 1 Device Overview MC9S12XD-Family MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.1 Introduction This specification describes the function of the clocks and reset generator (CRG). 2.1.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.1.2 Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG. • Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required, the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value. • Wait mode In this mode, the PLL can be disabled automatically depending on the PLLSEL bit in the CLKSEL register.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.1.3 Block Diagram Figure 2-1 shows a block diagram of the CRG.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.2 External Signal Description This section lists and describes the signals that connect off chip. 2.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins These pins provide operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, VDDPLL and VSSPLL must be connected to properly. 2.2.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.1 Module Memory Map Table 2-1 gives an overview on all CRG registers. Table 2-1.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2 Register Descriptions This section describes in address order all the CRG registers and their individual bits.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.1 CRG Synthesizer Register (SYNR) The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (fSCM).
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.3 Reserved Register (CTFLG) This register is reserved for factory testing of the CRG module and is not available in normal modes. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-6. Reserved Register (CTFLG) Read: Always reads 0x_00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRG fucntionality. 2.3.2.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-2. CRGFLG Field Descriptions (continued) Field Description 5 LVRF Low Voltage Reset Flag — If low voltage reset feature is not available (see device specification) LVRF always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.5 CRG Interrupt Enable Register (CRGINT) This register enables CRG interrupt requests. 7 R W Reset 6 RTIE ILAF 0 1 5 0 0 4 LOCKIE 0 3 2 0 0 0 0 1 SCMIE 0 0 0 0 1. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset. = Unimplemented or Reserved Figure 2-8. CRG Interrupt Enable Register (CRGINT) Read: Anytime Write: Anytime Table 2-3.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.6 CRG Clock Select Register (CLKSEL) This register controls CRG clock selection. Refer to Figure 2-17 for more details on the effect of each bit. 7 R W Reset 6 PLLSEL PSTP 0 0 5 4 0 0 0 0 3 PLLWAI 0 2 0 1 0 RTIWAI COPWAI 0 0 0 = Unimplemented or Reserved Figure 2-9. CRG Clock Select Register (CLKSEL) Read: Anytime Write: Refer to each bit for individual write conditions Table 2-4.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.7 CRG PLL Control Register (PLLCTL) This register controls the PLL functionality. R W Reset 7 6 5 4 3 2 1 0 CME PLLON AUTO ACQ FSTWKP PRE PCE SCME 1 1 1 1 0 0 0 1 Figure 2-10. CRG PLL Control Register (PLLCTL) Read: Anytime Write: Refer to each bit for individual write conditions Table 2-5. PLLCTL Field Descriptions Field Description 7 CME Clock Monitor Enable Bit — CME enables the clock monitor.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-5. PLLCTL Field Descriptions (continued) Field Description 2 PRE RTI Enable during Pseudo Stop Bit — PRE enables the RTI during pseudo stop mode. Write anytime. 0 RTI stops running during pseudo stop mode. 1 RTI continues running during pseudo stop mode. Note: If the PRE bit is cleared the RTI dividers will go static while pseudo stop mode is active. The RTI dividers will not initialize like in wait mode with RTIWAI bit set.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-7.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-8.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.9 CRG COP Control Register (COPCTL) This register controls the COP (computer operating properly) watchdog. 7 R W WCOP Reset1 6 RSBCK 0 5 4 3 0 0 0 0 0 WRTMASK 0 2 1 0 CR2 CR1 CR0 1. Refer to Device User Guide (Section: CRG) for reset values of WCOP, CR2, CR1, and CR0. = Unimplemented or Reserved Figure 2-12. CRG COP Control Register (COPCTL) Read: Anytime Write: 1.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-9. COPCTL Field Descriptions (continued) Field Description 5 WRTMASK Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of WCOP and CR[2:0]. 0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL 1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.10 Reserved Register (FORBYP) NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG’s functionality. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 2-13.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.3.2.12 CRG COP Timer Arm/Reset Register (ARMCOP) This register is used to restart the COP time-out period. 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Reset Figure 2-15. ARMCOP Register Diagram Read: Always reads 0x_00 Write: Anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4 Functional Description 2.4.1 Functional Blocks 2.4.1.1 Phase Locked Loop (PLL) The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,... 126,128 based on the SYNR register.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4.1.1.1 PLL Operation The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is divided in a range of 1 to 64 (REFDV + 1) to output the REFERENCE clock. The VCO output clock, (PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (SYNR + 1)] to output the FEEDBACK clock. Figure 2-16.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1): • The TRACK bit is a read-only indicator of the mode of the filter. • The TRACK bit is set when the VCO frequency is within a certain tolerance, ∆trk, and is clear when the VCO frequency is out of a certain tolerance, ∆unt. • The LOCK bit is a read-only indicator of the locked state of the PLL.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) The clock generator creates the clocks used in the MCU (see Figure 2-17). The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the setting of the respective configuration bits. The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The memory blocks use the bus clock. If the MCU enters self clock mode (see Section 2.4.2.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See Figure 2-19 as an example. check window 1 3 2 50000 49999 VCO Clock 1 2 3 4 5 4096 OSCCLK 4095 osc ok Figure 2-19. Check Window Example The sequence for clock quality check is shown in Figure 2-20.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) NOTE Remember that in parallel to additional actions caused by self clock mode or clock monitor reset1 handling the clock quality checker continues to check the OSCCLK signal. The clock quality checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (fSCM) and an active VREG during pseudo stop mode or wait mode. 2.4.1.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4.2.2 Self Clock Mode The VCO has a minimum operating frequency, fSCM. If the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO running at minimum operating frequency; this mode of operation is called self clock mode. This requires CME = 1 and SCME = 1.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) CPU Req’s Wait Mode. PLLWAI=1 ? No Yes Clear PLLSEL, Disable PLL No Enter Wait Mode CME=1 ? Wait Mode left due to external reset No Yes Exit Wait w. ext.RESET CM Fail ? INT ? Yes No Yes Exit Wait w. CMRESET No SCME=1 ? Yes SCMIE=1 ? Generate SCM Interrupt (Wakeup from Wait) No Exit Wait Mode Yes Exit Wait Mode SCM=1 ? No Yes Enter SCM Enter SCM Continue w. Normal OP Figure 2-21.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) There are four different scenarios for the CRG to restart the MCU from wait mode: • External reset • Clock monitor reset • COP reset • Any interrupt If the MCU gets an external reset or COP reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal or COP reset vector.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-12. Outcome of Clock Loss in Wait Mode CME SCME SCMIE 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 0 Clock failure --> Scenario 1: OSCCLK recovers prior to exiting wait mode. – MCU remains in wait mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag. Some time later OSCCLK recovers.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Core req’s Stop Mode. Clear PLLSEL, Disable PLL Exit Stop w. ext.RESET Stop Mode left due to external reset No INT ? Yes No Enter Stop Mode PSTP=1 ? Yes CME=1 ? No Yes SCME=1 & FSTWKP=1 ? No INT ? Yes Yes CM fail ? No No Yes No Exit Stop w. CMRESET No SCME=1 ? Yes Clock OK ? Exit Stop w.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4.3.3.1 Wake-up from Pseudo Stop Mode (PSTP=1) Wake-up from pseudo stop mode is the same as wake-up from wait mode.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-13. Outcome of Clock Loss in Pseudo Stop Mode CME SCME SCMIE 0 X X Clock failure --> No action, clock loss not detected. 1 0 X Clock failure --> CRG performs Clock Monitor Reset immediately 0 Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting pseudo stop mode. – MCU remains in pseudo stop mode, – VREG enabled, – PLL enabled, – SCM activated, – Start clock quality check, – Set SCMIF interrupt flag.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.4.3.3.2 Wake-up from Full Stop (PSTP = 0) The MCU requires an external interrupt or an external reset in order to wake-up from stop-mode. If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows (see Section 2.4.1.4, “Clock Quality Checker”).
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Chapter 2 Clocks and Reset Generator (S12CRGV6) CPU resumes program execution immediately Instruction FSTWKP=1 SCME=1 STOP IRQ Service STOP IRQ Service IRQ Service STOP Interrupt Interrupt Interrupt Power Saving Oscillator Clock Oscillator Disabled PLL Clock Core Clock Self-Clock Mode Figure 2-23. Fast Wake-up from Full Stop Mode: Example 1 . CPU resumes program execution immediately Instruction FSTWKP=1 SCME=1 STOP IRQ Service FSTWKP=0 SCMIE=1 Freq.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.5 Resets This section describes how to reset the CRG, and how the CRG itself controls the reset of the MCU. It explains all special reset requirements. Since the reset generator for the MCU is part of the CRG, this section also describes all automatic actions that occur during or as a result of individual reset conditions. The reset values of registers and signals are provided in Section 2.3, “Memory Map and Register Definition”.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Table 2-15.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.5.2 Clock Monitor Reset The CRG generates a clock monitor reset in case all of the following conditions are true: • Clock monitor is enabled (CME = 1) • Loss of clock is detected • Self-clock mode is disabled (SCME = 0). The reset event asynchronously forces the configuration registers to their default settings (see Section 2.3, “Memory Map and Register Definition”).
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Chapter 2 Clocks and Reset Generator (S12CRGV6) Clock Quality Check (no Self-Clock Mode) RESET )( Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 2-26. RESET Pin Tied to VDD (by a pull-up resistor) Clock Quality Check (no Self Clock Mode) )( RESET Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK Figure 2-27. RESET Pin Held Low Externally 2.6 Interrupts The interrupts/reset vectors requested by the CRG are listed in Table 2-16.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) 2.6.2 PLL Lock Interrupt The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit. 2.6.
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Chapter 2 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 3.1 Introduction The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The module will be operated from the VDDPLL supply rail (2.5 V nominal) and require the minimum number of external components. It is designed for optimal start-up margin with typical crystal oscillators. 3.1.1 Features The XOSC will contain circuitry to dynamically control current gain in the output amplitude.
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Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 3.1.3 Block Diagram Figure 3-1 shows a block diagram of the XOSC. Monitor_Failure Clock Monitor OSCCLK Peak Detector Gain Control VDDPLL = 2.5 V Rf XTAL EXTAL Figure 3-1. XOSC Block Diagram 3.2 External Signal Description This section lists and describes the signals that connect off chip 3.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry.
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Chapter 3 Pierce Oscillator (S12XOSCLCPV1) EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ. NOTE Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. Loop controlled circuit is not suited for overtone resonators and crystals. EXTAL C1 MCU Crystal or Ceramic Resonator XTAL C2 VSSPLL Figure 3-2.
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Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 3.2.3 XCLKS — Input Signal The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. Refer to the Device Overview chapter for polarity and sampling conditions of the XCLKS pin. Table 3-1 lists the state coding of the sampled XCLKS signal. . Table 3-1. Clock Selection Based on XCLKS XCLKS 3.
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Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 3.4.3 Wait Mode Operation During wait mode, XOSC is not impacted. 3.4.4 Stop Mode Operation XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 3 Pierce Oscillator (S12XOSCLCPV1) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.1 Introduction The ATD10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to the Electrical Specifications chapter for ATD accuracy. 4.1.1 • • • • • • • • • • • • • • 4.1.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Bus Clock ATD clock Clock Prescaler Trigger Mux ETRIG0 ETRIG1 ETRIG2 ATD10B16C Sequence Complete Mode and Timing Control Interrupt ETRIG3 (see Device Overview chapter for availability and connectivity) ATDCTL1 ATDDIEN Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15 PORTAD VDDA VSSA Successive Approximation Register (SAR) and DAC VRH VRL AN15 AN14 AN13 AN12 AN11
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.2 External Signal Description This section lists all inputs to the ATD10B16C block. 4.2.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — Analog Input Channel x Pins This pin serves as the analog input channel x. It can also be configured as general-purpose digital input and/or external trigger for the ATD conversion. 4.2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description . Table 4-1.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2 Register Descriptions This section describes in address order all the ATD10B16C registers and their individual bits.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Register Name 0x000D ATDDIEN1 R W 0x000E PORTAD0 W R 0x000F PORTAD1 R Bit 7 6 5 4 3 2 1 Bit 0 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 W R BIT 9 MSB BIT 7 MSB 0x0010–0x00
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-3. Multi-Channel Wrap Around Coding 4.3.2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-5. External Trigger Channel Select Coding 1 4.3.2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 7 6 5 4 3 2 1 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE 0 0 0 0 0 0 0 R 0 ASCIF W Reset 0 = Unimplemented or Reserved Figure 4-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime Table 4-6. ATDCTL2 Field Descriptions Field Description 7 ADPU ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power consumption.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-7. External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity 0 0 Falling Edge 0 1 Ring Edge 1 0 Low Level 1 1 High Level MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.4 ATD Control Register 3 (ATDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence. 7 R 6 5 4 3 2 1 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 0 1 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 4-6.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-8. ATDCTL3 Field Descriptions (continued) Field Description 2 FIFO Result Register FIFO Mode —If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-10. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. 7 6 5 4 3 2 1 0 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 0 0 0 0 0 1 0 1 R W Reset Figure 4-7.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-13. Clock Prescaler Values Prescale Value Total Divisor Value Max. Bus Clock1 Min.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-14. ATDCTL5 Field Descriptions (continued) Field Description 3:0 C[D:A} Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 4-17 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT = 0), this selection code specified the channel to be examined.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-17. Analog Input Channel Select Coding CD CC CB CA Analog Input Channel 0 0 0 0 AN0 0 0 0 1 AN1 0 0 1 0 AN2 0 0 1 1 AN3 0 1 0 0 AN4 0 1 0 1 AN5 0 1 1 0 AN6 0 1 1 1 AN7 1 0 0 0 AN8 1 0 0 1 AN9 1 0 1 0 AN10 1 0 1 1 AN11 1 1 0 0 AN12 1 1 0 1 AN13 1 1 1 0 AN14 1 1 1 1 AN15 MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. 7 6 R 5 4 ETORF FIFOR 0 0 0 SCF 3 2 1 0 CC3 CC2 CC1 CC0 0 0 0 0 W Reset 0 0 = Unimplemented or Reserved Figure 4-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on CC[3:0]) Table 4-18.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-18. ATDSTAT0 Field Descriptions (continued) Field Description 4 FIFOR FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.8 R Reserved Register 0 (ATDTEST0) 7 6 5 4 3 2 1 0 u u u u u u u u 1 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved u = Unaffected Figure 4-10. Reserved Register 0 (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality. 4.3.2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-20. Special Channel Select Coding SC CD CC CB CA Analog Input Channel 1 0 0 X X Reserved 1 0 1 0 0 VRH 1 0 1 0 1 VRL 1 0 1 1 0 (VRH+VRL) / 2 1 0 1 1 1 Reserved 1 1 X X X Reserved 4.3.2.10 ATD Status Register 2 (ATDSTAT2) This read-only register contains the Conversion Complete Flags CCF15 to CCF8.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.11 ATD Status Register 1 (ATDSTAT1) This read-only register contains the Conversion Complete Flags CCF7 to CCF0 R 7 6 5 4 3 2 1 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 4-13. ATD Status Register 1 (ATDSTAT1) Read: Anytime Write: Anytime, no effect Table 4-22.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.12 ATD Input Enable Register 0 (ATDDIEN0) 7 6 5 4 3 2 1 0 IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 0 0 0 0 0 0 0 0 R W Reset Figure 4-14. ATD Input Enable Register 0 (ATDDIEN0) Read: Anytime Write: anytime Table 4-23.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.14 Port Data Register 0 (PORTAD0) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN[15:8]. R 7 6 5 4 3 2 1 0 PTAD15 PTAD14 PTAD13 PTAD12 PTAD11 PTAD10 PTAD9 PTAD8 1 1 1 1 1 1 1 1 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 W Reset Pin Function = Unimplemented or Reserved Figure 4-16.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.15 Port Data Register 1 (PORTAD1) The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN7-0. R 7 6 5 4 3 2 1 0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 1 1 1 1 1 1 1 1 AN 7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 W Reset Pin Function = Unimplemented or Reserved Figure 4-17.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.16 ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.3.2.16.2 R (10-BIT) R (8-BIT) Right Justified Result Data 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 4-20.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.4.1.2 Analog Input Multiplexer The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine. 4.4.1.3 Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential. 4.4.1.4 Analog-to-Digital (A/D) Machine The A/D machine performs analog to digital conversions.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger circuitry. After ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 4.5 Resets At reset the ATD10B16C is in a power down state. The reset state of each individual bit is listed within Section 4.3, “Memory Map and Register Definition,” which details the registers and their bit fields. 4.6 Interrupts The interrupt requested by the ATD10B16C is listed in Table 4-28. Refer to MCU specification for related vector address and priority. Table 4-28.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.1 Introduction The ATD10B8C is an 8-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical specifications for ATD accuracy. 5.1.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.1.2.2 • • • 5.1.3 MCU Operating Modes Stop mode Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This aborts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time tSR before initiating a new ATD conversion sequence.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Bus Clock ETRIG0 ETRIG1 ETRIG2 Clock Prescaler ATD clock Trigger Mux ATD10B8C Sequence Complete Mode and Timing Control Interrupt ETRIG3 (See Device Overview chapter for availability and connectivity) ATDDIEN ATDCTL1 PORTAD Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 VDDA VSSA Successive Approximation Register (SAR) and DAC VRH VRL AN7 AN6 + AN5 Sample & Hold AN4 1 1 AN3 Analog AN2 – Comparator MUX AN1 AN0 Figure 5
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the ATD. 5.3.1 Module Memory Map Figure 5-2 gives an overview of all ATD registers. NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. 5.3.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Register Name Unimplemente d R W ATDSTAT1 R W Unimplemente d R W ATDDIEN R W Unimplemente d R W PORTAD R W Bit 7 6 5 4 3 2 1 Bit 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 Left Justified Result Data Note: The read portion of the left justified result data registers has been divided to show the bit position when reading 10-bi
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 BIT 1 U BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 ATDDR3L 10-BIT 8-BIT W ATDDR4H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 ATDDR4L 10-BIT 8-BIT W BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 ATDD45H 10-BIT BIT 9 MSB 8-BIT BIT 7 MSB W BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 A
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Register Name Bit 7 6 5 4 3 2 1 Bit 0 ATDD47H 10-BIT 8-BIT W 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 ATDD47L 10-BIT BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 8-BIT = Unimplemented or Reserved Figure 5-2. ATD Register Summary (Sheet 5 of 5) 5.3.2.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3.2.2 ATD Control Register 1 (ATDCTL1) Writes to this register will abort current conversion sequence but will not start a new sequence. 7 R W ETRIGSEL Reset 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 ETRIGCH2 ETRIGCH1 ETRIGCH0 1 1 1 = Unimplemented or Reserved Figure 5-4. ATD Control Register 1 (ATDCTL1) Read: Anytime Write: Anytime Table 5-3.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3.2.3 ATD Control Register 2 (ATDCTL2) This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. 7 R W Reset ADPU 0 6 5 4 3 2 1 AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE 0 0 0 0 0 0 0 ASCIF 0 = Unimplemented or Reserved Figure 5-5. ATD Control Register 2 (ATDCTL2) Read: Anytime Write: Anytime Table 5-5.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Table 5-5. ATDCTL2 Field Descriptions (continued) Field Description 1 ASCIE ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. 0 ASCIF ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 5.3.2.7, “ATD Status Register 0 (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Table 5-7. ATDCTL3 Field Descriptions (continued) Field Description 2 FIFO Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3.2.5 ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. R W Reset 7 6 5 4 3 2 1 0 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 0 0 0 0 0 1 0 1 Figure 5-7.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Table 5-12. Clock Prescaler Values Prescale Value Total Divisor Value Max. Bus Clock1 Min.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3.2.6 ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. 7 R W Reset 6 DJM 0 5 4 DSGN SCAN MULT 0 0 0 3 0 0 2 1 0 CC CB CA 0 0 0 = Unimplemented or Reserved Figure 5-8. ATD Control Register 5 (ATDCTL5) Read: Anytime Write: Anytime Table 5-13.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Table 5-14. Available Result Data Formats SRES8 DJM DSGN Result Data Formats Description and Bus Bit Mapping 1 1 1 0 0 0 0 0 1 0 0 1 0 1 X 0 1 X 8-bit / left justified / unsigned — bits 8–15 8-bit / left justified / signed — bits 8–15 8-bit / right justified / unsigned — bits 0–7 10-bit / left justified / unsigned — bits 6–15 10-bit / left justified / signed — bits 6–15 10-bit / right justified / unsigned — bits 0–9 Table 5-15.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3.2.7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the sequence complete flag, overrun flags for external trigger and FIFO mode, and the conversion counter. 7 R W Reset 6 0 SCF 0 0 5 4 ETORF FIFOR 0 0 3 2 1 0 0 CC2 CC1 CC0 0 0 0 0 = Unimplemented or Reserved Figure 5-9. ATD Status Register 0 (ATDSTAT0) Read: Anytime Write: Anytime (No effect on (CC2, CC1, CC0)) Table 5-17.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3.2.8 R Reserved Register (ATDTEST0) 7 6 5 4 3 2 1 0 U U U U U U U U 1 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 5-10. Reserved Register (ATDTEST0) Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality. 5.3.2.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3.2.10 ATD Status Register 1 (ATDSTAT1) This read-only register contains the conversion complete flags. R 7 6 5 4 3 2 1 0 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 5-12. ATD Status Register 1 (ATDSTAT1) Read: Anytime Write: Anytime, no effect Table 5-20.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3.2.11 R W Reset ATD Input Enable Register (ATDDIEN) 7 6 5 4 3 2 1 0 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 0 0 0 0 0 0 0 0 Figure 5-13. ATD Input Enable Register (ATDDIEN) Read: Anytime Write: Anytime Table 5-21.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.3.2.13 ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the result registers based on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.4 Functional Description The ATD is structured in an analog and a digital sub-block. 5.4.1 Analog Sub-Block The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block. 5.4.1.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.4.2 Digital Sub-Block This subsection explains some of the digital features in more detail. See register descriptions for all details. 5.4.2.1 External Trigger Input The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place.
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Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5.4.2.2 General Purpose Digital Input Port Operation The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external input data that can be accessed through the digital port register PORTAD (input-only). The analog/digital multiplex operation is performed in the input pads.
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Chapter 6 XGATE (S12XGATEV2) 6.1 Introduction The XGATE module is a peripheral co-processor that allows autonomous data transfers between the MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the transferred data and perform complex communication protocols. The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s interrupt load. Figure 6-1 gives an overview on the XGATE architecture.
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Chapter 6 XGATE (S12XGATEV2) Special XGATE channel that is not associated with any peripheral service request. A Software Channel is triggered by its Software Trigger Bit which is implemented in the XGATE module. XGATE Semaphore A set of hardware flip-flops that can be exclusively set by either the S12X_CPU or the XGATE. (see 6.4.4/6-204) XGATE Thread A code sequence which is executed by the XGATE’s RISC core after receiving an XGATE request.
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Chapter 6 XGATE (S12XGATEV2) In freeze mode all clocks of the XGATE module may be stopped, depending on the module configuration (see Section 6.3.1.1, “XGATE Control Register (XGMCTL)”). 6.1.4 Block Diagram Figure Figure 6-1 shows a block diagram of the XGATE. Peripheral Interrupts XGATE REQUESTS XGATE XGATE INTERRUPTS S12X_INT Interrupt Flags Semaphores RISC Core Software Triggers Data/Code Software Triggers S12X_DBG S12X_MMC Peripherals Figure 6-1. XGATE Block Diagram 6.
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Chapter 6 XGATE (S12XGATEV2) 6.3 Memory Map and Register Definition This section provides a detailed description of address space and registers used by the XGATE module. The memory map for the XGATE module is given below in Figure 6-2.The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reserved registers read zero.
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Chapter 6 XGATE (S12XGATEV2) XGIF R 127 126 125 124 123 122 121 0 0 0 0 0 0 0 111 Register Name 113 112 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 R W
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Chapter 6 XGATE (S12XGATEV2) XGSWTM R 15 14 13 0 0 0 W XGSEMM R W Reserved 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 0 0 0 0 3 2 1 0 XGSWT[7:0] XGSWTM[7:0] 0 4 XGSEM[7:0] XGSEMM[7:0] R W XGCCR R 0 0 0 W XGPC R XGN XGZ XGV XGC XGPC W Reserved 0 R W Reserved R W XGR1 R XGR1 W XGR2 R XGR2 W XGR3 R XGR3 W XGR4 R XGR4 W XGR5 R XGR5 W XGR6 R XGR6 W XGR7 R XGR7 W = Unimplemented or Reserved Figure 6-2.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.1 XGATE Control Register (XGMCTL) All module level switches and flags are located in the module control register Figure 6-3. 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 XG SSM XG FACTM 0 0 R W XGEM Reset 0 XG XG FRZM DBGM 0 0 7 0 0 5 4 3 2 0 XG XGIEM SWEIFM 0 6 XGE XGFRZ XGDBG XGSS XGFACT 0 0 0 0 0 0 1 0 XG SWEIF XGIE 0 0 = Unimplemented or Reserved Figure 6-3.
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Chapter 6 XGATE (S12XGATEV2) Table 6-1. XGMCTL Field Descriptions (Sheet 2 of 3) Field 11 XGFACTM Description XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or cleared if a "1" is written to the XGFACTM bit in the same register access. Read: This bit will always read "0".
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Chapter 6 XGATE (S12XGATEV2) Table 6-1. XGMCTL Field Descriptions (Sheet 3 of 3) Field Description 4 XGSS XGATE Single Step — This bit forces the execution of a single instruction if the XGATE is in DEBUG Mode and no software error has occurred (XGSWEIF cleared). Read: 0 No single step in progress 1 Single step in progress Write 0 No effect 1 Execute a single RISC instruction Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has been executed.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.2 XGATE Channel ID Register (XGCHID) The XGATE channel ID register (Figure 6-4) shows the identifier of the XGATE channel that is currently active. This register will read “$00” if the XGATE module is idle. In debug mode this register can be used to start and terminate threads (see Section 6.6.1, “Debug Features”). 7 R 6 5 4 3 0 2 1 0 0 0 0 XGCHID[6:0] W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 6-4.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.4 XGATE Channel Interrupt Flag Vector (XGIF) The interrupt flag vector (Figure 6-6) provides access to the interrupt flags bits of each channel. Each flag may be cleared by writing a "1" to its bit location.
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Chapter 6 XGATE (S12XGATEV2) Table 6-4. XGIV Field Descriptions Field Description 127–9 XGIF[78:9] Channel Interrupt Flags — These bits signal pending channel interrupts. They can only be set by the RISC core. Each flag can be cleared by writing a "1" to its bit location. Unimplemented interrupt flags will always read "0". Refer to Section “Interrupts” of the SoC Guide for a list of implemented Interrupts.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.5 XGATE Software Trigger Register (XGSWT) The eight software triggers of the XGATE module can be set and cleared through the XGATE software trigger register (Figure 6-7). The upper byte of this register, the software trigger mask, controls the write access to the lower byte, the software trigger bits. These bits can be set or cleared if a "1" is written to the associated mask in the same bus cycle.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.6 XGATE Semaphore Register (XGSEM) The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM instructions. The S12X_CPU has access to the semaphores through the XGATE semaphore register (Figure 6-8). Refer to section Section 6.4.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.7 XGATE Condition Code Register (XGCCR) The XGCCR register (Figure 6-9) provides access to the RISC core’s condition code register. R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 XGN XGZ XGV XGC 0 0 0 0 = Unimplemented or Reserved Figure 6-9. XGATE Condition Code Register (XGCCR) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-7.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.8 XGATE Program Counter Register (XGPC) The XGPC register (Figure 6-10) provides access to the RISC core’s program counter. 15 14 13 12 11 10 9 8 R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGPC W Reset 0 0 0 0 0 0 0 0 Figure 6-10. XGATE Program Counter Register (XGPC) Figure 6-11. Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-8. XGPC Field Descriptions Field 15–0 XGPC[15:0] 6.3.1.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.10 XGATE Register 2 (XGR2) The XGR2 register (Figure 6-13) provides access to the RISC core’s register 2. 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGR2 W Reset 7 0 0 0 0 0 0 0 0 Figure 6-13. XGATE Register 2 (XGR2) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-10. XGR2 Field Descriptions Field 15–0 XGR2[15:0] 6.3.1.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.12 XGATE Register 4 (XGR4) The XGR4 register (Figure 6-15) provides access to the RISC core’s register 4. 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGR4 W Reset 7 0 0 0 0 0 0 0 0 Figure 6-15. XGATE Register 4 (XGR4) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-12. XGR4 Field Descriptions Field 15–0 XGR4[15:0] 6.3.1.
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Chapter 6 XGATE (S12XGATEV2) 6.3.1.14 XGATE Register 6 (XGR6) The XGR6 register (Figure 6-17) provides access to the RISC core’s register 6. 15 14 13 12 11 10 9 8 R 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 XGR6 W Reset 7 0 0 0 0 0 0 0 0 Figure 6-17. XGATE Register 6 (XGR6) Read: In debug mode if unsecured Write: In debug mode if unsecured Table 6-14. XGR6 Field Descriptions Field 15–0 XGR6[15:0] 6.3.1.
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Chapter 6 XGATE (S12XGATEV2) 6.4 Functional Description The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories and peripherals (see Figure 6-1). The RISC processor always remains in an idle state until it is triggered by an XGATE request. Then it executes a code sequence that is associated with the request and optionally triggers an interrupt to the S12X_CPU upon completion. Code sequences are not interruptible.
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Chapter 6 XGATE (S12XGATEV2) The programmer’s model of the XGATE RISC core is shown in Figure 6-19. The processor offers a set of seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An additional eighth register (R0) is tied to the value “$0000”. Register R1 has an additional functionality. It is preloaded with the initial variable pointer of the channel’s service request vector (see Figure 6-20).
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Chapter 6 XGATE (S12XGATEV2) 6.4.4 Semaphores The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism to protect system resources that are shared between two concurrent threads of program execution; one thread running on the S12X_CPU and one running on the XGATE RISC core. Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked by XGATE”.
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Chapter 6 XGATE (S12XGATEV2) Figure 6-22 gives an example of the typical usage of the XGATE hardware semaphores. Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is running on the RISC core. They both have a critical section of code that accesses the same system resource. To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence must be embedded in a semaphore lock/release sequence as shown. S12X_CPU .........
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Chapter 6 XGATE (S12XGATEV2) 6.5 6.5.1 Interrupts Incoming Interrupt Requests XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which specific interrupt requests these are and which channel ID they are assigned to is documented in Section “Interrupts” of the SoC Guide. 6.5.
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Chapter 6 XGATE (S12XGATEV2) • • 6.6.2 Single Stepping Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core registers will be updated accordingly.
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Chapter 6 XGATE (S12XGATEV2) 3. Tagged Breakpoints The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section). Upon entering debug mode, the program counter will point to the tagged instruction. The other RISC core registers will hold the result of the previous instruction. 4. Forced Breakpoints Forced breakpoints are triggered by the S12X_DBG module (see section 4.
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Chapter 6 XGATE (S12XGATEV2) 6.8.1.1 Naming Conventions RD RD.L RD.H RS, RS1, RS2 RS.L, RS1.L, RS2.L RS.H, RS1.H, RS2.
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Chapter 6 XGATE (S12XGATEV2) 6.8.1.4 Immediate 4 Bit Wide (IMM4) The 4 bit wide immediate addressing mode is supported by all shift instructions. RD = RD ∗ imm4 Examples: LSL LSR 6.8.1.5 R4,#1 R4,#3 ; R4 = R4 << 1; shift register R4 by 1 bit to the left ; R4 = R4 >> 3; shift register R4 by 3 bits to the right Immediate 8 Bit Wide (IMM8) The 8 bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD, CMP). RD = RD ∗ imm8 Examples: ADDL SUBL LDH CMPL 6.8.1.
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Chapter 6 XGATE (S12XGATEV2) 6.8.1.8 Dyadic Addressing (DYA) In this mode the result of an operation between two registers is stored in one of the registers used as operands. RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the destination register, only the condition code flags are updated.
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Chapter 6 XGATE (S12XGATEV2) 6.8.1.13 Index Register plus Register Offset (IDR) For load and store instructions (RS, RI) provides a variable offset in a register. Examples: LDB STW 6.8.1.14 R4,(R1,R2) R4,(R1,R2) ; loads a byte from R1+R2 into R4 ; stores R4 as a word to R1+R2 Index Register plus Register Offset with Post-increment (IDR+) [RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory.
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Chapter 6 XGATE (S12XGATEV2) 6.8.2.2 Logic and Arithmetic Instructions All logic and arithmetic instructions support the 8 bit immediate addressing mode (IMM8: RD = RD ∗ #IMM8) and the triadic addressing mode (TRI: RD = RS1 ∗ RS2). All arithmetic is considered as signed, sign, overflow, zero and carry flag will be updated. The carry will not be affected for logical operations. ADDL ANDH R2,#1 R4,#$FE ; increment R2 ; R4.H = R4.
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Chapter 6 XGATE (S12XGATEV2) 6.8.2.5 Bit Field Operations This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions are very useful to extract, insert, clear, set or toggle portions of a 16 bit word.
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Chapter 6 XGATE (S12XGATEV2) 6.8.3 Cycle Notation Table 6-16 show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each letter implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals are not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit operations.
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Chapter 6 XGATE (S12XGATEV2) ADC ADC Add with Carry Operation RS1 + RS2 + C ⇒ RD Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the previous operation allowing 32 and more bit additions.
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Chapter 6 XGATE (S12XGATEV2) ADD ADD Add without Carry Operation RS1 + RS2 ⇒ RD RD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #[15:8]) Performs a 16 bit addition and stores the result in the destination register RD. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) ADDH ADDH Add Immediate 8 bit Constant (High Byte) Operation RD + IMM8:$00 ⇒ RD Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition and stores the result in the high byte of the destination register RD. This instruction can be used after an ADDL for a 16 bit immediate addition.
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Chapter 6 XGATE (S12XGATEV2) ADDL Add Immediate 8 bit Constant (Low Byte) ADDL Operation RD + $00:IMM8 ⇒ RD Adds the content of register RD and an unsigned immediate 8 bit constant using binary addition and stores the result in the destination register RD. This instruction must be used first for a 16 bit immediate addition in conjunction with the ADDH instruction. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) AND AND Logical AND Operation RS1 & RS2 ⇒ RD RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8]) Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD. Remark: There is no complement to the BITH and BITL functions. This can be imitated by using R0 as a destination register. AND R0, RS1, RS2 performs a bit wise test without storing a result.
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Chapter 6 XGATE (S12XGATEV2) ANDH Logical AND Immediate 8 bit Constant (High Byte) ANDH Operation RD.H & IMM8 ⇒ RD.H Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
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Chapter 6 XGATE (S12XGATEV2) ANDL Logical AND Immediate 8 bit Constant (Low Byte) ANDL Operation RD.L & IMM8 ⇒ RD.L Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
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Chapter 6 XGATE (S12XGATEV2) ASR ASR Arithmetic Shift Right Operation n b15 RD C n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
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Chapter 6 XGATE (S12XGATEV2) BCC BCC Branch if Carry Cleared (Same as BHS) Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Carry flag and branches if C = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BCC REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BCS BCS Branch if Carry Set (Same as BLO) Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Carry flag and branches if C = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BCS REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BEQ BEQ Branch if Equal Operation If Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Zero flag and branches if Z = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BEQ REL9 Address Mode REL9 Machine Code 0 0 1 0 0 1 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BFEXT BFEXT Bit Field Extract Operation RS1[(o+w):o] ⇒ RD[w:0]; 0 ⇒ RD[15:(w+1)] w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD. The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted.
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Chapter 6 XGATE (S12XGATEV2) BFFO BFFO Bit Field Find First One Operation FirstOne (RS) ⇒ RD; Searches the first “1” in register RS (from MSB to LSB) and writes the bit position into the destination register RD. The upper bits of RD are cleared. In case the content of RS is equal to $0000, RD will be cleared and the carry flag will be set. This is used to distinguish a “1” in position 0 versus no “1” in the whole RS register at all. CCR Effects N Z V C 0 ∆ 0 ∆ N: Z: V: C: 1 0; cleared.
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Chapter 6 XGATE (S12XGATEV2) BFINS BFINS Bit Field Insert Operation RS1[w:0] ⇒ RD[(w+o):o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0 and writes them into register RD starting at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to clear bits.
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Chapter 6 XGATE (S12XGATEV2) BFINSI BFINSI Bit Field Insert and Invert Operation !RS1[w:0] ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, inverts them and writes into register RD starting at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to set bits.
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Chapter 6 XGATE (S12XGATEV2) BFINSX BFINSX Bit Field Insert and XNOR Operation !(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o]; w = (RS2[7:4]) o = (RS2[3:0]) Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes the bits back io RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0 as a RS1, this command can be used to toggle bits.
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Chapter 6 XGATE (S12XGATEV2) BGE BGE Branch if Greater than or Equal to Zero Operation If N ^ V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≥ RS2: SUB BGE R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BGE REL9 Address Mode REL9 Machine Code 0 0 1 1 0 1 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BGT BGT Branch if Greater than Zero Operation If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 > RS2: SUB BGE R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BGT REL9 Address Mode REL9 Machine Code 0 0 1 1 1 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BHI BHI Branch if Higher Operation If C | Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 > RS2: SUB BHI R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BHI REL9 Address Mode REL9 Machine Code 0 0 1 1 0 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BHS BHS Branch if Higher or Same (Same as BCC) Operation If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≥ RS2: SUB BHS R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BHS REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BITH BITH Bit Test Immediate 8 bit Constant (High Byte) Operation RD.H & IMM8 ⇒ NONE Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant. Only the condition code flags get updated, but no result is written back CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
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Chapter 6 XGATE (S12XGATEV2) BITL BITL Bit Test Immediate 8 bit Constant (Low Byte) Operation RD.L & IMM8 ⇒ NONE Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant. Only the condition code flags get updated, but no result is written back. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
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Chapter 6 XGATE (S12XGATEV2) BLE BLE Branch if Less or Equal to Zero Operation If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 ≤ RS2: SUB BLE R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLE REL9 Address Mode REL9 Machine Code 0 0 1 1 1 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BLO BLO Branch if Carry Set (Same as BCS) Operation If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 < RS2: SUB BLO R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLO REL9 Address Mode REL9 Machine Code 0 0 1 0 0 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BLS BLS Branch if Lower or Same Operation If C | Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare unsigned numbers. Branch if RS1 ≤ RS2: SUB BLS R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLS REL9 Address Mode REL9 Machine Code 0 0 1 1 0 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BLT BLT Branch if Lower than Zero Operation If N ^ V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Branch instruction to compare signed numbers. Branch if RS1 < RS2: SUB BLT R0,RS1,RS2 REL9 CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BLT REL9 Address Mode REL9 Machine Code 0 0 1 1 0 1 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BMI BMI Branch if Minus Operation If N = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Sign flag and branches if N = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BMI REL9 Address Mode REL9 Machine Code 0 0 1 0 1 0 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BNE BNE Branch if Not Equal Operation If Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Zero flag and branches if Z = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BNE REL9 Address Mode REL9 Machine Code 0 0 1 0 0 1 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BPL BPL Branch if Plus Operation If N = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Sign flag and branches if N = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BPL REL9 Address Mode REL9 Machine Code 0 0 1 0 1 0 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BRA BRA Branch Always Operation PC + $0002 + (REL10 << 1) ⇒ PC Branches always CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BRA REL10 Address Mode REL10 Machine Code 0 0 1 1 1 1 Cycles REL10 PP MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BRK BRK Break Operation Put XGATE into Debug Mode (see Section 6.6.2, “Entering Debug Mode”)and signals a Software breakpoint to the S12X_DBG module (see section 4.9 of the S12X_DBG Section). NOTE It is not possible to single step over a BRK instruction. This instruction does not advance the program counter. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
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Chapter 6 XGATE (S12XGATEV2) BVC BVC Branch if Overflow Cleared Operation If V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Overflow flag and branches if V = 0. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BVC REL9 Address Mode REL9 Machine Code 0 0 1 0 1 1 0 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) BVS BVS Branch if Overflow Set Operation If V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC Tests the Overflow flag and branches if V = 1. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form BVS REL9 Address Mode REL9 Machine Code 0 0 1 0 1 1 1 Cycles REL9 PP/P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) CMP CMP Compare Operation RS2 – RS1 ⇒ NONE (translates to SUB R0, RS1, RS2) RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8]) Subtracts two 16 bit values and discards the result. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) CMPL Compare Immediate 8 bit Constant (Low Byte) CMPL Operation RS.L – IMM8 ⇒ NONE, only condition code flags get updated Subtracts the 8 bit constant IMM8 contained in the instruction code from the low byte of the source register RS.L using binary subtraction and updates the condition code register accordingly. Remark: There is no equivalent operation using triadic addressing.
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Chapter 6 XGATE (S12XGATEV2) COM COM One’s Complement Operation ~RS ⇒ RD (translates to XNOR RD, R0, RS) ~RD ⇒ RD (translates to XNOR RD, R0, RD) Performs a one’s complement on a general purpose register. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
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Chapter 6 XGATE (S12XGATEV2) CPC CPC Compare with Carry Operation RS2 – RS1 - C ⇒ NONE (translates to SBC R0, RS1, RS2) Subtracts the carry bit and the content of register RS2 from the content of register RS1 using binary subtraction and discards the result. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) CPCH CPCH Compare Immediate 8 bit Constant with Carry (High Byte) Operation RS.H - IMM8 - C ⇒ NONE, only condition code flags get updated Subtracts the carry bit and the 8 bit constant IMM8 contained in the instruction code from the high byte of the source register RD using binary subtraction and updates the condition code register accordingly.
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Chapter 6 XGATE (S12XGATEV2) CSEM CSEM Clear Semaphore Operation Unlocks a semaphore that was locked by the RISC core. In monadic address mode, bits RS[2:0] select the semaphore to be cleared. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
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Chapter 6 XGATE (S12XGATEV2) CSL CSL Logical Shift Left with Carry Operation n C RD C C C C n bits n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
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Chapter 6 XGATE (S12XGATEV2) CSR CSR Logical Shift Right with Carry Operation n C C C C RD C n bits n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with the carry flag. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
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Chapter 6 XGATE (S12XGATEV2) JAL JAL Jump and Link Operation PC + $0002 ⇒ RD; RD ⇒ PC Jumps to the address stored in RD and saves the return address in RD. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form JAL RD Address Mode MON Machine Code 0 0 0 0 0 RD 1 1 Cycles 1 1 0 1 1 0 PP MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) LDB LDB Load Byte from Memory (Low Byte) Operation M[RB, #OFFS5 ⇒ RD.L; $00 ⇒ RD.H M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H; RI+1 ⇒ RI;1 RI-1 ⇒ RI; M[RS, RI] ⇒ RD.L; $00 ⇒ RD.H Loads a byte from memory into the low byte of register RD. The high byte is cleared. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
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Chapter 6 XGATE (S12XGATEV2) LDH LDH Load Immediate 8 bit Constant (High Byte) Operation IMM8 ⇒ RD.H; Loads an eight bit immediate constant into the high byte of register RD. The low byte is not affected. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form LDH RD, #IMM8 Address Mode IMM8 Machine Code 1 1 1 1 1 RD Cycles IMM8 P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) LDL LDL Load Immediate 8 bit Constant (Low Byte) Operation IMM8 ⇒ RD.L; $00 ⇒ RD.H Loads an eight bit immediate constant into the low byte of register RD. The high byte is cleared. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form LDL RD, #IMM8 Address Mode IMM8 Machine Code 1 1 1 1 0 RD Cycles IMM8 P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) LDW LDW Load Word from Memory Operation M[RB, #OFFS5] ⇒ RD M[RB, RI] ⇒ RD M[RB, RI] ⇒ RD; RI+2 ⇒ RI1 RI-2 ⇒ RI; M[RS, RI] ⇒ RD IMM16 ⇒ RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8]) Loads a 16 bit value into the register RD. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
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Chapter 6 XGATE (S12XGATEV2) LSL LSL Logical Shift Left Operation n C RD 0 0 0 0 n bits n = RS or IMM4 Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
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Chapter 6 XGATE (S12XGATEV2) LSR LSR Logical Shift Right Operation n 0 0 0 0 RD C n bits n = RS or IMM4 Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled with zeros. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0. n can range from 0 to 16. In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is equal to 0.
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Chapter 6 XGATE (S12XGATEV2) MOV MOV Move Register Content Operation RS ⇒ RD (translates to OR RD, R0, RS) Copies the content of RS to RD. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected. Code and CPU Cycles Source Form MOV RD, RS Address Mode TRI Machine Code 0 0 0 1 0 RD 0 0 Cycles 0 RS 1 0 P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) NEG NEG Two’s Complement Operation –RS ⇒ RD (translates to SUB RD, R0, RS) –RD ⇒ RD (translates to SUB RD, R0, RD) Performs a two’s complement on a general purpose register. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) NOP NOP No Operation Operation No Operation for one cycle. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form NOP Address Mode INH Machine Code 0 0 0 0 0 0 0 1 0 0 Cycles 0 0 0 0 0 0 P MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) OR OR Logical OR Operation RS1 | RS2 ⇒ RD RD | IMM16⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8] Performs a bit wise logical OR between two 16 bit values and stores the result in the destination register RD. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Refer to ORH instruction for #IMM16 operations. 0; cleared. Not affected.
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Chapter 6 XGATE (S12XGATEV2) ORH ORH Logical OR Immediate 8 bit Constant (High Byte) Operation RD.H | IMM8 ⇒ RD.H Performs a bit wise logical OR between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
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Chapter 6 XGATE (S12XGATEV2) ORL ORL Logical OR Immediate 8 bit Constant (Low Byte) Operation RD.L | IMM8 ⇒ RD.L Performs a bit wise logical OR between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared. Not affected.
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Chapter 6 XGATE (S12XGATEV2) PAR PAR Calculate Parity Operation Calculates the number of ones in the register RD. The Carry flag will be set if the number is odd, otherwise it will be cleared. CCR Effects N Z V C 0 ∆ 0 ∆ N: Z: V: C: 0; cleared. Set if RD is $0000; cleared otherwise. 0; cleared. Set if there the number of ones in the register RD is odd; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) ROL ROL Rotate Left Operation RD n bits n = RS or IMM4 Rotates the bits in register RD n positions to the left. The lower n bits of the register RD are filled with the upper n bits. Two source forms are available. In the first form, the parameter n is contained in the instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits of the source register RS[3:0]. All other bits in RS are ignored.
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Chapter 6 XGATE (S12XGATEV2) ROR ROR Rotate Right Operation RD n bits n = RS or IMM4 Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are filled with the lower n bits. Two source forms are available. In the first form, the parameter n is contained in the instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits of the source register RS[3:0]. All other bits in RS are ignored.
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Chapter 6 XGATE (S12XGATEV2) RTS RTS Return to Scheduler Operation Terminates the current thread of program execution and remains idle until a new thread is started by the hardware scheduler. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected. Code and CPU Cycles Source Form RTS Address Mode INH Machine Code 0 0 0 0 0 0 1 0 0 0 Cycles 0 0 0 0 0 0 PA MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) SBC SBC Subtract with Carry Operation RS1 - RS2 - C ⇒ RD Subtracts the content of register RS2 and the value of the Carry bit from the content of register RS1 using binary subtraction and stores the result in the destination register RD. Also the zero flag is carried forward from the previous operation allowing 32 and more bit subtractions.
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Chapter 6 XGATE (S12XGATEV2) SEX SEX Sign Extend Byte to Word Operation The result in RD is the 16 bit sign extended representation of the original two’s complement number in the low byte of RD.L. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. 0; cleared. Not affected.
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Chapter 6 XGATE (S12XGATEV2) SIF SIF Set Interrupt Flag Operation Sets the Interrupt Flag of an XGATE Channel. This instruction supports two source forms. If inherent address mode is used, then the interrupt flag of the current channel (XGCHID) will be set. If the monadic address form is used, the interrupt flag associated with the channel id number contained in RS[6:0] is set. The content of RS[15:7] is ignored. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected.
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Chapter 6 XGATE (S12XGATEV2) SSEM SSEM Set Semaphore Operation Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag: 1 = Semaphore is locked by the RISC core 0 = Semaphore is locked by the S12X_CPU In monadic address mode, bits RS[2:0] select the semaphore to be set. CCR Effects N Z V C — — — ∆ N: Z: V: C: Not affected. Not affected. Not affected. Set if semaphore is locked by the RISC core; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) STB STB Store Byte to Memory (Low Byte) Operation RS.L ⇒ M[RB, #OFFS5] RS.L ⇒ M[RB, RI] RS.L ⇒ M[RB, RI]; RI+1 ⇒ RI; RI–1 ⇒ RI; RS.L ⇒ M[RB, RI]1 Stores the low byte of register RD to memory. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
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Chapter 6 XGATE (S12XGATEV2) STW STW Store Word to Memory Operation RS ⇒ M[RB, #OFFS5] RS ⇒ M[RB, RI] RS ⇒ M[RB, RI]; RI+2 ⇒ RI; RI–2 ⇒ RI; RS ⇒ M[RB, RI]1 Stores the content of register RS to memory. CCR Effects N Z V C — — — — N: Z: V: C: Not affected. Not affected. Not affected. Not affected.
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Chapter 6 XGATE (S12XGATEV2) SUB SUB Subtract without Carry Operation RS1 – RS2 ⇒ RD RD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM16{15:8]) Subtracts two 16 bit values and stores the result in the destination register RD. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) SUBH SUBH Subtract Immediate 8 bit Constant (High Byte) Operation RD – IMM8:$00 ⇒ RD Subtracts a signed immediate 8 bit constant from the content of high byte of register RD and using binary subtraction and stores the result in the high byte of destination register RD. This instruction can be used after an SUBL for a 16 bit immediate subtraction.
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Chapter 6 XGATE (S12XGATEV2) SUBL Subtract Immediate 8 bit Constant (Low Byte) SUBL Operation RD – $00:IMM8 ⇒ RD Subtracts an immediate 8 bit constant from the content of register RD using binary subtraction and stores the result in the destination register RD. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) TFR TFR Transfer from and to Special Registers Operation TFR RD,CCR: CCR ⇒ RD[3:0]; 0 ⇒ RD[15:4] TFR CCR,RD: RD[3:0] ⇒ CCR TFR RD,PC: PC+4 ⇒ RD Transfers the content of one RISC core register to another. The TFR RD,PC instruction can be used to implement relative subroutine calls. Example: RETADDR SUBR TFR BRA ... ...
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Chapter 6 XGATE (S12XGATEV2) TST TST Test Register Operation RS – 0 ⇒ NONE (translates to SUB R0, RS, R0) Subtracts zero from the content of register RS using binary subtraction and discards the result. CCR Effects N Z V C ∆ ∆ ∆ ∆ N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the result is $0000; cleared otherwise. Set if a two´s complement overflow resulted from the operation; cleared otherwise.
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Chapter 6 XGATE (S12XGATEV2) XNOR XNOR Logical Exclusive NOR Operation ~(RS1 ^ RS2) ⇒ RD ~(RD ^ IMM16)⇒ RD (translates to XNOR RD, #IMM16{15:8]; XNOR RD, #IMM16[7:0]) Performs a bit wise logical exclusive NOR between two 16 bit values and stores the result in the destination register RD. Remark: Using R0 as a source registers will calculate the one’s complement of the other source register. Using R0 as both source operands will fill RD with $FFFF.
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Chapter 6 XGATE (S12XGATEV2) XNORH Logical Exclusive NOR Immediate 8 bit Constant (High Byte) XNORH Operation ~(RD.H ^ IMM8) ⇒ RD.H Performs a bit wise logical exclusive NOR between the high byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.H. The low byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 15 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared.
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Chapter 6 XGATE (S12XGATEV2) XNORL Logical Exclusive NOR Immediate 8 bit Constant (Low Byte) XNORL Operation ~(RD.L ^ IMM8) ⇒ RD.L Performs a bit wise logical exclusive NOR between the low byte of register RD and an immediate 8 bit constant and stores the result in the destination register RD.L. The high byte of RD is not affected. CCR Effects N Z V C ∆ ∆ 0 — N: Z: V: C: Set if bit 7 of the result is set; cleared otherwise. Set if the 8 bit result is $00; cleared otherwise. 0; cleared.
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Chapter 6 XGATE (S12XGATEV2) 6.8.6 Instruction Coding Table 6-17 summarizes all XGATE instructions in the order of their machine coding. Table 6-17.
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Chapter 6 XGATE (S12XGATEV2) Table 6-17.
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Chapter 6 XGATE (S12XGATEV2) Table 6-17.
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Chapter 6 XGATE (S12XGATEV2) 6.9 Initialization and Application Information 6.9.1 Initialization The recommended initialization of the XGATE is as follows: 1. Clear the XGE bit to suppress any incoming service requests. 2. Make sure that no thread is running on the XGATE. This can be done in several ways: a) Poll the XGCHID register until it reads $00. Also poll XGDBG and XGSWEIF to make sure that the XGATE has not been stopped. b) Enter Debug Mode by setting the XGDBG bit. Clear the XGCHID register.
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Chapter 6 XGATE (S12XGATEV2) XGSWT XGSEM EQU EQU XGATE_REGS+$18 XGATE_REGS+$1A ;XGATE Software Trigger Register ;XGATE Semaphore Register RPAGE EQU $0016 RAM_SIZE EQU 32*$400 RAM_START RAM_START_XG RAM_START_GLOB EQU EQU EQU $1000 $10000-RAM_SIZE $100000-RAM_SIZE XGATE_VECTORS XGATE_VECTORS_XG EQU EQU RAM_START RAM_START_XG XGATE_DATA XGATE_DATA_XG EQU EQU RAM_START+(4*128) RAM_START_XG+(4*128) XGATE_CODE XGATE_CODE_XG EQU EQU XGATE_DATA+(XGATE_CODE_FLASH-XGATE_DATA_FLASH) XGATE_DATA_X
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Chapter 6 XGATE (S12XGATEV2) INIT_XGATE INIT_XGATE_BUSY_LOOP ;########################################### ;# INITIALIZE XGATE # ;########################################### MOVW #XGMCTL_CLEAR , XGMCTL;clear all XGMCTL bits TST BNE XGCHID ;wait until current thread is finished INIT_XGATE_BUSY_LOOP LDX LDD STD STD STD STD STD STD STD STD #XGIF #$FFFF 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ 2,X+ ;clear all channel interrupt flags MOVW #XGATE_VECTORS_XG, XGVBR;set vector base register MOVW #$FF00, XGSWT INIT
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Chapter 6 XGATE (S12XGATEV2) XGATE_DATA_FLASH XGATE_DATA_SCI XGATE_DATA_IDX XGATE_DATA_MSG XGATE_CODE_FLASH XGATE_CODE_DONE XGATE_CODE_FLASH_END XGATE_DUMMY_ISR_XG ;########################################### ;# XGATE DATA # ;########################################### ALIGN 1 EQU * EQU *-XGATE_DATA_FLASH DW SCI_REGS ;pointer to SCI register space EQU *-XGATE_DATA_FLASH DB XGATE_DATA_MSG ;string pointer EQU *-XGATE_DATA_FLASH FCC "Hello World! ;ASCII string DB $0D ;CR ;#################################
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.1 Introduction The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module enhanced by additional features in order to enlarge the field of applications, in particular for automotive ABS applications. This design specification describes the standard timer as well as the additional features. The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.1.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.2 External Signal Description The ECT module has a total of eight external pins. 7.2.1 IOC7 — Input Capture and Output Compare Channel 7 This pin serves as input capture or output compare for channel 7. 7.2.2 IOC6 — Input Capture and Output Compare Channel 6 This pin serves as input capture or output compare for channel 6. 7.2.3 IOC5 — Input Capture and Output Compare Channel 5 This pin serves as input capture or output compare for channel 5.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3 Memory Map and Register Definition This section provides a detailed description of all memory and registers. 7.3.1 Module Memory Map The memory map for the ECT module is given below in Table 7-1. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the ECT module and the address offset for each register. Table 7-1.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-1.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Register Name TSCR2 Bit 7 R W TFLG1 R W TFLG2 R W TC0 (High) R W TC0 (Low) R W TC1 (High) R W TC1 (Low) R W TC2 (High) R W TC2 (Low) R W TC3 (High) R W TC3 (Low) R W TC4 (High) R W TC4 (Low) R W TC5 (High) R W TC5 (Low) R W 6 5 4 3 2 1 Bit 0 0 0 0 TCRE PR2 PR1 PR0 C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Register Name TC6 (High) R W TC6 (Low) R W TC7 (High) R W TC7 (Low) R W PACTL R Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAEN PAMOD PEDGE CLK1 CLK0 PA0VI PAI 0 0 0 0 0 PA0VF PAIF 0 W PAFLG R 0 W PACN3 R W
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Register Name ICSYS R W Reserved Bit 7 6 5 4 3 2 1 Bit 0 SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ R Reserved W TIMTST R Timer Test Register W PTPSR R W PTMCPSR R W PBCTL R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 0 0 0 0 0 W PBFLG R PBEN R 0 0 0 0 0 0 0 PA3H7 PA3H6 PA3H5 PA3H4 PA3H3 PA3H2 PA3H1 PA3H0 PA2H7 PA2H6 PA2H5 PA2H
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Register Name TC1H (High) R Bit 7 6 5 4 3 2 1 Bit 0 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 W TC1H (Low) R W TC2H (High) R W TC2H (Low) R W TC3H (High) R W TC3H (Low) R W = Unimplemented or Reserved Figure 7-2.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.2 Timer Compare Force Register (CFORC) 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0 0 0 0 0 0 0 0 Reset Figure 7-4. Timer Compare Force Register (CFORC) Read or write: Anytime but reads will always return 0x0000 (1 state is transient). All bits reset to zero. Table 7-3.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.4 R W Reset Output Compare 7 Data Register (OC7D) 7 6 5 4 3 2 1 0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 0 0 0 0 0 0 0 0 Figure 7-6. Output Compare 7 Data Register (OC7D) Read or write: Anytime All bits reset to zero. Table 7-5.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.5 R W Reset Timer Count Register (TCNT) 15 14 13 12 11 10 9 8 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 0 0 0 0 0 0 0 0 Figure 7-7. Timer Count Register High (TCNT) R W Reset 7 6 5 4 3 2 1 0 TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 0 0 0 0 0 0 0 0 Figure 7-8. Timer Count Register Low (TCNT) Read: Anytime Write: Has no meaning or effect All bits reset to zero. Table 7-6.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.6 Timer System Control Register 1 (TSCR1) 7 R W Reset 6 5 4 3 TEN TSWAI TSFRZ TFFCA PRNT 0 0 0 0 0 2 1 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-9. Timer System Control Register 1 (TSCR1) Read or write: Anytime except PRNT bit is write once All bits reset to zero. Table 7-7. TSCR1 Field Descriptions Field Description 7 TEN Timer Enable 0 Disables the main timer, including the counter.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.7 R W Reset Timer Toggle On Overflow Register 1 (TTOV) 7 6 5 4 3 2 1 0 TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 0 0 0 0 0 0 0 0 Figure 7-10. Timer Toggle On Overflow Register 1 (TTOV) Read or write: Anytime All bits reset to zero. Table 7-8. TTOV Field Descriptions Field Description 7:0 TOV[7:0] Toggle On Overflow Bits — TOV97:0] toggles output compare pin on timer counter overflow.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.8 R W Reset Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2) 7 6 5 4 3 2 1 0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 0 0 0 0 0 0 0 0 Figure 7-11. Timer Control Register 1 (TCTL1) R W Reset 7 6 5 4 3 2 1 0 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 0 0 0 0 0 0 0 0 Figure 7-12. Timer Control Register 2 (TCTL2) Read or write: Anytime All bits reset to zero. Table 7-9.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.9 R W Reset Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4) 7 6 5 4 3 2 1 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 Figure 7-13. Timer Control Register 3 (TCTL3) R W Reset 7 6 5 4 3 2 1 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0 0 0 0 0 0 0 0 Figure 7-14. Timer Control Register 4 (TCTL4) Read or write: Anytime All bits reset to zero. Table 7-11.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.10 R W Reset Timer Interrupt Enable Register (TIE) 7 6 5 4 3 2 1 0 C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 0 0 0 0 0 Figure 7-15. Timer Interrupt Enable Register (TIE) Read or write: Anytime All bits reset to zero. The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register. Table 7-13.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.11 Timer System Control Register 2 (TSCR2) 7 R W Reset TOI 0 6 5 4 0 0 0 0 0 0 3 2 1 0 TCRE PR2 PR1 PR0 0 0 0 0 = Unimplemented or Reserved Figure 7-16. Timer System Control Register 2 (TSCR2) Read or write: Anytime All bits reset to zero. Table 7-14. TSCR2 Field Descriptions Field 7 TOI Description Timer Overflow Interrupt Enable 0 Timer overflow interrupt disabled. 1 Hardware interrupt requested when TOF flag set.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.12 R W Reset Main Timer Interrupt Flag 1 (TFLG1) 7 6 5 4 3 2 1 0 C7F C6F C5F C4F C3F C2F C1F C0F 0 0 0 0 0 0 0 0 Figure 7-17. Main Timer Interrupt Flag 1 (TFLG1) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.13 Main Timer Interrupt Flag 2 (TFLG2) 7 R W Reset TOF 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-18. Main Timer Interrupt Flag 2 (TFLG2) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.14 R W Reset Timer Input Capture/Output Compare Registers 0–7 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 7-19. Timer Input Capture/Output Compare Register 0 High (TC0) R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 7-20.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 7-26. Timer Input Capture/Output Compare Register 3 Low (TC3) R W Reset 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 7-27.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) R W Reset 15 14 13 12 11 10 9 8 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 0 0 0 0 0 0 0 Figure 7-33. Timer Input Capture/Output Compare Register 7 High (TC7) R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 7-34. Timer Input Capture/Output Compare Register 7 Low (TC7) Read: Anytime Write anytime for output compare function.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-18. PACTL Field Descriptions (continued) Field Description 5 PAMOD Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). 0 Event counter mode 1 Gated time accumulation mode 4 PEDGE Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1). Refer to Table 7-19. For PAMOD bit = 0 (event counter mode).
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.16 R Pulse Accumulator A Flag Register (PAFLG) 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 0 PAOVF PAIF 0 0 = Unimplemented or Reserved Figure 7-36. Pulse Accumulator A Flag Register (PAFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) R W Reset 7 6 5 4 3 2 1 0 PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 0 0 0 0 0 0 0 0 Figure 7-38. Pulse Accumulators Count Register 2 (PACN2) Read: Anytime Write: Anytime All bits reset to zero. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) When PACN1 overflows from 0x00FF to 0x0000, the interrupt flag PBOVF in PBFLG is set. Full count register access will take place in one clock cycle. NOTE A separate read/write for high byte and low byte will give a different result than accessing them as a word. When clocking pulse and write to the registers occurs simultaneously, write takes priority and the register is not incremented. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL) 7 R W Reset 6 5 MCZI MODMC RDMCL 0 0 0 4 3 0 0 ICLAT FLMC 0 0 2 1 0 MCEN MCPR1 MCPR0 0 0 0 Figure 7-41. 16-Bit Modulus Down-Counter Control Register (MCCTL) Read: Anytime Write: Anytime All bits reset to zero. Table 7-22. MCCTL Field Descriptions Field 7 MCZI Description Modulus Counter Underflow Interrupt Enable 0 Modulus counter interrupt is disabled.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-23. Modulus Counter Prescaler Select 7.3.2.20 W Reset MCPR0 Prescaler Division 0 0 1 0 1 4 1 0 8 1 1 16 16-Bit Modulus Down-Counter FLAG Register (MCFLG) 7 R MCPR1 MCZF 0 6 5 4 3 2 1 0 0 0 0 POLF3 POLF2 POLF1 POLF0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 7-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG) Read: Anytime Write only used in the flag clearing mechanism for bit 7.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.21 R ICPAR — Input Control Pulse Accumulators Register (ICPAR) 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PA3EN PA2EN PA1EN PA0EN 0 0 0 0 = Unimplemented or Reserved Figure 7-43. Input Control Pulse Accumulators Register (ICPAR) Read: Anytime Write: Anytime. All bits reset to zero. The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN is set, PA3EN and PA2EN have no effect.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.22 R W Reset Delay Counter Control Register (DLYCT) 7 6 5 4 3 2 1 0 DLY7 DLY6 DLY5 DLY4 DLY3 DLY2 DLY1 DLY0 0 0 0 0 0 0 0 0 Figure 7-44. Delay Counter Control Register (DLYCT) Read: Anytime Write: Anytime All bits reset to zero. Table 7-26. DLYCT Field Descriptions Field 7:0 DLY[7:0] Description Delay Counter Select — When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to calculate the delay.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.23 R W Reset Input Control Overwrite Register (ICOVW) 7 6 5 4 3 2 1 0 NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 0 0 0 0 0 0 0 0 Figure 7-45. Input Control Overwrite Register (ICOVW) Read: Anytime Write: Anytime All bits reset to zero. Table 7-29.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.24 R W Reset Input Control System Control Register (ICSYS) 7 6 5 4 3 2 1 0 SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ 0 0 0 0 0 0 0 0 Figure 7-46. Input Control System Register (ICSYS) Read: Anytime Write: Once in normal modes All bits reset to zero. Table 7-30.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-30. ICSYS Field Descriptions (continued) Field Description 0 LATQ Input Control Latch or Queue Mode Enable — The BUFEN control bit should be set in order to enable the IC and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled. Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set will produce latching of input capture and pulse accumulators registers into their holding registers.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-32. Precision Timer Prescaler Selection Examples when PRNT = 1 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Prescale Factor 0 0 0 0 0 1 1 1 8 0 0 0 0 1 1 1 1 16 0 0 0 1 1 1 1 1 32 0 0 1 1 1 1 1 1 64 0 1 1 1 1 1 1 1 128 1 1 1 1 1 1 1 1 256 7.3.2.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Table 7-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 (continued) PTMPS7 PTMPS6 PTMPS5 PTMPS4 PTMPS3 PTMPS2 PTMPS1 PTMPS0 Prescaler Division Rate 0 0 0 0 0 1 1 1 8 0 0 0 0 1 1 1 1 16 0 0 0 1 1 1 1 1 32 0 0 1 1 1 1 1 1 64 0 1 1 1 1 1 1 1 128 1 1 1 1 1 1 1 1 256 7.3.2.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.28 R Pulse Accumulator B Flag Register (PBFLG) 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 1 PBOVF 0 0 0 0 = Unimplemented or Reserved Figure 7-50. Pulse Accumulator B Flag Register (PBFLG) Read: Anytime Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not affect the current status of the bit.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.29 R 8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H) 7 6 5 4 3 2 1 0 PA3H7 PA3H6 PA3H5 PA3H4 PA3H3 PA3H2 PA3H1 PA3H0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 7-51. 8-Bit Pulse Accumulators Holding Register 3 (PA3H) R 7 6 5 4 3 2 1 0 PA2H7 PA2H6 PA2H5 PA2H4 PA2H3 PA2H2 PA2H1 PA2H0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 7-52.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.30 R W Reset Modulus Down-Counter Count Register (MCCNT) 15 14 13 12 11 10 9 8 MCCNT15 MCCNT14 MCCNT13 MCCNT12 MCCNT11 MCCNT10 MCCNT9 MCCNT8 1 1 1 1 1 1 1 1 Figure 7-55. Modulus Down-Counter Count Register High (MCCNT) R W Reset 7 6 5 4 3 2 1 0 MCCNT7 MCCNT6 MCCNT5 MCCNT4 MCCNT3 MCCNT2 MCCNT1 MCCNT9 1 1 1 1 1 1 1 1 Figure 7-56.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.3.2.31 R Timer Input Capture Holding Registers 0–3 (TCxH) 15 14 13 12 11 10 9 8 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 7-57. Timer Input Capture Holding Register 0 High (TC0H) R 7 6 5 4 3 2 1 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 7-58.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) R 15 14 13 12 11 10 9 8 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 7-63. Timer Input Capture Holding Register 3 High (TC3H) R 7 6 5 4 3 2 1 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 7-64. Timer Input Capture Holding Register 3 Low (TC3H) Read: Anytime Write: Has no effect. All bits reset to zero.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Bus Clock ÷ 1, 4, 8, 16 Bus Clock Timer Prescaler 16-Bit Load Register 16-Bit Modulus Down Counter Modulus Prescaler 0 P0 Comparator Pin Logic Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 P1 Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg. PA1H Hold Reg. Pin Logic Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 TC2H Hold Reg. PA2H Hold Reg.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Bus Clock ÷ 1, 2,3, ..., 256 Bus Clock Timer Prescaler 16-Bit Load Register 16-Bit Modulus Down Counter Modulus Prescaler 0 P0 RESET Underflow 16-Bit Free-Running 16 BITMain MAINTimer TIMER ÷ 1, 2,3, ..., 256 Comparator Pin Logic Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 8, 12, 16, ..., 1024 0 P1 RESET Comparator Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 16-Bit Free-Running 16 BITMain MAIN TIMER Timer ÷ 1, 4, 8, 16 Bus Clock 16-Bit Load Register 16-Bit Modulus Down Counter Modulus Prescaler 0 Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg. PA1H Hold Reg. 0 P2 P4 Pin Logic Delay Counter EDG2 TC2 Capture/Compare Reg. PAC2 TC2H Hold Reg. PA2H Hold Reg.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) ÷1, 2, 3, ... 256 Bus Clock 16-Bit Free-Running 16 BITMain MAIN TIMER Timer Timer Prescaler ÷ 1, 2, 3, ... 256 16-Bit Load Register Modulus Prescaler 16-Bit Modulus Down Counter Bus Clock 0 P0 RESET Comparator Pin Logic Delay Counter EDG0 TC0 Capture/Compare Reg. PAC0 TC0H Hold Reg. PA0H Hold Reg. 0 P1 LATCH0 8, 12, 16, ... 1024 RESET Comparator Pin Logic Delay Counter EDG1 TC1 Capture/Compare Reg. PAC1 TC1H Hold Reg.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) Load Holding Register and Reset Pulse Accumulator 0 8, 12,16, ..., 1024 8-Bit PAC0 (PACN0) EDG0 P0 Edge Detector Delay Counter PA0H Holding Register Interrupt 0 8, 12,16, ..., 1024 EDG1 P1 Edge Detector 8-Bit PAC1 (PACN1) Delay Counter PA1H Holding Register 0 8, 12,16, ..., 1024 EDG2 P2 Edge Detector 8-Bit PAC2 (PACN2) Delay Counter PA2H Holding Register Interrupt 8, 12,16, ...
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) TIMCLK (Timer Clock) CLK1 CLK0 PACLK / 256 Clock Select (PAMOD) PACLK PACLK / 65536 Prescaled Clock (PCLK) 4:1 MUX Edge Detector P7 Interrupt 8-Bit PAC3 (PACN3) 8-Bit PAC2 (PACN2) MUX PACA Bus Clock Divide by 64 Interrupt 8-Bit PAC1 (PACN1) 8-Bit PAC0 (PACN0) Delay Counter PACB Edge Detector P0 Figure 7-70.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.4.1 Enhanced Capture Timer Modes of Operation The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12 standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the IOSx bit in TIOS register, they are called input capture (IC) channels.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding register cannot be written by an event unless they are empty (see Section 7.4.1.1, “IC Channels”). This will prevent the captured value from being overwritten until it is read or latched in the holding register. 2. IC Queue Mode (LATQ = 0) The main timer value is memorized in the IC register by a valid input pin transition (see Figure 7-67 and Figure 7-68).
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.4.1.2 OC Channel Initialization Internal register whose output drives OCx when TIOS is set, can be force loaded with a desired data by writing to CFORC register before OCx is configured for output compare action. This allows a glitch free switch over of port from general purpose I/O to timer output once the output compare is enabled. 7.4.1.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.4.1.5 Precision Timer By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter and modulus down counter and enhance delay counter settings compared to the settings in the present ECT timer. 7.4.1.6 Flag Clearing Mechanisms The flags in the ECT can be cleared one of two ways: 1.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) 7.4.3 Interrupts This section describes interrupts originated by the ECT block. The MCU must service the interrupt requests. Table 7-37 lists the interrupts generated by the ECT to communicate with the MCU. Table 7-37.
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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.1 Introduction The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11 with some of the enhancements incorporated on the HC12: center aligned output mode and four available clock sources.The PWM module has eight channels with independent control of left and center aligned outputs on each channel. Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.1.3 Block Diagram Figure 8-1 shows the block diagram for the 8-bit 8-channel PWM block.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.2.3 PWM5 — PWM Channel 5 This pin serves as waveform output of PWM channel 5. 8.2.4 PWM4 — PWM Channel 4 This pin serves as waveform output of PWM channel 4. 8.2.5 PWM3 — PWM Channel 3 This pin serves as waveform output of PWM channel 3. 8.2.6 PWM3 — PWM Channel 2 This pin serves as waveform output of PWM channel 2. 8.2.7 PWM3 — PWM Channel 1 This pin serves as waveform output of PWM channel 1. 8.2.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. 8.3.2 Register Descriptions This section describes in detail all the registers and register bits in the PWM module.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Register Name PWMCNT0 PWMCNT1 PWMCNT2 PWMCNT3 PWMCNT4 PWMCNT5 PWMCNT6 PWMCNT7 PWMPER0 Bit 7 6 5 4 3 2 1 Bit 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 R Bit 7 6 5 4 3 2 1
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Register Name PWMPER7 R W PWMDTY0 R W PWMDTY1 R W PWMDTY2 R W PWMDTY3 R W PWMDTY4 R W PWMDTY5 R W PWMDTY6 R W PWMDTY7 R W PWMSDN R W Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts off for power savings. R W Reset 7 6 5 4 3 2 1 0 PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 0 0 0 0 0 0 0 0 Figure 8-3. PWM Enable Register (PWME) Read: Anytime Write: Anytime Table 8-1.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.3.2.2 PWM Polarity Register (PWMPOL) The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 8-3. PWMCLK Field Descriptions Field Description 7 PCLK7 Pulse Width Channel 7 Clock Select 0 Clock B is the clock source for PWM channel 7. 1 Clock SB is the clock source for PWM channel 7.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 8-4. PWMPRCLK Field Descriptions Field Description 6–4 PCKB[2:0] Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channels 2, 3, 6, or 7. These three bits determine the rate of clock B, as shown in Table 8-5.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Read: Anytime Write: Anytime NOTE Write these bits only when the corresponding channel is disabled. Table 8-7. PWMCAE Field Descriptions Field 7–0 CAE[7:0] 8.3.2.6 Description Center Aligned Output Modes on Channels 7–0 0 Channels 7–0 operate in left aligned output mode. 1 Channels 7–0 operate in center aligned output mode. PWM Control Register (PWMCTL) The PWMCTL register provides for various control of the PWM module.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Table 8-8. PWMCTL Field Descriptions Field Description 7 CON67 Concatenate Channels 6 and 7 0 Channels 6 and 7 are separate 8-bit PWMs. 1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit PWM (bit 7 of port PWMP).
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 8-9. Reserved Register (PWMTST) Read: Always read $00 in normal modes Write: Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality. 8.3.2.8 Reserved Register (PWMPRSC) This register is reserved for factory testing of the PWM module and is not available in normal modes.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 8-11. PWM Scale A Register (PWMSCLA) Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLA value) 8.3.2.10 PWM Scale B Register (PWMSCLB) PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Writing to these registers when in special modes can alter the PWM functionality. 8.3.2.12 PWM Channel Counter Registers (PWMCNTx) Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register - 1.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active period due to the double buffering scheme. See Section 8.4.2.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. See Section 8.4.2.3, “PWM Period and Duty” for more information. NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Table 8-9. PWMSDN Field Descriptions Field Description 7 PWMIF PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will be flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect. 0 No change on PWM7IN input. 1 Change on PWM7IN input 6 PWMIE PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.4.1.1 Prescale The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode (freeze mode signal active) the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM. The input clock can also be disabled when all eight PWM channels are disabled (PWME7-0 = 0).
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Clock A PCKA2 PCKA1 PCKA0 Clock A/2, A/4, A/6,....A/512 8-Bit Down Counter Clock to PWM Ch 0 PCLK0 Count = 1 M U X Load PWMSCLA M U X Clock SA DIV 2 PCLK1 M U X M Clock to PWM Ch 1 Clock to PWM Ch 2 U PCLK2 M U X 2 4 8 16 32 64 128 Divide by Prescaler Taps: X PCLK3 Clock B Clock B/2, B/4, B/6,....
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.4.2 PWM Channel Timers The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count. 8.4.2.2 PWM Polarity Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. PPOLx = 0 PPOLx = 1 PWMDTYx Period = PWMPERx Figure 8-20.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) E = 100 ns Duty Cycle = 75% Period = 400 ns Figure 8-21. PWM Left Aligned Output Example Waveform 8.4.2.6 Center Aligned Outputs For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) As an example of a center aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 *100% = 75% Shown in Figure 8-23 is the output waveform generated. E = 100 ns E = 100 ns DUTY CYCLE = 75% PERIOD = 800 ns Figure 8-23. PWM Center Aligned Output Example Waveform 8.4.2.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Clock Source 7 High Low PWMCNT6 PWCNT7 Period/Duty Compare PWM7 Clock Source 5 High Low PWMCNT4 PWCNT5 Period/Duty Compare PWM5 Clock Source 3 High Low PWMCNT2 PWCNT3 Period/Duty Compare PWM3 Clock Source 1 High Low PWMCNT0 PWCNT1 Period/Duty Compare PWM1 Figure 8-24.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. Table 8-11 is used to summarize which channels are used to set the various control bits when in 16-bit mode. Table 8-11. 16-bit Concatenation Mode Summary 8.4.2.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) 8.6 Interrupts The PWM module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whenever the input level of the PWM7 channel changes while PWM7ENA = 1 or when PWMENA is being asserted while the level at PWM7 is active.
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.1 Introduction The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.1.2 Modes of Operation The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes. 9.1.3 Block Diagram The block diagram of the IIC module is shown in Figure 9-1. IIC Registers Start Stop Arbitration Control Clock Control In/Out Data Shift Register Interrupt bus_clock SCL SDA Address Compare Figure 9-1. IIC Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.2 External Signal Description The IICV2 module has two external pins. 9.2.1 IIC_SCL — Serial Clock Line Pin This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification. 9.2.2 IIC_SDA — Serial Data Line Pin This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification. 9.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.3.2.2 IIC Frequency Divider Register (IBFD) 7 6 5 4 3 2 1 0 IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 0 0 0 0 0 0 0 0 R W Reset = Unimplemented or Reserved Figure 9-4. IIC Bus Frequency Divider Register (IBFD) Read and write anytime Table 9-2. IBFD Field Descriptions Field Description 7:0 IBC[7:0] I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-4. Multiplier Factor IBC7-6 MUL 00 01 01 02 10 04 11 RESERVED The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Table 9-3, all subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Table 9-3.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 9-5.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-5.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-5.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-5.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-5.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-6. IBCR Field Descriptions Field Description 7 IBEN I-Bus Enable — This bit controls the software reset of the entire IIC bus module. 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Table 9-7. IBSR Field Descriptions (continued) Field Description 2 SRW Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.4 Functional Description This section provides a complete functional description of the IICV2. 9.4.1 I-Bus Protocol The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description SDA SCL START Condition STOP Condition Figure 9-10. Start and Stop Conditions 9.4.1.2 Slave Address Transmission The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal. 9.4.1.4 STOP Signal The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description WAIT Start Counting High Period SCL1 SCL2 SCL Internal Counter Reset Figure 9-11. IIC-Bus Clock Synchronization 9.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 9.4.1.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.5 Resets The reset state of each individual bit is listed in Section 9.3, “Memory Map and Register Definition,” which details the registers and their bit-fields. 9.6 Interrupts IICV2 uses only one interrupt vector. Table 9-8.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.7.1.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description 9.7.1.4 Generation of STOP A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal. 9.7.1.
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description Clear IBIF Master Mode ? Y TX N Arbitration Lost ? Y RX Tx/Rx ? N Last Byte Transmitted ? N Clear IBAL Y RXAK=0 ? N Last Byte To Be Read ? N Y N Y Y IAAS=1 ? IAAS=1 ? Y N Address Transfer End Of Addr Cycle (Master Rx) ? N Y Y (Read) 2nd Last Y Byte To Be Read ? SRW=1 ? Write Next Byte To IBDR Generate Stop Signal Set TXAK =1 Generate Stop Signal Read Data From IBDR And Store ACK From Receiver ? N Read Data From I
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Chapter 9 Inter-Integrated Circuit (IICV2) Block Description MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.1 Introduction Freescale’s scalable controller area network (S12MSCANV3) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.1.2 Block Diagram MSCAN Oscillator Clock Bus Clock CANCLK MUX Presc. Tq Clk Receive/ Transmit Engine RXCAN TXCAN Transmit Interrupt Req. Receive Interrupt Req. Errors Interrupt Req. Message Filtering and Buffering Control and Status Wake-Up Interrupt Req. Configuration Registers Wake-Up Low Pass Filter Figure 10-1. MSCAN Block Diagram 10.1.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • Internal timer for time-stamping of received and transmitted messages Three low-power modes: sleep, power down, and MSCAN enable Global initialization of configuration registers 10.1.4 Modes of Operation The following modes of operation are specific to the MSCAN. See Section 10.4, “Functional Description,” for details. • Listen-Only Mode • MSCAN Sleep Mode • MSCAN Initialization Mode • MSCAN Power Down Mode 10.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN node 2 CAN node 1 CAN node n MCU CAN Controller (MSCAN) TXCAN RXCAN Transceiver CAN_H CAN_L CAN Bus Figure 10-2. CAN System 10.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the MSCAN. 10.3.1 Module Memory Map Figure 10-3 gives an overview on all registers and their individual bits in the MSCAN memory map.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name 0x0002 CANBTR0 R 0x0003 CANBTR1 R 0x0004 CANRFLG R 0x0005 CANRIER 0x0006 CANTFLG 0x000D CANMISC 3 2 1 Bit 0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE 0 0 0 0 0 TXE2 TXE1 TXE0 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 0 0
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Register Name 0x0014–0x0017 CANIDMRx R 0x0018–0x001B CANIDAR4–7 R 0x001C–0x001F CANIDMR4–7 R 0x0020–0x002F CANRXFG R 0x0030–0x003F CANTXFG R W W W Bit 7 6 5 4 3 2 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 See Section 10.3.3, “Programmer’s Model of Message Storage” W See Section 10.3.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode). Table 10-1. CANCTL0 Register Field Descriptions Field Description 7 RXFRM1 Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-1. CANCTL0 Register Field Descriptions (continued) Field Description 1 SLPRQ5 Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 10.4.5.4, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 7 6 5 4 3 2 CANE CLKSRC LOOPB LISTEN BORM WUPM 0 0 0 1 0 0 R 1 0 SLPAK INITAK 0 1 W Reset: = Unimplemented Figure 10-5. MSCAN Control Register 1 (CANCTL1) Read: Anytime Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). Table 10-2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-2. CANCTL1 Register Field Descriptions (continued) Field Description 1 SLPAK Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see Section 10.4.5.4, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-5. Baud Rate Prescaler 10.3.2.4 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 0 3 0 0 0 0 1 1 4 : : : : : : : 1 1 1 1 1 1 64 MSCAN Bus Timing Register 1 (CANBTR1) The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-7. Time Segment 2 Values 1 TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle1 0 0 1 2 Tq clock cycles : : : : 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles This setting is not valid. Please refer to Table 10-35 for valid settings. Table 10-8.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored. Table 10-9.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-9. CANRFLG Register Field Descriptions (continued) Field Description 1 OVRIF Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected 0 RXF2 Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-10. CANRIER Register Field Descriptions Field 7 WUPIE1 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) R 7 6 5 4 3 0 0 0 0 0 2 1 0 TXE2 TXE1 TXE0 1 1 1 W Reset: 0 0 0 0 0 = Unimplemented Figure 10-10. MSCAN Transmitter Flag Register (CANTFLG) NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode Table 10-12. CANTIER Register Field Descriptions Field Description 2:0 TXEIE[2:0] 10.3.2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. R 7 6 5 4 3 2 1 0 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 10-13.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode Table 10-15.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only Table 10-16. CANIDAC Register Field Descriptions Field Description 5:4 IDAM[1:0] Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization (see Section 10.4.3, “Identifier Acceptance Filter”). Table 10-17 summarizes the different settings.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 10-16. MSCAN Reserved Register Read: Always read 0x0000 in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special modes can alter the MSCAN functionality. 10.3.2.14 MSCAN Miscellaneous Register (CANMISC) This register provides additional features.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) R 7 6 5 4 3 2 1 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 0 0 0 0 0 0 0 0 W Reset: = Unimplemented Figure 10-18.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7) On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 10.3.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-20. CANIDAR0–CANIDAR3 Register Field Descriptions Field Description 7:0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-21. CANIDAR4–CANIDAR7 Register Field Descriptions Field Description 7:0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. 10.3.2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 10-22. CANIDMR0–CANIDMR3 Register Field Descriptions Field Description 7:0 AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-23. CANIDMR4–CANIDMR7 Register Field Descriptions Field Description 7:0 AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 1 Not applicable for receive buffers Read-only for CPU 3 Read-only for CPU 2 Figure 10-24 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 10-25. All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 10-24. Receive/Transmit Message Buffer — Extended Identifier Mapping Register Name Bit 7 6 5 4 3 2 1 Bit0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 R IDR0 W MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Figure 10-24.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Read: For transmit buffers, anytime when TXEx flag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). For receive buffers, only when RXF flag is set (see Section 10.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”).
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-25. IDR0 Register Field Descriptions — Extended Field Description 7:0 ID[28:21] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 7 6 5 4 3 2 1 0 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR x x x x x x x x R W Reset: Figure 10-29. Identifier Register 3 (IDR3) — Extended Identifier Mapping Table 10-28. IDR3 Register Field Descriptions — Extended Field Description 7:1 ID[6:0] Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-30. IDR1 Register Field Descriptions Field Description 7:5 ID[2:0] Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 10-29.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Module Base + 0x0004 (DSR0) 0x0005 (DSR1) 0x0006 (DSR2) 0x0007 (DSR3) 0x0008 (DSR4) 0x0009 (DSR5) 0x000A (DSR6) 0x000B (DSR7) 7 6 5 4 3 2 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x x x x x x x R W Reset: Figure 10-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping Table 10-31. DSR0–DSR7 Register Field Descriptions Field Description 7:0 DB[7:0] Data bits 7:0 10.3.3.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-33. Data Length Codes Data Length Code 10.3.3.4 DLC3 DLC2 DLC1 DLC0 Data Byte Count 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 Transmit Buffer Priority Register (TBPR) This register defines the local priority of the associated message buffer.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) “MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been flagged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.4.2 Message Storage CAN Receive / Transmit Engine CPU12 Memory Mapped I/O Rx0 RXF Receiver TxBG Tx0 MSCAN TxFG Tx1 TxBG Tx2 Transmitter CPU bus RxFG RxBG MSCAN Rx1 Rx2 Rx3 Rx4 TXE0 PRIO TXE1 CPU bus PRIO TXE2 PRIO Figure 10-39. User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.4.2.1 Message Transmit Background Modern application layer software is built upon two fundamental assumptions: • Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 10.4.7.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • Four identifier acceptance filters, each to be applied to — a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or — b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 10-41 shows how the first 32-bit filter bank (CANIDAR0–CANIDA3, CANIDMR0–3CANIDMR) produces filter 0 and 1 hits.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.0A/B Standard Identifier ID10 IDR0 ID3 ID2 IDR1 AM7 CANIDMR0 AM0 AM7 CANIDMR1 AM0 AC7 CANIDAR0 AC0 AC7 CANIDAR1 AC0 ID15 IDE ID14 IDR2 ID7 ID6 IDR3 RTR ID10 IDR2 ID3 ID10 IDR3 ID3 ID Accepted (Filter 0 Hit) AM7 CANIDMR2 AM0 AM7 CANIDMR3 AM0 AC7 CANIDAR2 AC0 AC7 CANIDAR3 AC0 ID Accepted (Filter 1 Hit) Figure 10-41.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) CAN 2.0B Extended Identifier ID28 IDR0 ID21 ID20 IDR1 CAN 2.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.4.3.1 Protocol Violation Protection The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: • The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-34. Time Segment Syntax Syntax Description System expects transitions to occur on the CAN bus during this period. SYNC_SEG Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) 10.4.4.3 Emulation Modes In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification. 10.4.4.4 Listen-Only Mode In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a transmision.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) Table 10-36. CPU vs.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • • • If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • or the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices. In initialization mode, the MSCAN is stopped.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) • or CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a recessive state.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter. Table 10-37. Interrupt Vectors Interrupt Source 10.4.7.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) (CANTFLG).” Interrupts are pending as long as one of the corresponding flags is set. The flags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The flags are reset by writing a 1 to the corresponding bit position. A flag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) If the MSCAN is configured for user request (BORM set in Section 10.3.2.2, “MSCAN Control Register 1 (CANCTL1)”), the recovery from bus-off starts after both independent events have become true: • 128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored • BOHOLD in Section 10.3.2.14, “MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order.
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.1 Introduction This block guide provides an overview of the serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs. 11.1.
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Chapter 11 Serial Communication Interface (S12SCIV5) • • • • • • Programmable transmitter output parity Two receiver wakeup methods: — Idle line wakeup — Address mark wakeup Interrupt-driven operation with eight flags: — Transmitter empty — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN Receiver framing error detection Hardw
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Chapter 11 Serial Communication Interface (S12SCIV5) SCI Data Register RXD Data In Infrared Decoder Receive Shift Register IDLE Receive & Wakeup Control Bus Clock Baud Rate Generator Receive RDRF/OR Interrupt Generation BRKD RXEDG BERR Data Format Control 1/16 Transmit Control Transmit Shift Register SCI Interrupt Request Transmit TDRE Interrupt Generation TC Infrared Encoder Data Out TXD SCI Data Register Figure 11-1. SCI Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.2 External Signal Description The SCI module has a total of two external pins. 11.2.1 TXD — Transmit Pin The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled. 11.2.2 RXD — Receive Pin The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.1 R W Reset SCI Baud Rate Registers (SCIBDH, SCIBDL) 7 6 5 4 3 2 1 0 IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 0 0 0 0 0 0 0 0 Figure 11-3. SCI Baud Rate Register (SCIBDH) R W Reset 7 6 5 4 3 2 1 0 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0 0 0 0 0 0 0 0 Figure 11-4. SCI Baud Rate Register (SCIBDL) Read: Anytime, if AMAP = 0.
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Chapter 11 Serial Communication Interface (S12SCIV5) Table 11-2. IRSCI Transmit Pulse Width 11.3.2.2 R W Reset TNP[1:0] Narrow Pulse Width 11 1/4 10 1/32 01 1/16 00 3/16 SCI Control Register 1 (SCICR1) 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 Figure 11-5. SCI Control Register 1 (SCICR1) Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition). Table 11-3.
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Chapter 11 Serial Communication Interface (S12SCIV5) Table 11-3. SCICR1 Field Descriptions (continued) Field Description 2 ILT Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.3 SCI Alternative Status Register 1 (SCIASR1) 7 R W Reset RXEDGIF 0 6 5 4 3 2 0 0 0 0 BERRV 0 0 0 0 0 1 0 BERRIF BKDIF 0 0 = Unimplemented or Reserved Figure 11-6. SCI Alternative Status Register 1 (SCIASR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 11-5.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.4 SCI Alternative Control Register 1 (SCIACR1) 7 R W Reset RXEDGIE 0 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 1 0 BERRIE BKDIE 0 0 = Unimplemented or Reserved Figure 11-7. SCI Alternative Control Register 1 (SCIACR1) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 11-6.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.5 R SCI Alternative Control Register 2 (SCIACR2) 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 W Reset 2 1 0 BERRM1 BERRM0 BKDFE 0 0 0 = Unimplemented or Reserved Figure 11-8. SCI Alternative Control Register 2 (SCIACR2) Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 11-7. SCIACR2 Field Descriptions Field Description 2:1 Bit Error Mode — Those two bits determines the functionality of the bit error detect feature.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.6 R W Reset SCI Control Register 2 (SCICR2) 7 6 5 4 3 2 1 0 TIE TCIE RIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Figure 11-9. SCI Control Register 2 (SCICR2) Read: Anytime Write: Anytime Table 11-9. SCICR2 Field Descriptions Field 7 TIE Description Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.7 SCI Status Register 1 (SCISR1) The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.
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Chapter 11 Serial Communication Interface (S12SCIV5) Table 11-10. SCISR1 Field Descriptions (continued) Field Description 3 OR Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.8 SCI Status Register 2 (SCISR2) 7 R W Reset AMAP 0 6 5 0 0 0 0 4 3 2 1 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 RAF 0 = Unimplemented or Reserved Figure 11-11. SCI Status Register 2 (SCISR2) Read: Anytime Write: Anytime Table 11-11. SCISR2 Field Descriptions Field Description 7 AMAP Alternative Map — This bit controls which registers sharing the same address space are accessible.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.3.2.9 SCI Data Registers (SCIDRH, SCIDRL) 7 R 6 R8 W Reset 0 T8 0 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 11-12. SCI Data Registers (SCIDRH) 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 0 Reset Figure 11-13.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.4 Functional Description This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 11-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.1 Infrared Interface Submodule This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.3 Data Format The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 11-15 below.
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Chapter 11 Serial Communication Interface (S12SCIV5) 1 11.4.4 The address bit identifies the frame as an address character. See Section 11.4.6.6, “Receiver Wakeup”. Baud Rate Generation A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL).
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.
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Chapter 11 Serial Communication Interface (S12SCIV5) The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this flag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate.
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Chapter 11 Serial Communication Interface (S12SCIV5) When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out.
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Chapter 11 Serial Communication Interface (S12SCIV5) Figure 11-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.5.5 LIN Transmit Collision Detection This module allows to check for collisions on the LIN bus. LIN Physical Interface Synchronizer Stage Receive Shift Register Compare RXD Pin Bit Error LIN Bus Bus Clock Sample Point Transmit Shift Register TXD Pin Figure 11-18.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.
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Chapter 11 Serial Communication Interface (S12SCIV5) indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request. 11.4.6.3 Data Sampling The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
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Chapter 11 Serial Communication Interface (S12SCIV5) To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 11-17 summarizes the results of the data bit samples. Table 11-17. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 NOTE The RT8, RT9, and RT10 samples do not affect start bit verification.
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Chapter 11 Serial Communication Interface (S12SCIV5) In Figure 11-22 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
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Chapter 11 Serial Communication Interface (S12SCIV5) In Figure 11-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
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Chapter 11 Serial Communication Interface (S12SCIV5) Figure 11-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.6.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.6.5.2 Fast Data Tolerance Figure 11-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. Stop Idle or Next Frame RT16 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 Receiver RT Clock Data Samples Figure 11-29.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.4.6.6.1 Idle Input line Wakeup (WAKE = 0) In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state.
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Chapter 11 Serial Communication Interface (S12SCIV5) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.5.2.2 Wait Mode SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). • If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. • If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.5.3.1 Description of Interrupt Operation The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port. 11.
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Chapter 11 Serial Communication Interface (S12SCIV5) 11.5.3.1.6 RXEDGIF Description The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1. 11.5.3.1.7 BERRIF Description The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.1 Introduction The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven. 12.1.1 Glossary of Terms SPI SS SCK MOSI MISO MOMI SISO 12.1.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) • SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) SPI 2 SPI Control Register 1 BIDIROE 2 SPI Control Register 2 SPC0 SPI Status Register Slave Control SPIF MODF SPTEF CPOL CPHA Phase + SCK In Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK Out Polarity Control Interrupt Control SPI Interrupt Request Baud Rate Generator Master Control Counter Bus Clock 3 SPR Port Control Logic SCK SS Prescaler Clock Select SPPR MOSI Baud Rate Shift Clock Sample Clock 3 Shifter SPI Baud Rate
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.2.3 SS — Slave Select Pin This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave. 12.2.4 SCK — Serial Clock Pin In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock. 12.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.3.2 Register Descriptions This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.3.2.1 R W Reset SPI Control Register 1 (SPICR1) 7 6 5 4 3 2 1 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 0 0 1 0 0 Figure 12-3. SPI Control Register 1 (SPICR1) Read: Anytime Write: Anytime Table 12-1. SPICR1 Field Descriptions Field Description 7 SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) Table 12-2. SS Input / Output Selection 12.3.2.2 R MODFEN SSOE Master Mode Slave Mode 0 0 SS not used by SPI SS input 0 1 SS not used by SPI SS input 1 0 SS input with MODF feature SS input 1 1 SS is slave select output SS input SPI Control Register 2 (SPICR2) 7 6 5 0 0 0 0 0 0 W Reset 4 3 MODFEN BIDIROE 0 0 2 0 0 1 0 SPISWAI SPC0 0 0 = Unimplemented or Reserved Figure 12-4.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) Table 12-4. Bidirectional Pin Configurations Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal 0 Bidirectional 1 X Master In Master Out 0 MISO not used by SPI Master In 1 Master I/O Slave Mode of Operation 12.3.2.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) Table 12-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 0 0 0 0 2 12.5 MHz 0 0 0 0 0 1 4 6.25 MHz 0 0 0 0 1 0 8 3.125 MHz 0 0 0 0 1 1 16 1.5625 MHz 0 0 0 1 0 0 32 781.25 kHz 0 0 0 1 0 1 64 390.63 kHz 0 0 0 1 1 0 128 195.31 kHz 0 0 0 1 1 1 256 97.66 kHz 0 0 1 0 0 0 4 6.25 MHz 0 0 1 0 0 1 8 3.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) Table 12-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 1 0 0 1 1 1 1280 19.53 kHz 1 0 1 0 0 0 12 2.08333 MHz 1 0 1 0 0 1 24 1.04167 MHz 1 0 1 0 1 0 48 520.83 kHz 1 0 1 0 1 1 96 260.42 kHz 1 0 1 1 0 0 192 130.21 kHz 1 0 1 1 0 1 384 65.10 kHz 1 0 1 1 1 0 768 32.55 kHz 1 0 1 1 1 1 1536 16.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.3.2.4 R SPI Status Register (SPISR) 7 6 5 4 3 2 1 0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 12-6. SPI Status Register (SPISR) Read: Anytime Write: Has no effect Table 12-7. SPISR Field Descriptions Field Description 7 SPIF SPIF Interrupt Flag — This bit is set after a received data byte has been transferred into the SPI data register.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.3.2.5 R W Reset SPI Data Register (SPIDR) 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 2 Bit 0 0 0 0 0 0 0 0 0 Figure 12-7. SPI Data Register (SPIDR) Read: Anytime; normally read only when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) Data A Received Data B Received Data C Received SPIF Serviced Receive Shift Register Data B Data A Data C SPIF SPI Data Register Data B Data A = Unspecified Data C = Reception in progress Figure 12-8.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4 Functional Description The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.1 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear. • Serial clock In slave mode, SCK is the SPI clock input from the master. • MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2. • SS pin The SS pin is the slave select input.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.3 Transmission Formats During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After the 16th (last) SCK edge: • Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI data register is not transmitted; instead the last received byte is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the SPI data register is transmitted.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) End of Idle State Begin SCK Edge Number 1 2 3 4 End Transfer 5 6 7 8 9 10 11 12 13 14 Begin of Idle State 15 16 SCK (CPOL = 0) SCK (CPOL = 1) If next transfer begins here SAMPLE I MOSI/MISO CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tT tL tI tL MSB first (LSBFE = 0): LSB first (LSBFE = 1): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK for tT, tl, tL LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MS
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.4 SPI Baud Rate Generation Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0).
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.5.2 Bidirectional Mode (MOMI or SISO) The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (see Table 12-8). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.6 Error Conditions The SPI has one error condition: • Mode fault error 12.4.6.1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the MODFEN bit is set.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.7.2 SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2. • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode • If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) 12.4.7.4 Reset The reset values of registers and signals are described in Section 12.3, “Memory Map and Register Definition”, which details the registers and their bit fields. • If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. • Reading from the SPIDR after reset will always read a byte of zeros. 12.4.7.
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Chapter 12 Serial Peripheral Interface (S12SPIV4) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.1 Introduction The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules or raise periodic interrupts. Refer to Figure 13-1 for a simplified block diagram. 13.1.1 Glossary Acronyms and Abbreviations PIT ISR CCR SoC micro time bases 13.1.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register. In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates like in run mode. In wait mode, if the PITSWAI bit is set, the PIT module is stalled. Stop mode In full stop mode or pseudo stop mode, the PIT module is stalled.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.3 Memory Map and Register Definition This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) Register Name PITLD1 (Low) R W PITCNT1 (High) R W PITCNT1 (Low) R W PITLD2 (High) R W PITLD2 (Low) R W PITCNT2 (High) R W PITCNT2 (Low) R W PITLD3 (High) R W PITLD3 (Low) R W PITCNT3 (High) R W PITCNT3 (Low) R W Bit 7 6 5 4 3 2 1 Bit 0 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 PLD15 PLD14 PLD13 PLD12 PLD11
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.3.0.1 PIT Control and Force Load Micro Timer Register (PITCFLMT) 7 R W Reset 6 5 PITE PITSWAI PITFRZ 0 0 0 4 3 2 1 0 0 0 0 0 0 PFLMT1 PFLMT0 0 0 0 0 0 = Unimplemented or Reserved Figure 13-3. PIT Control and Force Load Micro Timer Register (PITCFLMT) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 13-1.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.3.0.2 R PIT Force Load Timer Register (PITFLT) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 PFLT3 PFLT2 PFLT1 PFLT0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 13-4. PIT Force Load Timer Register (PITFLT) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 13-2.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.3.0.4 R PIT Multiplex Register (PITMUX) 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PMUX3 PMUX2 PMUX1 PMUX0 0 0 0 0 = Unimplemented or Reserved Figure 13-6. PIT Multiplex Register (PITMUX) Read: Anytime Write: Anytime; writes to the reserved bits have no effect Table 13-4.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.3.0.6 R PIT Time-Out Flag Register (PITTF) 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 PTF3 PTF2 PTF1 PTF0 0 0 0 0 = Unimplemented or Reserved Figure 13-8. PIT Time-Out Flag Register (PITTF) Read: Anytime Write: Anytime (write to clear); writes to the reserved bits have no effect Table 13-6.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.3.0.8 PIT Load Register 0 to 3 (PITLD0–3) 15 R W 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 Figure 13-11.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.3.0.9 PIT Count Register 0 to 3 (PITCNT0–3) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT PCNT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 W 15 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 Figure 13-15.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) 13.4 Functional Description Figure 13-19 shows a detailed block diagram of the PIT module. The main parts of the PIT are status, control and data registers, two 8-bit down-counters, four 16-bit down-counters and an interrupt/trigger interface.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the PITLD register is reloaded and the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set, as shown in Figure 13-20. The time-out period is a function of the timer load (PITLD) and micro timer load (PITMTLD) registers and the bus clock fBUS: time-out period = (PITMTLD + 1) * (PITLD + 1) / fBUS.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) is set, an interrupt service is requested whenever the corresponding time-out flag PTF in the PIT time-out flag (PITTF) register is set. The flag can be cleared by writing a one to the flag bit. NOTE Be careful when resetting the PITE, PINTE or PITCE bits in case of pending PIT interrupt requests, to avoid spurious interrupt requests. 13.4.
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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.1 Introduction Module VREG_3V3 is a dual output voltage regulator that provides two separate 2.5V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3V up to 5V (typical). 14.1.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.1.3 Block Diagram Figure 14-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core REG consists of two parallel subblocks, REG1 and REG2, providing two independent output voltages.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.2 External Signal Description Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply voltages, most signals are power supply signals connected to pads. Table 14-1 shows all signals of VREG_3V3 associated with pins. Table 14-1.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins Signals VDDPLL/VSSPLL are the secondary outputs of VREG_3V3 that provide the power supply for the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic). In Shutdown Mode, an external supply driving VDDPLL/VSSPLL can replace the voltage regulator. 14.2.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.3.2 Register Descriptions This section describes all the VREG_3V3 registers and their individual bits. 14.3.2.1 HT Control Register (VREGHTCL) The VREGHTCL is reserved for test purposes. This register should not be written. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 14-2. HT Control Register (VREGHTCL) 14.3.2.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.3.2.3 Autonomous Periodical Interrupt Control Register (VREGAPICL) The VREGAPICL register allows the configuration of the VREG_3V3 autonomous periodical interrupt features. 7 R W Reset APICLK 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 APIFE APIE APIF 0 0 0 = Unimplemented or Reserved Figure 14-4. Autonomous Periodical Interrupt Control Register (VREGAPICL) Table 14-4.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.3.2.4 Autonomous Periodical Interrupt Trimming Register (VREGAPITR) The VREGAPITR register allows to trim the API timeout period. 7 R W Reset 6 5 4 3 2 APITR5 APITR4 APITR3 APITR2 APITR1 APITR0 01 01 01 01 01 01 1 0 0 0 0 0 1. Reset value is either 0 or preset by factory. See Device User Guide for details. = Unimplemented or Reserved Figure 14-5. Autonomous Periodical Interrupt Trimming Register (VREGAPITR) Table 14-5.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.3.2.5 Autonomous Periodical Interrupt Rate High and Low Register (VREGAPIRH / VREGAPIRL) The VREGAPIRH and VREGAPIRL register allows the configuration of the VREG_3V3 autonomous periodical interrupt rate. R 7 6 5 4 0 0 0 0 0 0 0 0 W Reset 3 2 1 0 APIR11 APIR10 APIR9 APIR8 0 0 0 0 = Unimplemented or Reserved Figure 14-6.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) Table 14-8. Selectable Autonomous Periodical Interrupt Periods 1 APICLK APIR[11:0] Selected Period 0 000 0.2 ms1 0 001 0.4 ms1 0 002 0.6 ms1 0 003 0.8 ms1 0 004 1.0 ms1 0 005 1.2 ms1 0 ..... ..... 0 FFD 818.8 ms1 0 FFE 819 ms1 0 FFF 819.2 ms1 1 000 2 * bus clock period 1 001 4 * bus clock period 1 002 6 * bus clock period 1 003 8 * bus clock period 1 004 10 * bus clock period 1 005 12 * bus clock period 1 ....
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.3.2.6 Reserved 06 The Reserved 06 is reserved for test purposes. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 14-8. Reserved 06 14.3.2.7 Reserved 07 The Reserved 07 is reserved for test purposes. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 14-9. Reserved 07 14.4 Functional Description 14.4.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) 14.4.2.2 Reduced Power Mode In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to reduce power consumption. 14.4.3 Low-Voltage Detect (LVD) Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input voltage (VDDA–VSSA) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever status flag LVDS changes its value.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. See Table 14-6 for the trimming effect of APITR. NOTE The first period after enabling the counter by APIFE might be reduced. The API internal RC oscillator clock is not available if VREG_3V3 is in Shutdown Mode. 14.4.8 Resets This section describes how VREG_3V3 controls the reset of the MCU.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) Table 14-10. Interrupt Vectors Interrupt Source Local Enable Autonomous periodical interrupt (API) APIE = 1 14.4.10.1 Low-Voltage Interrupt (LVI) In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID.
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Chapter 14 Voltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 15 Background Debug Module (S12XBDMV2) 15.1 Introduction This section describes the functionality of the background debug module (BDM) sub-block of the HCS12X core platform. The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin.
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Chapter 15 Background Debug Module (S12XBDMV2) • • • • • • • • Software control of BDM operation during wait mode Software selectable clocks Global page access functionality Enabled but not active out of reset in emulation modes CLKSW bit set out of reset in emulation mode. When secured, hardware commands are allowed to access the register space in special single chip mode, if the Flash and EEPROM erase tests fail.
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Chapter 15 Background Debug Module (S12XBDMV2) 15.1.2.3 Low-Power Modes The BDM can be used until all bus masters (e.g., CPU or XGATE) are in stop mode. When CPU is in a low power mode (wait or stop mode) all BDM firmware commands as well as the hardware BACKGROUND command can not be used respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also the CPU can not enter a low power mode during BDM active mode.
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Chapter 15 Background Debug Module (S12XBDMV2) 15.2 External Signal Description A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode. 15.3 15.3.
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Chapter 15 Background Debug Module (S12XBDMV2) 15.3.2 Register Descriptions A summary of the registers associated with the BDM is shown in Figure 15-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
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Chapter 15 Background Debug Module (S12XBDMV2) 15.3.2.
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Chapter 15 Background Debug Module (S12XBDMV2) Table 15-2. BDMSTS Field Descriptions (continued) Field Description 6 BDMACT BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map.
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Chapter 15 Background Debug Module (S12XBDMV2) Table 15-3. BDM Clock Sources PLLSEL CLKSW 0 0 Bus clock dependent on oscillator 0 1 Bus clock dependent on oscillator 1 0 Alternate clock (refer to the device specification to determine the alternate clock source) 1 1 Bus clock dependent on the PLL 15.3.2.
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Chapter 15 Background Debug Module (S12XBDMV2) 15.3.2.3 BDM CCR HIGH Holding Register (BDMCCRH) Register Global Address 0x7FFF07 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 W Reset 2 1 0 CCR10 CCR9 CCR8 0 0 0 = Unimplemented or Reserved Figure 15-5.
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Chapter 15 Background Debug Module (S12XBDMV2) 15.4 Functional Description The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands: hardware and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 15.4.3, “BDM Hardware Commands”. Target system memory includes all memory that is accessible by the CPU.
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Chapter 15 Background Debug Module (S12XBDMV2) After being enabled, BDM is activated by one of the following1: • Hardware BACKGROUND command • CPU BGND instruction • External instruction tagging mechanism2 • Breakpoint force or tag mechanism2 When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table.
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Chapter 15 Background Debug Module (S12XBDMV2) Table 15-5. Hardware Commands Opcode (hex) Data BACKGROUND 90 None Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. ACK_ENABLE D5 None Enable Handshake. Issues an ACK pulse after the command is executed. ACK_DISABLE D6 None Disable Handshake. This command does not issue an ACK pulse.
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Chapter 15 Background Debug Module (S12XBDMV2) Table 15-6. Firmware Commands Command1 Opcode (hex) Data Description READ_NEXT2 62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator. READ_X 65 16-bit data out Read X index register. READ_Y 66 16-bit data out Read Y index register. READ_SP 67 16-bit data out Read stack pointer.
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Chapter 15 Background Debug Module (S12XBDMV2) 15.4.5 BDM Command Structure Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB.
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Chapter 15 Background Debug Module (S12XBDMV2) The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table.
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Chapter 15 Background Debug Module (S12XBDMV2) 15.4.6 BDM Serial Interface The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see Section 15.3.2.1, “BDM Status Register (BDMSTS)”.
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Chapter 15 Background Debug Module (S12XBDMV2) BDM Clock (Target MCU) Host Transmit 1 Host Transmit 0 Perceived Start of Bit Time Target Senses Bit Earliest Start of Next Bit 10 Cycles Synchronization Uncertainty Figure 15-8. BDM Host-to-Target Serial Bit Timing The receive cases are more complicated. Figure 15-9 shows the host receiving a logic 1 from the target system.
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Chapter 15 Background Debug Module (S12XBDMV2) Figure 15-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it.
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Chapter 15 Background Debug Module (S12XBDMV2) compared to the serial communication rate. This protocol allows a great flexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication.
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Chapter 15 Background Debug Module (S12XBDMV2) Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware handshake protocol in Figure 15-11 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin.
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Chapter 15 Background Debug Module (S12XBDMV2) GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin.
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Chapter 15 Background Debug Module (S12XBDMV2) Figure 15-14 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command.
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Chapter 15 Background Debug Module (S12XBDMV2) The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued.
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Chapter 15 Background Debug Module (S12XBDMV2) within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication.
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Chapter 15 Background Debug Module (S12XBDMV2) stop mode has been reached. Hence after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command. 15.4.11 Serial Communication Time Out The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued.
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Chapter 15 Background Debug Module (S12XBDMV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 16 Interrupt (S12XINTV1) 16.1 Introduction The XINT module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to either the CPU or the XGATE module.
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Chapter 16 Interrupt (S12XINTV1) 16.1.1 Glossary The following terms and abbreviations are used in the document. Table 16-1. Terminology Term CCR DMA INT IPL ISR MCU XGATE IRQ XIRQ 16.1.
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Chapter 16 Interrupt (S12XINTV1) • • • Wait mode In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 16.5.3, “Wake Up from Stop or Wait Mode” for details. Stop Mode In stop mode, the XINT module is frozen. It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to Section 16.5.
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Chapter 16 Interrupt (S12XINTV1) 16.1.4 Block Diagram Figure 16-1 shows a block diagram of the XINT module.
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Chapter 16 Interrupt (S12XINTV1) 16.2 External Signal Description The XINT module has no external signals. 16.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the XINT. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 16 Interrupt (S12XINTV1) 16.3.1 Register Descriptions This section describes in address order all the XINT registers and their individual bits.
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Chapter 16 Interrupt (S12XINTV1) 16.3.1.1 Interrupt Vector Base Register (IVBR) Address: 0x0121 7 6 5 R 3 2 1 0 1 1 1 IVB_ADDR[7:0] W Reset 4 1 1 1 1 1 Figure 16-3. Interrupt Vector Base Register (IVBR) Read: Anytime Write: Anytime Table 16-2. IVBR Field Descriptions Field Description 7–0 Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e.
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Chapter 16 Interrupt (S12XINTV1) 16.3.1.2 XGATE Interrupt Priority Configuration Register (INT_XGPRIO) Address: 0x0126 R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 2 0 0 XILVL[2:0] W Reset 1 0 0 1 = Unimplemented or Reserved Figure 16-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO) Read: Anytime Write: Anytime Table 16-3.
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Chapter 16 Interrupt (S12XINTV1) 16.3.1.3 Interrupt Request Configuration Address Register (INT_CFADDR) Address: 0x0127 7 6 R 4 INT_CFADDR[7:4] W Reset 5 0 0 0 1 3 2 1 0 0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 16-5. Interrupt Configuration Address Register (INT_CFADDR) Read: Anytime Write: Anytime Table 16-5.
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Chapter 16 Interrupt (S12XINTV1) 16.3.1.4 Interrupt Request Configuration Data Registers (INT_CFDATA0–7) The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the block of eight interrupt requests (out of 128) selected by the interrupt configuration address register (INT_CFADDR) in ascending order.
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Chapter 16 Interrupt (S12XINTV1) Address: 0x012C 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 11 = Unimplemented or Reserved Figure 16-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4) 1 Please refer to the notes following the PRIOLVL[2:0] description below. Address: 0x012D 7 R W Reset RQST 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 PRIOLVL[2:0] 0 0 11 = Unimplemented or Reserved Figure 16-11.
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Chapter 16 Interrupt (S12XINTV1) Table 16-6. INT_CFDATA0–7 Field Descriptions Field Description 7 RQST XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by the XGATE module. 0 Interrupt request is handled by the CPU 1 Interrupt request is handled by the XGATE module Note: The IRQ interrupt cannot be handled by the XGATE module.
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Chapter 16 Interrupt (S12XINTV1) 16.4 Functional Description The XINT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below. 16.4.1 S12X Exception Requests The CPU handles both reset requests and interrupt requests.
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Chapter 16 Interrupt (S12XINTV1) 16.4.2.1 Interrupt Priority Stack The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel which is configured to be handled by the CPU. The copying takes place when the interrupt vector is fetched.
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Chapter 16 Interrupt (S12XINTV1) If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector.
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Chapter 16 Interrupt (S12XINTV1) 16.5 16.5.1 Initialization/Application Information Initialization After system reset, software should: • Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF10–0xFFF9). • Initialize the interrupt processing level configuration data registers (INT_CFADDR, INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request target (CPU or XGATE module).
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Chapter 16 Interrupt (S12XINTV1) 0 Stacked IPL IPL in CCR 0 0 4 0 0 0 4 7 4 3 1 0 7 6 RTI L7 5 4 RTI Processing Levels 3 L3 (Pending) 2 L4 RTI 1 L1 (Pending) 0 RTI Reset Figure 16-14. Interrupt Processing Example 16.5.3 16.5.3.1 Wake Up from Stop or Wait Mode CPU Wake Up from Stop or Wait Mode Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking the MCU from stop or wait mode.
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Chapter 16 Interrupt (S12XINTV1) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.1 Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform. The block diagram of the MMC is shown in Figure 1-1. The MMC module controls the multi-master priority accesses, the selection of internal resources and external space. Internal buses including internal memories and peripherals are controlled in this module.
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Chapter 17 Memory Mapping Control (S12XMMCV2) • Wait mode MMC is functional during wait mode. Stop mode MMC is inactive during stop mode. • 17.1.2.2 • Functional Modes Single chip modes In normal and special single chip mode the internal memory is used. External bus is not active. Expanded modes Address, data, and control signals are activated in normal expanded and special test modes when accessing the external bus.
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Chapter 17 Memory Mapping Control (S12XMMCV2) Table 1-2 and Table 1-3 outline the pin names and functions. It also provides a brief description of their operation. Table 17-1. External Input Signals Associated with the MMC Signal I/O Description Availability MODC I Mode input MODB I Mode input Latched after RESET (active low) MODA I Mode input EROMCTL I EROM control input ROMCTL I ROM control input Table 17-2.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3 17.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the MMC block is shown in Figure 1-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
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Chapter 17 Memory Mapping Control (S12XMMCV2) Address Register Name 0x011C RAMWPC Bit 7 R RAMXGU R 1 W 0x011E RAMSHL R 1 W 0x011F RAMSHU 5 4 3 2 0 0 0 0 0 XGU6 XGU5 XGU4 XGU3 SHL6 SHL5 SHL4 SHU6 SHU5 SHU4 RPWE W 0x011D 6 R 1 W 1 Bit 0 AVIE AVIF XGU2 XGU1 XGU0 SHL3 SHL2 SHL1 SHL0 SHU3 SHU2 SHU1 SHU0 = Unimplemented or Reserved Figure 17-2. MMC Register Summary 17.3.2 17.3.2.
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Chapter 17 Memory Mapping Control (S12XMMCV2) The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects. CAUTION XGATE write access to this register during an CPU access which makes use of this register could lead to unexpected results. Table 17-4.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.2 Mode Register (MODE) Address: 0x000B PRR 7 R W Reset 6 5 MODC MODB MODA MODC1 MODB1 MODA1 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1. External signal (see Table 1-2). = Unimplemented or Reserved Figure 17-4. Mode Register (MODE) Read: Anytime. In emulation modes read operations will return the data read from the external bus. In all other modes the data are read from this register.
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Chapter 17 Memory Mapping Control (S12XMMCV2) RESET 010 Special Test (ST) 010 1 1 10 0 10 Normal Expanded (NX) 101 Emulation Single-Chip (ES) 001 Emulation Expanded (EX) 011 101 10 1 011 RESET 0 10 RESET RESET 000 001 101 101 010 110 111 Normal Single-Chip (NS) 100 1 00 01 RESET 100 1 01 1 00 Special Single-Chip (SS) 000 000 RESET Transition done by external pins (MODC, MODB, MODA) RESET Transition done by write access to the MODE register 110 111 Illegal (MODC, MODB, M
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.3 Global Page Index Register (GPAGE) Address: 0x0010 7 R 0 W Reset 0 6 5 4 3 2 1 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 17-6. Global Page Index Register (GPAGE) Read: Anytime Write: Anytime The global page index register is used only when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX, GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide).
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.4 Direct Page Register (DIRECT) Address: 0x0011 R W Reset 7 6 5 4 3 2 1 0 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 0 0 0 0 0 0 0 0 Figure 17-8. Direct Register (DIRECT) Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the direct page within the memory map. Table 17-8.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.5 MMC Control Register (MMCCTL1) Address: 0x0013 PRR R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 W Reset 2 1 0 EROMON ROMHM ROMON EROMCTL 0 ROMCTL = Unimplemented or Reserved Figure 17-10. MMC Control Register (MMCCTL1) Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other modes the data are read from this register. Write: Refer to each bit description.
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Chapter 17 Memory Mapping Control (S12XMMCV2) Table 17-10.
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Chapter 17 Memory Mapping Control (S12XMMCV2) Global Address [22:0] 0 0 0 Bit19 Bit18 Bit12 Bit11 Bit0 Address [11:0] RPAGE Register [7:0] Address: CPU Local Address or BDM Local Address Figure 17-12. RPAGE Address Mapping NOTE Because RAM page 0 has the same global address as the register space, it is possible to write to registers through the RAM space when RPAGE = $00. Table 17-11.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.7 EEPROM Page Index Register (EPAGE) Address: 0x0017 R W 7 6 5 4 3 2 1 0 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 1 1 1 1 1 1 1 0 Reset Figure 17-13.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.8 Program Page Index Register (PPAGE) Address: 0x0030 R W Reset 7 6 5 4 3 2 1 0 PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 1 1 1 1 1 1 1 0 Figure 17-15.
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Chapter 17 Memory Mapping Control (S12XMMCV2) Table 17-13. PPAGE Field Descriptions Field 7–0 PIX[7:0] Description Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM array pages is to be accessed in the Program Page Window. The fixed 16K page from $4000–$7FFF (when ROMHM = 0) is the page number $FD. The reset value of $FE ensures that there is linear Flash space available between addresses $4000 and $FFFF out of reset.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.10 RAM XGATE Upper Boundary Register (RAMXGU) Address: 0x011D 7 R 1 W Reset 1 6 5 4 3 2 1 0 XGU6 XGU5 XGU4 XGU3 XGU2 XGU1 XGU0 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 17-18. RAM XGATE Upper Boundary Register (RAMXGU) Read: Anytime Write: Anytime when RWPE = 0 Table 17-15.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.3.2.12 RAM Shared Region Upper Boundary Register (RAMSHU) Address: 0x011F 7 R 1 W Reset 1 6 5 4 3 2 1 0 SHU6 SHU5 SHU4 SHU3 SHU2 SHU1 SHU0 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 17-20. RAM Shared Region Upper Boundary Register (RAMSHU) Read: Anytime Write: Anytime when RWPE = 0 Table 17-17.
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Chapter 17 Memory Mapping Control (S12XMMCV2) • • • Normal expanded mode The external bus interface is configured as an up to 23-bit address bus, 8 or 16-bit data bus with dedicated bus control and status signals. This mode allows 8 or 16-bit external memory and peripheral devices to be interfaced to the system. The fastest external bus rate is half of the internal bus rate. An external signal can be used in this mode to cause the external bus to wait as desired by the external logic.
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Chapter 17 Memory Mapping Control (S12XMMCV2) CPU or BDM Local Memory Map Global Memory Map $00_0000 2K Registers $00_0800 $00_1000 $0000 RAM 253*4K paged 2K Registers $0800 EEPROM 1K window EPAGE 1M minus Kbytes 2K RAM $0F_E000 8K RAM $0C00 1K EEPROM $10_0000 RAM 4K window EEPROM 255*1K paged RPAGE $2000 $13_FC00 256 Kbytes $1000 1K EEPROM 8K RAM $14_4000 $4000 ROMHM=1 $14_8000 Unpaged Flash External Space No 2.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.4.2.1.1 Expansion of the Local Address Map Expansion of the CPU Local Address Map The program page index register in MMC allows accessing up to 4 Mbyte of FLASH or ROM in the global memory map by using the eight page index bits to page 256 16 Kbyte blocks into the program page window located from address $8000 to address $BFFF in the local CPU memory map. The page value for the program page window is stored in the PPAGE register.
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Chapter 17 Memory Mapping Control (S12XMMCV2) Expansion of the BDM Local Address Map PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the global address. These registers can be read and written by the BDM. The BDM expansion scheme is the same as the CPU expansion scheme. 17.4.2.
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Chapter 17 Memory Mapping Control (S12XMMCV2) BDM HARDWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 Bit0 BDMGPR Register [6:0] BDM Local Address BDM FIRMWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 Bit0 BDMGPR Register [6:0] CPU Local Address Figure 17-22. BDMGPR Address Mapping 17.4.2.3 Implemented Memory Map The global memory spaces reserved for the internal resources (RAM, EEPROM, and FLASH) are not determined by the MMC module.
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Chapter 17 Memory Mapping Control (S12XMMCV2) When the device is operating in expanded modes except emulation single-chip mode, accesses to the global addresses which are not occupied by the on-chip resources (unimplemented areas or external space) result in accesses to the external bus (see Figure 17-23). In emulation single-chip mode, accesses to the global addresses which are not occupied by the on-chip resources (unimplemented areas) result in accesses to the external bus.
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Chapter 17 Memory Mapping Control (S12XMMCV2) CPU and BDM Local Memory Map Global Memory Map $00_0000 2K Registers $00_0800 CS3 Unimplemented RAM 2K Registers RAM $0800 EEPROM 1K window EPAGE RAMSIZE $0000 $0F_FFFF $0C00 $2000 EEPROM $13_FFFF 8K RAM $1F_FFFF CS1 External Space $4000 CS2 RPAGE EEPROMSIZE Unimplemented EEPROM $1000 RAM 4K window CS2 1K EEPROM Unpaged Flash $40_0000 Flash 16K window CS0 $8000 Unimplemented FLASH PPAGE $C000 $FFFF Reset Vectors FLASH FLASHSIZE
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.4.2.4 17.4.2.4.1 XGATE Memory Map Scheme Expansion of the XGATE Local Address Map The XGATE 64 Kbyte memory space allows access to internal resources only (Registers, RAM, and FLASH). The 2 Kilobyte register address range is the same register address range as for the CPU and the BDM module . XGATE can access the FLASH in single chip modes, even when the MCU is secured. In expanded modes, XGATE can not access the FLASH when MCU is secured.
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Chapter 17 Memory Mapping Control (S12XMMCV2) XGATE Local Memory Map Global Memory Map $00_0000 2K Registers $00_0800 $0800 RAM $0F_FFFF XGRAMSIZE 2K Registers RAMSIZE $0000 RAM $FFFF FLASH FLASHSIZE 2K XGRAMSIZE FLASH $7F_FFFF Figure 17-24. Local to Global Address Mapping (XGATE) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.4.3 17.4.3.1 Chip Access Restrictions Illegal XGATE Accesses A possible access error is flagged by the MMC and signalled to XGATE under the following conditions: • XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses). • XGATE accesses the register space (in case of opcode or vector fetch). • XGATE performs a write to Flash in any modes (in case of load-store access).
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Chapter 17 Memory Mapping Control (S12XMMCV2) The following conditions must be satisfied to ensure correct operation of the RAM protection mechanism: • Value stored in RAMXGU must be lower than the value stored in RAMSHL. • Value stored RAMSHL must be lower or equal than the value stored in RAMSHU. Table 17-21.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.4.4 Chip Bus Control The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping operations. All internal and external resources are connected to specific target buses (see Figure 1-26).
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.4.4.2 Access Conflicts on Target Buses The arbitration scheme allows only one master to be connected to a target at any given time. The following rules apply when prioritizing accesses from different masters to the same target bus: • CPU always has priority over XGATE. • BDM access has priority over XGATE. • XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU and BDM for its duration.
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Chapter 17 Memory Mapping Control (S12XMMCV2) This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction execution. A CALL instruction can be performed from any address to any other address in the local CPU memory space. The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand in the instruction.
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Chapter 17 Memory Mapping Control (S12XMMCV2) Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in emulation modes. A summary of PRR accesses is the following: • An aligned word access to a PRR will take 2 bus cycles. • A misaligned word access to a PRRs will take 4 cycles.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.5.3 On-Chip ROM Control The MCU offers two modes to support emulation. In the first mode (called generator) the emulator provides the data instead of the internal FLASH and traces the CPU actions. In the other mode (called observer) the internal FLASH provides the data and all internal actions are made visible to the emulator. 17.5.3.1 ROM Control in Single-Chip Modes In single-chip modes the MCU has no external bus.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.5.3.3 ROM Control in Normal Expanded Mode In normal expanded mode the external bus will be connected to the application. If the ROMON bit is set, the internal FLASH provides the data. If the ROMON bit is cleared, the application memory provides the data (see Figure 1-29). MCU Application Flash Memory ROMON = 1 MCU Application Memory ROMON = 0 Figure 17-29. ROM in Normal Expanded Mode MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 17 Memory Mapping Control (S12XMMCV2) 17.5.3.4 ROM Control in Emulation Expanded Mode In emulation expanded mode the external bus will be connected to the emulator and to the application. If the ROMON bit is set, the internal FLASH provides the data. If the EROMON bit is set as well the emulator observes all CPU internal actions, otherwise the emulator provides the data and traces all CPU actions (see Figure 1-30).
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Chapter 17 Memory Mapping Control (S12XMMCV2) Observer MCU Emulator Application Memory Figure 17-31. ROMON = 0 in Emulation Expanded Mode 17.5.3.5 ROM Control in Special Test Mode In special test mode the external bus is connected to the application. If the ROMON bit is set, the internal FLASH provides the data, otherwise the application memory provides the data (see Figure 1-32). Application MCU Memory ROMON = 0 Application MCU Flash Memory ROMON = 1 Figure 17-32.
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Chapter 17 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.1 Introduction This section describes the functionality of the module mapping control (MMC) sub-block of the S12X platform. The block diagram of the MMC is shown in Figure 18-1. The MMC module controls the multi-master priority accesses, the selection of internal resources and external space. Internal buses, including internal memories and peripherals, are controlled in this module.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.1.1 Terminology Table 18-1.
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Chapter 18 Memory Mapping Control (S12XMMCV3) • • • • • • • • • Simultaneous accesses to different resources1 (internal, external, and peripherals) (see ) Resolution of target bus access collision Access restriction control from masters to some targets (e.g.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.1.4.2 • Functional Modes Single chip modes In normal and special single chip mode the internal memory is used. External bus is not active. Expanded modes Address, data, and control signals are activated in normal expanded and special test modes when accessing the external bus. Access to internal resources will not cause activity on the external bus.
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Chapter 18 Memory Mapping Control (S12XMMCV3) Table 18-2. External Input Signals Associated with the MMC Signal I/O Description Availability MODC I Mode input Latched after RESET (active low) MODB I Mode input Latched after RESET (active low) MODA I Mode input Latched after RESET (active low) EROMCTL I EROM control input Latched after RESET (active low) ROMCTL I ROM control input Latched after RESET (active low) Table 18-3.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.3 18.3.1 Memory Map and Registers Module Memory Map A summary of the registers associated with the MMC block is shown in Figure 18-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
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Chapter 18 Memory Mapping Control (S12XMMCV3) Address Register Name 0x011D RAMXGU Bit 7 R 1 W 0x011E RAMSHL R 1 W 0x011F RAMSHU R 1 W 6 5 4 3 2 1 Bit 0 XGU6 XGU5 XGU4 XGU3 XGU2 XGU1 XGU0 SHL6 SHL5 SHL4 SHL3 SHL2 SHL1 SHL0 SHU6 SHU5 SHU4 SHU3 SHU2 SHU1 SHU0 = Unimplemented or Reserved Figure 18-2. MMC Register Summary 18.3.2 18.3.2.
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Chapter 18 Memory Mapping Control (S12XMMCV3) Table 18-5. MMCCTL0 Field Descriptions Field Description 3–0 CS[3:0]E Chip Select Enables — Each of these bits enables one of the external chip selects CS3, CS2, CS1, and CS0 outputs which are asserted during accesses to specific external addresses. The associated global address ranges are shown in Table 18-6 and Table 18-21 and Figure 18-21. Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test mode.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.3.2.2 Mode Register (MODE) Address: 0x000B PRR 7 R W Reset 6 5 MODC MODB MODA MODC1 MODB1 MODA1 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1. External signal (see Table 18-2). = Unimplemented or Reserved Figure 18-4. Mode Register (MODE) Read: Anytime. In emulation modes read operations will return the data read from the external bus. In all other modes the data are read from this register.
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Chapter 18 Memory Mapping Control (S12XMMCV3) RESET 010 Special Test (ST) 010 1 1 10 0 10 Normal Expanded (NX) 101 Emulation Single-Chip (ES) 001 Emulation Expanded (EX) 011 101 10 1 011 RESET 0 10 RESET RESET 000 001 101 101 010 110 111 Normal Single-Chip (NS) 100 1 00 01 RESET 100 1 01 1 00 Special Single-Chip (SS) 000 000 RESET Transition done by external pins (MODC, MODB, MODA) RESET Transition done by write access to the MODE register 110 111 Illegal (MODC, MODB, M
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.3.2.3 Global Page Index Register (GPAGE) Address: 0x0010 7 R 0 W Reset 0 6 5 4 3 2 1 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 18-6. Global Page Index Register (GPAGE) Read: Anytime Write: Anytime The global page index register is used to construct a 23 bit address in the global map format.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.3.2.4 Direct Page Register (DIRECT) Address: 0x0011 R W 7 6 5 4 3 2 1 0 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 0 0 0 0 0 0 0 0 Reset Figure 18-8. Direct Register (DIRECT) Read: Anytime Write: anytime in special modes, one time only in other modes. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. Table 18-9.
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Chapter 18 Memory Mapping Control (S12XMMCV3) ;automatically select direct mode. 18.3.2.5 MMC Control Register (MMCCTL1) Address: 0x0013 PRR R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 W Reset 2 1 0 EROMON ROMHM ROMON EROMCTL 0 ROMCTL = Unimplemented or Reserved Figure 18-10. MMC Control Register (MMCCTL1) Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other modes the data are read from this register.
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Chapter 18 Memory Mapping Control (S12XMMCV3) Table 18-11.
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Chapter 18 Memory Mapping Control (S12XMMCV3) Global Address [22:0] 0 0 0 Bit19 Bit18 Bit12 Bit11 Bit0 Address [11:0] RPAGE Register [7:0] Address: CPU Local Address or BDM Local Address Figure 18-12. RPAGE Address Mapping NOTE Because RAM page 0 has the same global address as the register space, it is possible to write to registers through the RAM space when RPAGE = 0x00. Table 18-12.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.3.2.7 EEPROM Page Index Register (EPAGE) Address: 0x0017 R W 7 6 5 4 3 2 1 0 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 1 1 1 1 1 1 1 0 Reset Figure 18-13. EEPROM Page Index Register (EPAGE) Read: Anytime Write: Anytime These eight index bits are used to page 1 KByte blocks into the EEPROM page window located in the local (CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see Figure 18-14).
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.3.2.8 Program Page Index Register (PPAGE) Address: 0x0030 R W Reset 7 6 5 4 3 2 1 0 PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 1 1 1 1 1 1 1 0 Figure 18-15. Program Page Index Register (PPAGE) Read: Anytime Write: Anytime These eight index bits are used to page 16 KByte blocks into the Flash page window located in the local (CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 18-16).
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Chapter 18 Memory Mapping Control (S12XMMCV3) Table 18-14. PPAGE Field Descriptions Field 7–0 PIX[7:0] Description Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM array pages is to be accessed in the Program Page Window. The fixed 16K page from 0x4000–0x7FFF (when ROMHM = 0) is the page number 0xFD. The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and 0xFFFF out of reset.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.3.2.10 RAM XGATE Upper Boundary Register (RAMXGU) Address: 0x011D 7 R 1 W Reset 1 6 5 4 3 2 1 0 XGU6 XGU5 XGU4 XGU3 XGU2 XGU1 XGU0 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 18-18. RAM XGATE Upper Boundary Register (RAMXGU) Read: Anytime Write: Anytime when RWPE = 0 Table 18-16.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.3.2.12 RAM Shared Region Upper Boundary Register (RAMSHU) Address: 0x011F 7 R 1 W Reset 1 6 5 4 3 2 1 0 SHU6 SHU5 SHU4 SHU3 SHU2 SHU1 SHU0 1 1 1 1 1 1 1 = Unimplemented or Reserved Figure 18-20. RAM Shared Region Upper Boundary Register (RAMSHU) Read: Anytime Write: Anytime when RWPE = 0 Table 18-18.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.4 Functional Description The MMC block performs several basic functions of the S12X sub-system operation: MCU operation modes, priority control, address mapping, select signal generation and access limitations for the system. Each aspect is described in the following subsections. 18.4.1 • • • MCU Operating Mode Normal single-chip mode There is no external bus in this mode.
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Chapter 18 Memory Mapping Control (S12XMMCV3) • • • Normal expanded mode The external bus interface is configured as an up to 23-bit address bus, 8 or 16-bit data bus with dedicated bus control and status signals. This mode allows 8 or 16-bit external memory and peripheral devices to be interfaced to the system. The fastest external bus rate is half of the internal bus rate. An external signal can be used in this mode to cause the external bus to wait as desired by the external logic.
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Chapter 18 Memory Mapping Control (S12XMMCV3) CPU and BDM Local Memory Map Global Memory Map 0x00_0000 0x00_0800 2K REGISTERS 2K RAM RAM 253*4K paged 0x0800 0x0C00 0x1000 0x0F_E000 2K REGISTERS 1K EEPROM window 8K RAM EPAGE 0x10_0000 1K EEPROM 4K RAM window EEPROM 255*1K paged RPAGE 0x2000 8K RAM 0x4000 0x13_FC00 256 Kilobytes 0x0000 1M minus 2 Kilobytes 0x00_1000 1K EEPROM External Space 0x8000 16K FLASH window 2.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.4.2.1.1 Expansion of the Local Address Map Expansion of the CPU Local Address Map The program page index register in MMC allows accessing up to 4 Mbyte of FLASH or ROM in the global memory map by using the eight page index bits to page 256 16 Kbyte blocks into the program page window located from address 0x8000 to address 0xBFFF in the local CPU memory map. The page value for the program page window is stored in the PPAGE register.
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Chapter 18 Memory Mapping Control (S12XMMCV3) Expansion of the BDM Local Address Map PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the global address. These registers can be read and written by the BDM. The BDM expansion scheme is the same as the CPU expansion scheme. 18.4.2.
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Chapter 18 Memory Mapping Control (S12XMMCV3) BDM HARDWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 BDMGPR Register [6:0] Bit0 BDM Local Address BDM FIRMWARE COMMAND Global Address [22:0] Bit22 Bit16 Bit15 BDMGPR Register [6:0] Bit0 CPU Local Address Figure 18-22. BDMGPR Address Mapping MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.4.2.3 Implemented Memory Map The global memory spaces reserved for the internal resources (RAM, EEPROM, and FLASH) are not determined by the MMC module. Size of the individual internal resources are however fixed in the design of the device cannot be changed by the user. Please refer to the Device User Guide for further details. Figure 18-23 and Table 18-20 show the memory spaces occupied by the on-chip resources.
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Chapter 18 Memory Mapping Control (S12XMMCV3) Table 18-21 shows the address boundaries of each chip select and the relationship with the implemented resources (internal) parameters. Table 18-21.
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Chapter 18 Memory Mapping Control (S12XMMCV3) XGATE Local Memory Map Global Memory Map 0x00_0000 Registers 0x00_07FF XGRAM_LOW 0x0800 RAM 0x0F_FFFF RAMSIZE Registers XGRAMSIZE 0x0000 FLASH 0x78_0800 FLASH XGFLASH_HIGH 0xFFFF XGFLASHSIZE RAM 0x7F_FFFF Figure 18-24. XGATE Global Address Mapping MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.4.3 18.4.3.1 Chip Access Restrictions Illegal XGATE Accesses A possible access error is flagged by the MMC and signalled to XGATE under the following conditions: • XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses). • XGATE accesses the register space (in case of opcode or vector fetch). • XGATE performs a write to Flash in any modes (in case of load-store access).
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Chapter 18 Memory Mapping Control (S12XMMCV3) Table 18-22. RAM Write Protection Interrupt Vectors Interrupt Source CCR Mask Local Enable CPU access violation I Bit AVIE in RAMWPC Figure 18-25. RAM write protection scheme MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.4.4 Chip Bus Control The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDMand XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping operations. All internal and external resources are connected to specific target buses (see Figure 18-261).
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.4.4.1 Master Bus Prioritization regarding Access Conflicts on Target Buses The arbitration scheme allows only one master to be connected to a target at any given time. The following rules apply when prioritizing accesses from different masters to the same target bus: • CPU always has priority over BDM and XGATE. • XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU for its duration.
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Chapter 18 Memory Mapping Control (S12XMMCV3) This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction execution. A CALL instruction can be performed from any address to any other address in the local CPU memory space. The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand in the instruction.
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Chapter 18 Memory Mapping Control (S12XMMCV3) Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in emulation modes. A summary of PRR accesses: • An aligned word access to a PRR will take 2 bus cycles. • A misaligned word access to a PRRs will take 4 cycles.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.5.3 On-Chip ROM Control The MCU offers two modes to support emulation. In the first mode (called generator) the emulator provides the data instead of the internal FLASH and traces the CPU actions. In the other mode (called observer) the internal FLASH provides the data and all internal actions are made visible to the emulator. 18.5.3.1 ROM Control in Single-Chip Modes In single-chip modes the MCU has no external bus.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.5.3.3 ROM Control in Normal Expanded Mode In normal expanded mode the external bus will be connected to the application. If the ROMON bit is set, the internal FLASH provides the data. If the ROMON bit is cleared, the application memory provides the data (see Figure 18-29). MCU Application Memory Flash ROMON = 1 MCU Application Memory ROMON = 0 Figure 18-29. ROM in Normal Expanded Mode MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 18 Memory Mapping Control (S12XMMCV3) 18.5.3.4 ROM Control in Emulation Expanded Mode In emulation expanded mode the external bus will be connected to the emulator and to the application. If the ROMON bit is set, the internal FLASH provides the data. If the EROMON bit is set as well the emulator observes all CPU internal actions, otherwise the emulator provides the data and traces all CPU actions (see Figure 18-30).
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Chapter 18 Memory Mapping Control (S12XMMCV3) Observer MCU Emulator Application Memory Figure 18-31. ROMON = 0 in Emulation Expanded Mode 18.5.3.5 ROM Control in Special Test Mode In special test mode the external bus is connected to the application. If the ROMON bit is set, the internal FLASH provides the data, otherwise the application memory provides the data (see Figure 18-32). Application MCU Memory ROMON = 0 Application MCU Flash Memory ROMON = 1 Figure 18-32.
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Chapter 18 Memory Mapping Control (S12XMMCV3) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 691
Chapter 19 S12X Debug (S12XDBGV2) Module 19.1 Introduction The DBG module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The DBG module is optimized for the HCS12X 16-bit architecture and allows debugging of both CPU and XGATE module operations. Typically the DBG module is used in conjunction with the BDM module, whereby the user configures the DBG module for a debugging session over the BDM interface.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.1.
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Chapter 19 S12X Debug (S12XDBGV2) Module XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE module. When the CPU enters active BDM mode through a BACKGROUND command, with the DBG module armed, the DBG remains armed. The DBG module tracing is disabled if the MCU is secure. Breakpoints can however still be generated if the MCU is secure. Table 19-1.
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Chapter 19 S12X Debug (S12XDBGV2) Module . Table 19-2. External System Pins Associated With DBG Pin Name Pin Functions Description TAGHI (See DUG) TAGHI When instruction tagging is on, tags the high half of the instruction word being read into the instruction queue. TAGLO (See DUG) TAGLO When instruction tagging is on, tags the low half of the instruction word being read into the instruction queue. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.3 Memory Map and Register Definition A summary of the registers associated with the DBG sub-block is shown in Figure 19-2. Detailed descriptions of the registers and bits are given in the subsections that follow. 19.3.1 Register Descriptions This section consists of the DBG control and trace buffer register descriptions in address order.
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Chapter 19 S12X Debug (S12XDBGV2) Module Address Register Name 0x0029 DBGXAH Bit 7 6 5 4 3 2 1 Bit 0 Bit 22 21 20 19 18 17 Bit 16 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 R 0 W 0x002A DBGXAM R W 0x002B DBGXAL R W 0x002C DBGXDH R W 0x002D DBGXDL R W 0x002E DBGXDHM R W 0x002F DBGXDLM R W = Unimplemented
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Chapter 19 S12X Debug (S12XDBGV2) Module Table 19-3. DBGC1 Field Descriptions Field Description 7 ARM Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1. When ARM is set, the only bits in the DBG module registers that can be written are ARM and TRIG.
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Chapter 19 S12X Debug (S12XDBGV2) Module Table 19-5. COMRV Encoding 19.3.1.2 COMRV Visible Comparator Visible State Control Register 01 Comparator B DBGSCR2 10 Comparator C DBGSCR3 11 Comparator D DBGSCR3 Debug Status Register (DBGSR) 0x0021 7 6 5 4 3 2 1 0 TBF EXTF 0 0 0 SSF2 SSF1 SSF0 Reset — 0 0 0 0 0 0 0 POR 0 0 0 0 0 0 0 0 R W Unimplemented or Reserved Figure 19-4. Debug Status Register (DBGSR) Read: Anytime Write: Never Table 19-6.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.3.1.3 Debug Trace Control Register (DBGTCR) 0x0022 7 R 5 TSOURCE W Reset 6 0 4 3 TRANGE 0 0 2 1 TRCMOD 0 0 0 TALIGN 0 0 0 Figure 19-5. Debug Trace Control Register (DBGTCR) Read: Anytime Write: Bits 7:6 only when DBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed. Table 19-8.
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Chapter 19 S12X Debug (S12XDBGV2) Module Table 19-10. TRANGE Trace Range Encoding TRANGE Tracing Source 11 Trace only in range from comparator C to comparator D Table 19-11. TRCMOD Trace Mode Bit Encoding TRCMOD Description 00 NORMAL 01 LOOP1 10 DETAIL 11 Reserved Table 19-12. TALIGN Trace Alignment Encoding 19.3.1.
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Chapter 19 S12X Debug (S12XDBGV2) Module Table 19-14. CDCM Encoding CDCM Description 00 Match2 mapped to comparator C match....... Match3 mapped to comparator D match. 01 Match2 mapped to comparator C/D inside range....... Match3 disabled. 10 Match2 mapped to comparator C/D outside range....... Match3 disabled. 11 Reserved Table 19-15. ABCM Encoding 19.3.1.5 ABCM Description 00 Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
PAGE 702
Chapter 19 S12X Debug (S12XDBGV2) Module 19.3.1.6 Debug Count Register (DBGCNT) 0x0026 7 R 6 5 4 0 3 2 1 0 CNT W Reset 0 POR 0 — — — — — — — 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 19-9. Debug Count Register (DBGCNT) Read: Anytime Write: Never Table 19-17. DBGCNT Field Descriptions Field Description 6–0 CNT[6:0] Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the trace buffer.
PAGE 703
Chapter 19 S12X Debug (S12XDBGV2) Module 19.3.1.7 Debug State Control Registers Each of the state sequencer states 1 to 3 features a dedicated control register to determine if transitions from that state are allowed depending upon comparator matches or tag hits and to define the next state for the state sequencer following a match. The 3 debug state control registers are located at the same address in the register address map (0x0027).
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Chapter 19 S12X Debug (S12XDBGV2) Module Table 19-21. State1 Sequencer Next Sate Selection SC[3:0] Description 0000 Any match triggers to state2 0001 Any match triggers to state3 0010 Any match triggers to final state 0011 Match2 triggers to State2....... Other matches have no effect 0100 Match2 triggers to State3....... Other matches have no effect 0101 Match2 triggers to final state....... Other matches have no effect 0110 Match0 triggers to State2....... Match1 triggers to State3.......
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Chapter 19 S12X Debug (S12XDBGV2) Module Table 19-22. DBGSCR2 Field Descriptions Field 3–0 SC[3:0} Description State Control Bits — These bits select the targeted next state while in State2, based upon the match event. See Table 19-23. The trigger priorities described in Table 19-38 dictate that in the case of simultaneous matches, the match on the lower channel number ([0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final state has priority over all other matches.
PAGE 706
Chapter 19 S12X Debug (S12XDBGV2) Module (DBGXCTL)”. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. Table 19-24. DBGSCR3 Field Descriptions Field Description 3–0 SC[3:0] State Control Bits — These bits select the targeted next state while in State3, based upon the match event. The trigger priorities described in Table 19-38 dictate that in the case of simultaneous matches, the match on the lower channel number (0,1,2,3) has priority.
PAGE 707
Chapter 19 S12X Debug (S12XDBGV2) Module Table 19-26. Comparator Register Layout 0x0029 ADDRESS HIGH Read/Write 0x002A ADDRESS MEDIUM Read/Write 0x002B ADDRESS LOW Read/Write 0x002C DATA HIGH COMPARATOR Read/Write Comparator A and C only 0x002D DATA LOW COMPARATOR Read/Write Comparator A and C only 0x002E DATA HIGH MASK Read/Write Comparator A and C only 0x002F DATA LOW MASK Read/Write Comparator A and C only 19.3.1.11.
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Chapter 19 S12X Debug (S12XDBGV2) Module Table 19-27. DBGXCTL Field Descriptions (continued) Field Description 6 Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the (COMP B/D) associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.3.1.11.2 Debug Comparator Address High Register (DBGXAH) 0x0029 7 R 0 W Reset 0 6 5 4 3 2 1 0 Bit 22 21 20 19 18 17 Bit 16 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 19-15. Debug Comparator Address High Register (DBGXAH) Read: Anytime Write: Anytime when DBG not armed. Table 19-29.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.3.1.11.4 Debug Comparator Address Low Register (DBGXAL) 0x002B R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 19-17. Debug Comparator Address Low Register (DBGXAL) Read: Anytime Write: Anytime when DBG not armed. Table 19-31.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.3.1.11.6 Debug Comparator Data Low Register (DBGXDL) 0x002D R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 19-19. Debug Comparator Data Low Register (DBGXDL) Read: Anytime Write: Anytime when DBG not armed. Table 19-33.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.3.1.11.8 Debug Comparator Data Low Mask Register (DBGXDLM) 0x002F R W Reset 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Figure 19-21. Debug Comparator Data Low Mask Register (DBGXDLM) Read: Anytime Write: Anytime when DBG not armed. Table 19-35.
PAGE 713
Chapter 19 S12X Debug (S12XDBGV2) Module TAGS TAGHITS EXTERNAL TAGHI / TAGLO BREAKPOINT REQUESTS CPU & XGATE XGATE BUS COMPARATOR A COMPARATOR B COMPARATOR C COMPARATOR D COMPARATOR MATCH CONTROL CPU BUS BUS INTERFACE XGATE S/W BREAKPOINT REQUEST SECURE MATCH0 MATCH1 MATCH2 TAG & TRIGGER TRIGGER CONTROL LOGIC STATE STATE SEQUENCER MATCH3 TRACE CONTROL TRIGGER READ TRACE DATA (DBG READ DATA BUS) TRACE BUFFER Figure 19-22. DBG Overview 19.4.
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Chapter 19 S12X Debug (S12XDBGV2) Module If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite number of cycles due to instruction pipe lining.
PAGE 715
Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.2.2 Exact Address Comparator Match (Comparators B and D) Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match qualification functions the same as for comparators A and C. If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the specified type of access causes a match.
PAGE 716
Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.2.3.2 Outside Range (Address < CompAC_Addr or Address > CompBD_Addr) In the outside range comparator mode, either comparator pair A and B or comparator pair C and D can be configured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range.
PAGE 717
Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.3.4 Trigger On XGATE S/W Breakpoint Request The XGATE S/W breakpoint request issues a forced breakpoint request to the CPU immediately independent of DBG settings. If the debug module is armed triggers the state sequencer into the disarmed state. Active tracing sessions are terminated immediately, thus if tracing has not yet begun using begintrigger, no trace information is stored. XGATE generated breakpoints are independent of the DBGBRK bits.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.4 State Sequence Control ARM = 0 State 0 (Disarmed) ARM = 1 State1 State2 ARM = 0 Session complete (disarm) Final State State3 ARM=0 Figure 19-23. State Sequencer Diagram The state sequence control allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then State1 of the state sequencer is entered.
PAGE 719
Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.4.1 Final State On entering final state a trigger may be issued to the trace buffer according to the trace position control as defined by the TALIGN field (see Section 19.3.1.3, “Debug Trace Control Register (DBGTCR)”). If the TSOURCE bits in the trace control register DBGTCR are cleared then the trace buffer is disabled and the transition to final state can only generate a breakpoint request.
PAGE 720
Chapter 19 S12X Debug (S12XDBGV2) Module is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary. 19.4.5.1.3 Storing with End-Trigger Storing with end-trigger, data is stored in the trace buffer until the final state is entered, at which point the DBG module will become disarmed and no more data will be stored.
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Chapter 19 S12X Debug (S12XDBGV2) Module Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help find.
PAGE 722
Chapter 19 S12X Debug (S12XDBGV2) Module information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format for loop1 mode is the same as that of normal mode. Whilst tracing from XGATE or CPU only, in normal or loop1 modes each array line contains data from entries made at 2 separate times, thus in this case the DBGCNT[0] is incremented after each separate entry.
PAGE 723
Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.5.3.1 Information Byte Organization The format of the control information byte for both CPU and XGATE modules is dependent upon the active trace mode and tracing source as described below. In normal mode or loop1 mode, tracing of XGATE activity XINF is used to store control information. In normal mode or loop1 mode, tracing of CPU activity CINF is used to store control information. In detail mode, CXINF contains the control information.
PAGE 724
Chapter 19 S12X Debug (S12XDBGV2) Module Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CFREE CSZ CRW COCF XACK XSZ XRW XOCF Figure 19-26. Information Byte CXINF This describes the format of the information byte used only when tracing from CPU or XGATE in detail mode. When tracing from the CPU in detail mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot of the XGATE program counter.
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Chapter 19 S12X Debug (S12XDBGV2) Module Table 19-42. CXINF Field Descriptions (continued) Field Description 1 XRW Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing XGATE activity in detail mode. 0 Read/Write Access 1 Access 0 XOCF XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle.
PAGE 726
Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.5.3.3 Trace Buffer Reset State The trace buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out. The DBGCNT bits are not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is indicated by DBGCNT.
PAGE 727
Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.6.1 External Tagging using TAGHI and TAGLO External tagging using the external TAGHI and TAGLO pins can only be used to tag CPU opcodes; tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into State0 when the tagged opcode reaches the execution stage of the instruction queue. The pins operate independently, thus the state of one pin does not affect the function of the other.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.7.2 Breakpoints From Internal Comparator Channel Final State Triggers Breakpoints can be generated when internal comparator channels trigger the state sequencer to the final state. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue.
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Chapter 19 S12X Debug (S12XDBGV2) Module 19.4.7.5 DBG Breakpoint Priorities XGATE software breakpoints have the highest priority. Active tracing sessions are terminated immediately. If a TRIG triggers occur after begin or mid aligned tracing has already been triggered by a comparator instigated transition to final state, then TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs.
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Chapter 19 S12X Debug (S12XDBGV2) Module When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modification it will return to the instruction whose tag generated the breakpoint. Thus care must be taken to avoid re triggering a breakpoint at the same location.
PAGE 731
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 732
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 733
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 734
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 735
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 736
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 737
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 738
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 739
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 740
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 741
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 742
Chapter 19 S12X Debug (S12XDBGV2) Module MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 743
Chapter 20 S12X Debug (S12XDBGV3) Module 20.1 Introduction The S12XDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-intrusive debug of application software. The S12XDBG module is optimized for the HCS12X 16-bit architecture and allows debugging of both S12XCPU and XGATE module operations. Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user configures the S12XDBG module for a debugging session over the BDM interface.
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Chapter 20 S12X Debug (S12XDBGV3) Module The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. Tracing is disabled when the MCU system is secured. 20.1.
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Chapter 20 S12X Debug (S12XDBGV3) Module During BDM hardware accesses and whilst the BDM module is active, S12XCPU monitoring is disabled. Thus breakpoints, comparators, and bus tracing mapped to the S12XCPU are disabled but XGATE bus monitoring accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE module.
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Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-2. External System Pins Associated With S12XDBG Pin Name Pin Functions TAGHI (See DUG) TAGHI When instruction tagging is on, tags the high half of the instruction word being read into the instruction queue. TAGLO (See DUG) TAGLO When instruction tagging is on, tags the low half of the instruction word being read into the instruction queue.
PAGE 747
Chapter 20 S12X Debug (S12XDBGV3) Module Address Name Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0x002A DBGXAM R W 0x002B DBGXAL R W Bit 7 6 5 4 3 2 1 Bit 0 0x002C DBGXDH R W Bit 15 14 13 12 11 10 9 Bit 8 0x002D DBGXDL R W Bit 7 6 5 4 3 2 1 Bit 0 0x002E DBGXDHM R W Bit 15 14 13 12 11 10 9 Bit 8 1 Bit 0 R Bit 7 6 5 4 3 2 W 1 This represents the contents if the Comparator A or C control register is blended into this address.
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Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-3. DBGC1 Field Descriptions Field Description 7 ARM Arm Bit — The ARM bit controls whether the S12XDBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1. When ARM is set, the only bits in the S12XDBG module registers that can be written are ARM and TRIG.
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Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-5. COMRV Encoding COMRV Visible Comparator Visible Register at 0x0027 10 Comparator C DBGSCR3 11 Comparator D DBGMFR MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.2 Debug Status Register (DBGSR) Address: 0x0021 R 7 6 5 4 3 2 1 0 TBF EXTF 0 0 0 SSF2 SSF1 SSF0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset POR = Unimplemented or Reserved Figure 20-4. Debug Status Register (DBGSR) Read: Anytime Write: Never Table 20-6. DBGSR Field Descriptions Field Description 7 TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.3 Debug Trace Control Register (DBGTCR) Address: 0x0022 7 6 R TSOURCE W Reset 5 0 4 3 TRANGE 0 0 2 1 TRCMOD 0 0 0 TALIGN 0 0 0 Figure 20-5. Debug Trace Control Register (DBGTCR) Read: Anytime Write: Bits 7:6 only when S12XDBG is neither secure nor armed. Bits 5:0 anytime the module is disarmed. Table 20-8.
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Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-10. TRANGE Trace Range Encoding TRANGE Tracing Range 00 Trace from all addresses (No filter) 01 Trace only in address range from $00000 to Comparator D 10 Trace only in address range from Comparator C to $7FFFFF 11 Trace only in range from Comparator C to Comparator D Table 20-11. TRCMOD Trace Mode Bit Encoding TRCMOD Description 00 Normal 01 Loop1 10 Detail 11 Pure PC Table 20-12.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.4 Debug Control Register2 (DBGC2) Address: 0x0023 R 7 6 5 4 0 0 0 0 0 0 0 0 3 1 CDCM W Reset 2 0 0 ABCM 0 0 0 = Unimplemented or Reserved Figure 20-6. Debug Control Register2 (DBGC2) Read: Anytime Write: Anytime the module is disarmed. This register configures the comparators for range matching. Table 20-13.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL) Address: 0x0024, 0x0025 15 R W 14 13 12 11 10 9 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Reset X X X X X X X 8 7 6 5 4 3 2 1 0 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X X Figure 20-7. Debug Trace Buffer Register (DBGTB) Read: Anytime when unlocked and not secured and not armed.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.6 Debug Count Register (DBGCNT) Address: 0x0026 7 R 6 5 4 0 3 2 1 0 — 0 — 0 — 0 CNT W Reset POR 0 0 — 0 — 0 — 0 — 0 = Unimplemented or Reserved Figure 20-8. Debug Count Register (DBGCNT) Read: Anytime Write: Never Table 20-17. DBGCNT Field Descriptions Field Description 6–0 CNT[6:0] Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7 Debug State Control Registers There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027).
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7.1 Debug State Control Register 1 (DBGSCR1) Address: 0x0027 R 7 6 5 4 0 0 0 0 0 0 0 W Reset 0 3 2 1 0 SC3 SC2 SC1 SC0 0 0 0 0 = Unimplemented or Reserved Figure 20-9. Debug State Control Register 1 (DBGSCR1) Read: Anytime Write: Anytime when S12XDBG not armed. This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in State1.
PAGE 758
Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7.2 Debug State Control Register 2 (DBGSCR2) Address: 0x0027 R 7 6 5 4 0 0 0 0 0 0 0 W Reset 0 3 2 1 0 SC3 SC2 SC1 SC0 0 0 0 0 = Unimplemented or Reserved Figure 20-10. Debug State Control Register 2 (DBGSCR2) Read: Anytime Write: Anytime when S12XDBG not armed. This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in State2.
PAGE 759
Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7.3 Debug State Control Register 3 (DBGSCR3) Address: 0x0027 R 7 6 5 4 0 0 0 0 0 0 0 W Reset 0 3 2 1 0 SC3 SC2 SC1 SC0 0 0 0 0 = Unimplemented or Reserved Figure 20-11. Debug State Control Register 3 (DBGSCR3) Read: Anytime Write: Anytime when S12XDBG not armed. This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state whilst in State3.
PAGE 760
Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.7.4 Debug Match Flag Register (DBGMFR) Address: 0x0027 R 7 6 5 4 3 2 1 0 0 0 0 0 MC3 MC2 MC1 MC0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 20-12. Debug Match Flag Register (DBGMFR) Read: Anytime Write: Never DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly to a channel.
PAGE 761
Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.1 Debug Comparator Control Register (DBGXCTL) The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map. Address: 0x0028 7 R 0 W Reset 0 6 5 4 3 2 1 0 NDB TAG BRK RW RWE SRC COMPE 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-13.
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Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-27. DBGXCTL Field Descriptions (continued) Field Description 4 BRK Break — This bit controls whether a comparator match terminates a debug session immediately, independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bits DBGBRK[1:0]. 0 The debug session termination is dependent upon the state sequencer and trigger conditions.
PAGE 763
Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.2 Debug Comparator Address High Register (DBGXAH) Address: 0x0029 7 R 0 W Reset 0 6 5 4 3 2 1 0 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 0 0 0 0 0 0 0 = Unimplemented or Reserved Figure 20-15. Debug Comparator Address High Register (DBGXAH) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-29.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.4 Debug Comparator Address Low Register (DBGXAL) Address: 0x002B R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 20-17. Debug Comparator Address Low Register (DBGXAL) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-31.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.6 Debug Comparator Data Low Register (DBGXDL) Address: 0x002D R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 20-19. Debug Comparator Data Low Register (DBGXDL) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-33.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.3.2.8.8 Debug Comparator Data Low Mask Register (DBGXDLM) Address: 0x002F R W Reset 7 6 5 4 3 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Figure 20-21. Debug Comparator Data Low Mask Register (DBGXDLM) Read: Anytime Write: Anytime when S12XDBG not armed. Table 20-35.
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Chapter 20 S12X Debug (S12XDBGV3) Module The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads.
PAGE 768
Chapter 20 S12X Debug (S12XDBGV3) Module before the tagged instruction executes (tagged-type trigger). Whilst tagging the RW, RWE, SZE, and SZ bits are ignored and the comparator register must be loaded with the exact opcode address. If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory.
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Chapter 20 S12X Debug (S12XDBGV3) Module Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs to comparator register contents or when the data bus is equivalent to the comparator register contents. 20.4.2.2 Exact Address Comparator Match (Comparators B and D) Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match qualification functions the same as for comparators A and C.
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Chapter 20 S12X Debug (S12XDBGV3) Module match condition requires that a valid match for both comparators happens on the same bus cycle. A match condition on only one comparator is not valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned address is inside the range. 20.4.2.3.
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Chapter 20 S12X Debug (S12XDBGV3) Module execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device emulation modes. 20.4.3.4 Trigger On XGATE S/W Breakpoint Request The XGATE S/W breakpoint request issues a forced breakpoint request to the S12XCPU immediately independent of S12XDBG settings and triggers the state sequencer into the disarmed state.
PAGE 772
Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.4 State Sequence Control ARM = 0 State 0 (Disarmed) ARM = 1 State1 State2 ARM = 0 Session Complete (Disarm) Final State State3 ARM = 0 Figure 20-23. State Sequencer Diagram The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered.
PAGE 773
Chapter 20 S12X Debug (S12XDBGV3) Module bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug module is disarmed. 20.4.5 Trace Buffer Operation The trace buffer is a 64 lines deep by 64-bits wide RAM array.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.5.1.3 Storing with End-Trigger Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the address of a change of flow instruction the trigger event will not be stored in the Trace Buffer. 20.4.5.2 Trace Modes The S12XDBG module can operate in four trace modes.
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Chapter 20 S12X Debug (S12XDBGV3) Module Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the S12XDBG module is designed to help find.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.5.3 Trace Buffer Organization The buffer can be used to trace either from S12XCPU, from XGATE or from both sources. An X prefix denotes information from the XGATE module, a C prefix denotes information from the S12XCPU. ADRH, ADRM, ADRL denote address high, middle and low byte respectively. INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.5.3.1 Information Byte Organization The format of the control information byte for both S12XCPU and XGATE modules is dependent upon the active trace mode and tracing source as described below. In Normal, Loop1, or Pure PC modes tracing of XGATE activity, XINF is used to store control information. In Normal, Loop1, or Pure PC modes tracing of S12XCPU activity, CINF is used to store control information.
PAGE 778
Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-41. CINF Field Descriptions Field Description 7 CSD Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination address. This is only used in Normal and Loop1 mode tracing. 0 Source Address 1 Destination Address 6 CVA Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. This is only used in Normal and Loop1 mode tracing.
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Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-42. CXINF Field Descriptions (continued) Field Description 5 CRW Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access. This bit only contains valid information when tracing S12XCPU activity in Detail Mode. 0 Write Access 1 Read Access 4 COCF S12XCPU Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch cycle.
PAGE 780
Chapter 20 S12X Debug (S12XDBGV3) Module The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1 and 0 of Table 20-39. The bytes containing invalid information (shaded in Table 20-39) are also read out. Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of the RAM pointer will occur. Reading the trace buffer is not possible if both TSOURCE bits are cleared. 20.4.5.
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Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.6.1 External Tagging using TAGHI and TAGLO External tagging using the external TAGHI and TAGLO pins can only be used to tag S12XCPU opcodes; tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into state0 when the tagged opcode reaches the execution stage of the instruction queue. The pins operate independently, thus the state of one pin does not affect the function of the other.
PAGE 782
Chapter 20 S12X Debug (S12XDBGV3) Module upon the state of the DBGBRK or ARM bits in DBGC1. They depend solely on the state of the XGSBPE and BDM bits. Thus it is not necessary to ARM the DBG module to use XGATE software breakpoints to generate breakpoints in the S12XCPU program flow, but it is necessary to set XGSBPE. Furthermore, if a breakpoint to BDM is required, the BDM bit must also be set.
PAGE 783
Chapter 20 S12X Debug (S12XDBGV3) Module 20.4.7.4 Breakpoints Via TAGHI Or TAGLO Pin Taghits Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is always end aligned, independent of internal channel trigger alignment configuration. 20.4.7.5 Auxilliary Breakpoint Input When this signal asserts tracing is terminated and an immediate forced breakpoints are generated, depending on the configuration of DBGBRK bits. 20.4.7.
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Chapter 20 S12X Debug (S12XDBGV3) Module Table 20-45. Breakpoint Mapping Summary DBGBRK[1] (DBGC1[3]) BDM Bit (DBGC1[4]) BDM Enabled BDM Active S12X Breakpoint Mapping 0 X X X No Breakpoint 1 0 X 0 Breakpoint to SWI 1 0 X 1 No Breakpoint 1 1 0 X Breakpoint to SWI 1 1 1 0 Breakpoint to BDM 1 1 1 1 No Breakpoint BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM.
PAGE 785
Chapter 21 External Bus Interface (S12XEBIV2) 21.1 Introduction This document describes the functionality of the XEBI block controlling the external bus interface. The XEBI controls the functionality of a non-multiplexed external bus (a.k.a. ‘expansion bus’) in relationship with the chip operation modes. Dependent on the mode, the external bus can be used for data exchange with external memory, peripherals or PRU, and provide visibility to the internal bus externally in combination with an emulator. 21.
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Chapter 21 External Bus Interface (S12XEBIV2) 21.1.3 Block Diagram Figure 21-1 is a block diagram of the XEBI with all related I/O signals. ADDR[22:0] DATA[15:0] IVD[15:0] LSTRB R/W EWAIT XEBI UDS LDS RE WE ACC[2:0] IQSTAT[3:0] Figure 21-1. XEBI Block Diagram 21.2 External Signal Description The user is advised to refer to the SoC section for port configuration and location of external bus signals.
PAGE 787
Chapter 21 External Bus Interface (S12XEBIV2) Table 21-1.
PAGE 788
Chapter 21 External Bus Interface (S12XEBIV2) 21.3 Memory Map and Register Definition This section provides a detailed description of all registers accessible in the XEBI. 21.3.1 Module Memory Map The registers associated with the XEBI block are shown in Figure 21-2. Register Name EBICTL0 Bit 7 R W EBICTL1 R W ITHRS EWAITE 6 0 5 4 3 2 1 Bit 0 HDBE ASIZ4 ASIZ3 ASIZ2 ASIZ1 ASIZ0 0 0 0 EXSTR2 EXSTR1 EXSTR0 0 = Unimplemented or Reserved Figure 21-2. XEBI Register Summary 21.3.
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Chapter 21 External Bus Interface (S12XEBIV2) 21.3.2.1 External Bus Interface Control Register 0 (EBICTL0) 7 R W Reset 6 0 ITHRS 0 0 5 4 3 2 1 0 HDBE ASIZ4 ASIZ3 ASIZ2 ASIZ1 ASIZ0 1 1 1 1 1 1 = Unimplemented or Reserved Figure 21-3. External Bus Interface Control Register 0 (EBICTL0) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes, the data are read from this register. Write: Anytime.
PAGE 790
Chapter 21 External Bus Interface (S12XEBIV2) Table 21-3. Input Threshold Levels on External Signals ITHRS External Signal NS SS NX Standard Standard Standard DATA[15:8] TAGHI, TAGLO 0 DATA[7:0] EWAIT DATA[15:8] TAGHI, TAGLO 1 Reduced if HDBE = 1 DATA[7:0] Standard Standard EX ST Reduced Reduced Standard Standard Reduced Reduced Reduced Standard Reduced if EWAITE = 1 Standard Standard Reduced Reduced if EWAITE = 1 EWAIT ES Table 21-4.
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Chapter 21 External Bus Interface (S12XEBIV2) 21.3.2.2 External Bus Interface Control Register 1 (EBICTL1) 7 R W EWAITE Reset 0 6 5 4 3 0 0 0 0 0 0 0 0 2 1 0 EXSTR2 EXSTR1 EXSTR0 1 1 1 = Unimplemented or Reserved Figure 21-4. External Bus Interface Control Register 1 (EBICTL1) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
PAGE 792
Chapter 21 External Bus Interface (S12XEBIV2) 21.4 Functional Description This section describes the functions of the external bus interface. The availability of external signals and functions in relation to the operating mode is initially summarized and described in more detail in separate sub-sections. 21.4.1 Operating Modes and External Bus Properties A summary of the external bus interface functions for each operating mode is shown in Table 21-7. Table 21-7.
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Chapter 21 External Bus Interface (S12XEBIV2) 21.4.2 Internal Visibility Internal visibility allows the observation of the internal MCU address and data bus as well as the determination of the access source and the CPU pipe (queue) status through the external bus interface. Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal CPU and BDM accesses are made visible on the external bus interface, except those to BDM firmware and BDM registers.
PAGE 794
Chapter 21 External Bus Interface (S12XEBIV2) The following terminology is used: ‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins ‘x’ — Undefined output pin values ‘z’ — Tristate pins ‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’ 21.4.2.2.1 Read Access Timing Table 21-9. Read Access (1 Cycle) Access #0 Bus cycle -> ... ECLK phase ... ADDR[22:20] / ACC[2:0] ... ADDR[19:16] / IQSTAT[3:0] ...
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Chapter 21 External Bus Interface (S12XEBIV2) 21.4.2.2.2 Write Access Timing Table 21-12. Write Access (1 Cycle) Bus cycle -> ... ECLK phase ... ADDR[22:20] / ACC[2:0] ... ADDR[19:16] / IQSTAT[3:0] ... Access #0 Access #1 Access #2 1 2 3 high low addr 0 iqstat -1 high low addr 1 iqstat 0 ? ADDR[15:0] / IVD[15:0] ... DATA[15:0] (write) ... ? R/W ... 0 high low ... acc 2 ... addr 2 iqstat 1 ... x ... data 2 ... 1 ... acc 1 acc 0 x data 0 data 1 0 1 ...
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Chapter 21 External Bus Interface (S12XEBIV2) 21.4.2.2.3 Read-Write-Read Access Timing Table 21-15. Interleaved Read-Write-Read Accesses (1 Cycle) Bus cycle -> ... ECLK phase ... ADDR[22:20] / ACC[2:0] ... ADDR[19:16] / IQSTAT[3:0] ... Access #0 Access #1 Access #2 1 2 3 high low addr 0 iqstat -1 low addr 1 iqstat 0 acc 0 ... DATA[15:0] (internal read) ... ? DATA[15:0] (external read) ... R/W ... high low ... acc 2 ... addr 2 iqstat 1 ... x ... z ...
PAGE 797
Chapter 21 External Bus Interface (S12XEBIV2) Stretched accesses are controlled by: 1. EXSTR[2:0] bits in the EBICTL1 register configuring fixed amount of stretch cycles 2. Activation of the external wait feature by EWAITE in EBICTL1 register 3. Assertion of the external EWAIT signal when EWAITE = 1 The EXSTR[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch cycles. If the external wait feature is enabled, the minimum number of additional stretch cycles is 2.
PAGE 798
Chapter 21 External Bus Interface (S12XEBIV2) Table 21-17.
PAGE 799
Chapter 21 External Bus Interface (S12XEBIV2) 21.4.6 Low-Power Options The XEBI does not support any user-controlled options for reducing power consumption. 21.4.6.1 Run Mode The XEBI does not support any options for reducing power in run mode. Power consumption is reduced in single-chip modes due to the absence of the external bus interface.
PAGE 800
Chapter 21 External Bus Interface (S12XEBIV2) 21.5.1 Normal Expanded Mode This mode allows interfacing to external memories or peripherals which are available in the commercial market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each external access. 21.5.1.
PAGE 801
Chapter 21 External Bus Interface (S12XEBIV2) 21.5.2 Emulation Modes In emulation mode applications, the development systems use a custom PRU device to rebuild the single-chip or expanded bus functions which are lost due to the use of the external bus with an emulator. Accesses to a set of registers controlling the related ports in normal modes (refer to SoC section) are directed to the external bus in emulation modes which are substituted by PRR as part of the PRU.
PAGE 802
Chapter 21 External Bus Interface (S12XEBIV2) 21.5.2.1 Example 2a: Emulation Single-Chip Mode This mode is used for emulation systems in which the target application is operating in normal single-chip mode. Figure 21-5 shows the PRU connection with the available external bus signals in an emulator application. S12X_EBI Emulator ADDR[22:0]/IVD[15:0] DATA[15:0] EMULMEM PRU PRR Ports LSTRB R/W ADDR[22:20]/ACC[2:0] ADDR[19:16]/ IQSTAT[3:0] ECLK ECLKX2 Figure 21-5.
PAGE 803
Chapter 21 External Bus Interface (S12XEBIV2) 21.5.2.2 Example 2b: Emulation Expanded Mode This mode is used for emulation systems in which the target application is operating in normal expanded mode. If the external bus is used with a PRU, the external device rebuilds the data select and data direction signals UDS, LDS, RE, and WE from the ADDR0, LSTRB, and R/W signals. Figure 21-6 shows the PRU connection with the available external bus signals in an emulator application.
PAGE 804
Chapter 21 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 805
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.1 Introduction The S12XD family port integration module (below referred to as PIM) establishes the interface between the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins.
PAGE 806
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.1.
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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 Port D DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Port AD1 Port AD0 Port T Port P SCK SS MOSI MISO SS SPI1 SCK MOSI MISO SPI2 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 SS SPI0 SCK MOSI MISO TXD SCI1 RXD TXD SCI0 RXD BKGD/MODC ECLKX2/XCLKS TAGHI/MODB TAGLO/RE/MODA ECLK S12X_EBI LDS/LSTRB S12X_BDM WE/R/W S12X_DBG IRQ XIRQ S12X_INT EWAIT/ROMCTL NOACC/ADDR22 ADDR21 A
PAGE 808
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.2 External Signal Description This section lists and describes the signals that do connect off-chip. 22.2.1 Signal Properties Table 22-1 shows all the pins and their functions that are controlled by the PIM. Refer to Section 22.4, “Functional Description” for the availability of the individual pins in the different package options.
PAGE 809
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1.
PAGE 810
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1.
PAGE 811
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1.
PAGE 812
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1.
PAGE 813
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1.
PAGE 814
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-1.
PAGE 815
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3 Memory Map and Register Definition This section provides a detailed description of all PIM registers. 22.3.1 Module Memory Map Table 22-2 shows the register map of the port integration module. Table 22-2.
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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-2.
PAGE 817
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-2.
PAGE 818
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2 Register Descriptions Table 22-3 summarizes the effect on the various configuration bits, data direction (DDR), output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports. The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active. Table 22-3.
PAGE 819
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name PORTA R W PORTB R W DDRA R W DDRB R W PORTC R W PORTD R W DDRC R W DDRD R W PORTE R W DDRE R W Bit 7 6 5 4 3 2 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 DDRC7 DDRC6 DDRC5
PAGE 820
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name ECLKCTL R W Reserved R Bit 7 6 NECLK NCLKX2 0 0 IRQE IRQEN 0 0 5 4 3 2 1 Bit 0 0 0 0 0 EDIV1 EDIV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W IRQCR R W Reserved R W Non-PIM R Address W Range PORTK R W DDRK R W Non-PIM Address Range PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 DDRK7 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 Non-PIM R Address W Range PTT R W PTIT R Non-PIM Address Rang
PAGE 821
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name Reserved R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 WOMS7 WOMS6 WOMS
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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name PPSM R W WOMM R W MODRR R Bit 7 6 5 4 3 2 1 Bit 0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1
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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name PERH R W PPSH R W PIEH R W PIFH R W PTJ R W PTIJ R Bit 7 6 5 4 3 2 1 Bit 0 PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 PTJ7 PTJ6 PTJ5 PTJ4 PTJ2 PTJ1 PTJ0 PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ2 PTIJ1 PTIJ0 DDRJ7 DDRJ6 DDRJ5 DDRJ4 D
PAGE 824
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Register Name Name Bit 7 R W Reserved R 6 5 4 3 2 1 Bit 0 DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 0 0 0 0 0 0 0 0 W RDR1AD0 R W Reserved R RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0 0 0 0 0 0 0 0 PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 PT0AD123 PT0AD122 PT0AD121 PT0AD120 PT0AD119 PT0AD118 PT0AD117 PT0AD116 PT1AD
PAGE 825
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.1 Port A Data Register (PORTA) 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 ADDR15 mux IVD15 ADDR14 mux IVD14 ADDR13 mux IVD13 ADDR12 mux IVD12 ADDR11 mux IVD11 ADDR10 mux IVD10 ADDR9 mux IVD9 ADDR8 mux IVD8 0 0 0 0 0 0 0 0 R W Alt. Function Reset Figure 22-3. Port A Data Register (PORTA) Read: Anytime.
PAGE 826
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Write: Anytime. In emulation modes, write operations will also be directed to the external bus. Table 22-5. PORTB Field Descriptions Field Description 7–0 PB[7:0] Port B — Port B pins 7–0 are associated with address outputs ADDR7 through ADDR1 respectively in expanded modes. Pin 0 is associated with output ADDR0 in emulation modes and special test mode and with Upper Data Select (UDS) in normal expanded mode.
PAGE 827
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.3 Port A Data Direction Register (DDRA) 7 6 5 4 3 2 1 0 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 R W Reset Figure 22-5. Port A Data Direction Register (DDRA) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
PAGE 828
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.5 Port C Data Register (PORTC) 7 6 5 4 3 2 1 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Exp.: DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 Reset 0 0 0 0 0 0 0 0 R W Figure 22-7. Port C Data Register (PORTC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime.
PAGE 829
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.7 Port C Data Direction Register (DDRC) 7 6 5 4 3 2 1 0 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0 0 0 0 0 0 0 0 R W Reset Figure 22-9. Port C Data Direction Register (DDRC) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
PAGE 830
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.9 Port E Data Register (PORTE) 7 6 5 4 3 2 1 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Alt. Func. XCLKS or ECLKX2 MODB or TAGHI MODA or RE or TAGLO ECLK EROMCTL or LSTRB or LDS R/W or WE IRQ XIRQ Reset 0 0 0 0 0 0 —1 —1 R W = Unimplemented or Reserved Figure 22-11. Port E Data Register (PORTE) 1 These registers are reset to zero.
PAGE 831
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.10 Port E Data Direction Register (DDRE) 7 6 5 4 3 2 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0 0 0 0 0 R 1 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 22-12. Port E Data Direction Register (DDRE) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
PAGE 832
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.11 S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) 7 6 PUPKE BKPUE 1 1 5 R 4 3 2 1 0 PUPEE PUPDE PUPCE PUPBE PUPAE 1 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 22-13. S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) Read: Anytime in single-chip modes. Write: Anytime, except BKPUE which is writable in special test mode only.
PAGE 833
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.12 S12X_EBI Ports Reduced Drive Register (RDRIV) 7 R 6 5 0 0 RDPK 4 3 2 1 0 RDPE RDPD RDPC RDPB RDPA 0 0 0 0 0 W Reset 0 0 0 = Unimplemented or Reserved Figure 22-14. S12X_EBI Ports Reduced Drive Register (RDRIV) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
PAGE 834
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.
PAGE 835
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-16. ECLKCTL Field Descriptions (continued) Field Description 6 NCLKX2 No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other operating modes.
PAGE 836
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.15 Port K Data Register (PORTK) 7 6 5 4 3 2 1 0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 Alt. Func. ROMCTL or EWAIT ADDR22 mux NOACC ADDR21 ADDR20 ADDR19 mux IQSTAT3 ADDR18 mux IQSTAT2 ADDR17 mux IQSTAT1 ADDR16 mux IQSTAT0 Reset 0 0 0 0 0 0 0 0 R W Figure 22-17. Port K Data Register (PORTK) Read: Anytime.
PAGE 837
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-20. DDRK Field Descriptions Field Description 7–0 DDRK[7:0] Data Direction Port K 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTK after changing the DDRK register. MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 838
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.17 Port T Data Register (PTT) 7 6 5 4 3 2 1 0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0 0 0 0 0 0 0 0 R W ECT Reset Figure 22-19. Port T Data Register (PTT) Read: Anytime. Write: Anytime. Table 22-21. PTT Field Descriptions Field Description 7–0 PTT[7:0] Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section).
PAGE 839
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.19 Port T Data Direction Register (DDRT) 7 6 5 4 3 2 1 0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 22-21. Port T Data Direction Register (DDRT) Read: Anytime. Write: Anytime. This register configures each port T pin as either input or output. The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare.
PAGE 840
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.20 Port T Reduced Drive Register (RDRT) 7 6 5 4 3 2 1 0 RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 22-22. Port T Reduced Drive Register (RDRT) Read: Anytime. Write: Anytime. This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-24.
PAGE 841
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.22 Port T Polarity Select Register (PPST) 7 6 5 4 3 2 1 0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 R W Reset Figure 22-24. Port T Polarity Select Register (PPST) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. Table 22-26.
PAGE 842
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.24 Port S Input Register (PTIS) R 7 6 5 4 3 2 1 0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 22-26. Port S Input Register (PTIS) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
PAGE 843
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.25 Port S Data Direction Register (DDRS) 7 6 5 4 3 2 1 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 22-27. Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime. This register configures each port S pin as either input or output. If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
PAGE 844
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.26 Port S Reduced Drive Register (RDRS) 7 6 5 4 3 2 1 0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 22-28. Port S Reduced Drive Register (RDRS) Read: Anytime. Write: Anytime. This register configures the drive strength of each port S output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-28.
PAGE 845
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.28 Port S Polarity Select Register (PPSS) 7 6 5 4 3 2 1 0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 0 0 0 0 0 0 0 0 R W Reset Figure 22-30. Port S Polarity Select Register (PPSS) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. Table 22-30.
PAGE 846
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.30 Port M Data Register (PTM) 7 6 5 4 3 2 1 0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 TXCAN3 RXCAN3 TXCAN2 RXCAN2 TXCAN1 RXCAN1 TXCAN0 RXCAN0 TXCAN0 RXCAN0 TXCAN0 RXCAN0 TXCAN4 RXCAN4 SCK0 MOSI0 SS0 MISO0 0 0 0 0 0 0 R W CAN Routed CAN0 Routed CAN4 TXCAN4 RXCAN4 Routed SPIO Reset 0 0 Figure 22-32. Port M Data Register (PTM) Read: Anytime. Write: Anytime.
PAGE 847
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-32. PTM Field Descriptions (continued) Field Description 3–2 PTM[3:2] The CAN1 function (TXCAN1 and RXCAN1) takes precedence over the routed CAN0, the routed SPI0 and the general purpose I/O function if the CAN1 module is enabled. The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. Refer to MSCAN section for details.
PAGE 848
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.31 Port M Input Register (PTIM) R 7 6 5 4 3 2 1 0 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 22-33. Port M Input Register (PTIM) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
PAGE 849
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.32 Port M Data Direction Register (DDRM) 7 6 5 4 3 2 1 0 DDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 0 0 0 0 0 0 0 0 R W Reset Figure 22-34. Port M Data Direction Register (DDRM) Read: Anytime. Write: Anytime. This register configures each port M pin as either input or output. The CAN/SCI3 forces the I/O state to be an output for each port line associated with an enabled output (TXCAN[3:0], TXD3).
PAGE 850
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.33 Port M Reduced Drive Register (RDRM) 7 6 5 4 3 2 1 0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 0 0 0 0 0 0 0 0 R W Reset Figure 22-35. Port M Reduced Drive Register (RDRM) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port M output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-34.
PAGE 851
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.35 Port M Polarity Select Register (PPSM) 7 6 5 4 3 2 1 0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 0 0 0 0 R W Reset Figure 22-37. Port M Polarity Select Register (PPSM) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. If CAN is active a pull-up device can be activated on the RXCAN[3:0] inputs, but not a pull-down. Table 22-36.
PAGE 852
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.37 Module Routing Register (MODRR) 7 R 6 5 4 3 2 1 0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 22-39. Module Routing Register (MODRR) Read: Anytime. Write: Anytime. This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports. Table 22-38.
PAGE 853
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.38 Port P Data Register (PTP) 7 6 5 4 3 2 1 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PWM PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 SPI SCK2 SS2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 0 0 0 0 0 0 0 0 R W Reset Figure 22-40. Port P Data Register (PTP) Read: Anytime. Write: Anytime. Port P pins 7, and 5–0 are associated with the PWM as well as the SPI1 and SPI2 modules.
PAGE 854
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.39 Port P Input Register (PTIP) R 7 6 5 4 3 2 1 0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 22-41. Port P Input Register (PTIP) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
PAGE 855
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.40 Port P Data Direction Register (DDRP) 7 6 5 4 3 2 1 0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 22-42. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output. If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
PAGE 856
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.41 Port P Reduced Drive Register (RDRP) 7 6 5 4 3 2 1 0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 22-43. Port P Reduced Drive Register (RDRP) Read: Anytime. Write: Anytime. This register configures the drive strength of each port P output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-40.
PAGE 857
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.43 Port P Polarity Select Register (PPSP) 7 6 5 4 3 2 1 0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 0 0 0 0 0 0 0 0 R W Reset Figure 22-45. Port P Polarity Select Register (PPSP) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Table 22-42.
PAGE 858
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.45 Port P Interrupt Flag Register (PIFP) 7 6 5 4 3 2 1 0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 0 0 0 0 0 0 0 0 R W Reset Figure 22-47. Port P Interrupt Flag Register (PIFP) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSP register.
PAGE 859
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.46 Port H Data Register (PTH) 7 6 5 4 3 2 1 0 PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 SS2 SCK2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 0 0 0 0 0 0 0 0 R W Routed SPI Reset Figure 22-48. Port H Data Register (PTH) Read: Anytime. Write: Anytime. Port H pins 7–0 are associated with the SCI4 and SCI5 as well as the routed SPI1 and SPI2 modules.
PAGE 860
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.47 Port H Input Register (PTIH) R 7 6 5 4 3 2 1 0 PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 22-49. Port H Input Register (PTIH) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
PAGE 861
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.48 Port H Data Direction Register (DDRH) 7 6 5 4 3 2 1 0 DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 0 0 0 0 0 0 0 0 R W Reset Figure 22-50. Port H Data Direction Register (DDRH) Read: Anytime. Write: Anytime. This register configures each port H pin as either input or output. If the associated SCI channel or routed SPI module is enabled this register has no effect on the pins.
PAGE 862
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.49 Port H Reduced Drive Register (RDRH) 7 6 5 4 3 2 1 0 RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 0 0 0 0 0 0 0 0 R W Reset Figure 22-51. Port H Reduced Drive Register (RDRH) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port H output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-46.
PAGE 863
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.51 Port H Polarity Select Register (PPSH) 7 6 5 4 3 2 1 0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 0 0 0 0 0 0 0 0 R W Reset Figure 22-53. Port H Polarity Select Register (PPSH) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Table 22-48.
PAGE 864
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.53 Port H Interrupt Flag Register (PIFH) 7 6 5 4 3 2 1 0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 0 0 0 0 0 0 0 0 R W Reset Figure 22-55. Port H Interrupt Flag Register (PIFH) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSH register.
PAGE 865
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.54 Port J Data Register (PTJ) 7 6 5 4 PTJ7 PTJ6 PTJ5 PTJ4 TXCAN4 RXCAN4 SCL0 SDA0 R 3 2 1 0 PTJ2 PTJ1 PTJ0 TXD2 RXD2 0 W CAN4/ SCI2 IICO IIC1 Routed CAN0 TXCAN0 SDA1 CS2 CS0 0 0 RXCAN0 Alt. Function Reset SCL1 0 0 CS1 0 0 CS3 0 0 = Unimplemented or Reserved Figure 22-56. Port J Data Register (PTJ) Read: Anytime. Write: Anytime.
PAGE 866
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-51. PTJ Field Descriptions (continued) Field Description 1 PJ1 The SCI2 function takes precedence over the general purpose I/O function if the SCI2 module is enabled. Refer to SCI section for details. 0 PJ0 The SCI2 function takes precedence over the chip select (CS3) and the general purpose I/O function if the SCI2 module is enabled. The chip select (CS3) takes precedence over the general purpose I/O function.
PAGE 867
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.55 Port J Input Register (PTIJ) R 7 6 5 4 3 2 1 0 PTIJ7 PTIJ6 PTIJ5 PTIJ4 0 PTIJ2 PTIJ1 PTIJ0 0 0 0 0 0 0 0 0 W Reset1 = Unimplemented or Reserved Figure 22-57. Port J Input Register (PTIJ) 1 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
PAGE 868
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.56 Port J Data Direction Register (DDRJ) 7 6 5 4 3 DDRJ7 DDRJ6 DDRJ5 DDRJ4 0 0 0 0 R 2 1 0 DDRJ2 DDRJ1 DDRJ0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 22-58. Port J Data Direction Register (DDRJ) Read: Anytime. Write: Anytime. This register configures each port J pin as either input or output. The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6 (RXCAN4).
PAGE 869
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.57 Port J Reduced Drive Register (RDRJ) 7 6 5 4 3 RDRJ7 RDRJ6 RDRJ5 RDRJ4 0 0 0 0 R 2 1 0 RDRJ2 RDRJ1 RDRJ0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 22-59. Port J Reduced Drive Register (RDRJ) Read: Anytime. Write: Anytime. This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-53.
PAGE 870
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.59 Port J Polarity Select Register (PPSJ) 7 6 5 4 3 PPSJ7 PPSJ6 PPSJ5 PPSJ4 0 0 0 0 R 2 1 0 PPSJ2 PPSJ1 PPSJ0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 22-61. Port J Polarity Select Register (PPSJ) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Table 22-55.
PAGE 871
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.61 Port J Interrupt Flag Register (PIFJ) 7 6 5 4 PIFJ7 PIFJ6 PIFJ5 PIFJ4 0 0 0 0 3 R 2 1 0 PIFJ2 PIFJ1 PIFJ0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 22-63. Port J Interrupt Flag Register (PIFJ) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSJ register.
PAGE 872
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0) 7 6 5 4 3 2 1 0 DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 22-65. Port AD0 Data Direction Register 1 (DDR1AD0) Read: Anytime. Write: Anytime. This register configures pins PAD[07:00] as either input or output. Table 22-58.
PAGE 873
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.64 Port AD0 Reduced Drive Register 1 (RDR1AD0) 7 6 5 4 3 2 1 0 RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 22-66. Port AD0 Reduced Drive Register 1 (RDR1AD0) Read: Anytime. Write: Anytime. This register configures the drive strength of each output pin PAD[07:00] as either full or reduced. If the port is used as input this bit is ignored. Table 22-59.
PAGE 874
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.66 Port AD1 Data Register 0 (PT0AD1) 7 6 5 4 3 2 1 0 PT0AD123 PT0AD122 PT0AD121 PT0AD120 PT0AD119 PT0AD118 PT0AD117 PT0AD116 0 0 0 0 0 0 0 0 R W Reset Figure 22-68. Port AD1 Data Register 0 (PT0AD1) Read: Anytime. Write: Anytime. This register is associated with AD1 pins PAD[23:16]. These pins can also be used as general purpose I/O.
PAGE 875
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.68 Port AD1 Data Direction Register 0 (DDR0AD1) 7 6 5 4 3 2 1 0 R DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116 W Reset 0 0 0 0 0 0 0 0 Figure 22-70. Port AD1 Data Direction Register 0 (DDR0AD1) Read: Anytime. Write: Anytime. This register configures pin PAD[23:16] as either input or output. Table 22-61.
PAGE 876
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.69 Port AD1 Data Direction Register 1 (DDR1AD1) 7 6 5 4 3 2 1 0 R DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18 W Reset 0 0 0 0 0 0 0 0 Figure 22-71. Port AD1 Data Direction Register 1 (DDR1AD1) Read: Anytime. Write: Anytime. This register configures pins PAD[15:08] as either input or output. Table 22-62.
PAGE 877
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.70 Port AD1 Reduced Drive Register 0 (RDR0AD1) 7 6 5 4 3 2 1 0 R RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116 W Reset 0 0 0 0 0 0 0 0 Figure 22-72. Port AD1 Reduced Drive Register 0 (RDR0AD1) Read: Anytime. Write: Anytime. This register configures the drive strength of each PAD[23:16] output pin as either full or reduced. If the port is used as input this bit is ignored. Table 22-63.
PAGE 878
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.3.2.72 Port AD1 Pull Up Enable Register 0 (PER0AD1) 7 6 5 4 3 2 1 0 R PER0AD123 PER0AD122 PER0AD121 PER0AD120 PER0AD119 PER0AD118 PER0AD117 PER0AD116 W Reset 0 0 0 0 0 0 0 0 Figure 22-74. Port AD1 Pull Up Enable Register 0 (PER0AD1) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective PAD[23:16] pin if the port is used as input. This bit has no effect if the port is used as output.
PAGE 879
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4 Functional Description Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an output from the external bus interface module or a peripheral module or an input to the external bus interface module or a peripheral module. A set of configuration registers is common to all ports with exceptions in the expanded bus interface and ATD ports (Table 22-67).
PAGE 880
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.1.2 Input Register This is a read-only register and always returns the buffered state of the pin (Figure 22-76). 22.4.1.3 Data Direction Register This register defines whether the pin is used as an input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 22-76). PTI 0 1 PT 0 PIN 1 DDR 0 1 data out Module output enable module enable Figure 22-76.
PAGE 881
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.1.8 Interrupt Enable Register If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable the interrupt. 22.4.1.9 Interrupt Flag Register If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event. 22.4.1.10 Module Routing Register This register supports the re-routing of the CAN0, CAN4, SPI0, SPI1, and SPI2 pins to alternative ports.
PAGE 882
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.2.3 Port C and D Port C pins PC[7:0] and port D pins PD[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the external bus interface. In this case port C and port D are associated with the external data bus inputs/outputs DATA15–DATA8 and DATA7–DATA0, respectively. These pins are configured for reduced input threshold in certain operating modes (refer to S12X_EBI section).
PAGE 883
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.2.6 Port T This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the enhanced capture timer. 22.4.2.7 Port S This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:0] can be used either for generalpurpose I/O, or with the SCI and SPI subsystems. The SPI0 pins can be re-routed. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”.
PAGE 884
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.2.10 Port H This port is associated with the SPI1, SPI2, SCI4, and SCI5. Port H pins PH[7:0] can be used for either general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1 and SPI2 modules. Refer to Section 22.3.2.37, “Module Routing Register (MODRR)”. Port H offers 8 I/O pins with edge triggered interrupt capability (Section 22.4.3, “Pin Interrupts”).
PAGE 885
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) 22.4.3 Pin Interrupts Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
PAGE 886
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly. The filters are continuously clocked by the bus clock in run and wait mode. In stop mode, the clock is generated by an RC-oscillator in the port integration module.
PAGE 887
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) Table 22-70.
PAGE 888
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) • Power consumption will increase the more the voltages on general purpose input pins deviate from the supply voltages towards mid-range because the digital input buffers operate in the linear region. MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 889
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 890
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 891
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 892
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 893
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 894
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 895
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 896
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 897
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 898
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 899
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Introduction The S12XD family port integration module (below referred to as PIM) establishes the interface between the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins.
PAGE 900
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) • • • • • • • • • • Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P, H, and J on per-pin basis Control registers to enable/disable pull-up devices on Ports AD0, and AD1 on per-pin basis Single control register to enable/disable pull-ups on Ports A, B, C, D, E, and K on per-port basis and on BKGD pin Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, AD0, and AD1 on
PAGE 901
DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 Port D DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Port AD1 Port AD0 Port T PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 SS SPI0 SCK MOSI MISO TXD SCI1 RXD TXD SCI0 RXD BKGD/MODC ECLKX2/XCLKS TAGHI/MODB TAGLO/RE/MODA ECLK S12X_EBI LDS/LSTRB S12X_BDM WE/R/W S12X_DBG IRQ XIRQ S12X_INT EWAIT/ROMCTL NOACC/ADDR22 ADDR21 ADRR20 ADDR19 ADDR18 ADDR17 ADDR16 Figure 23-1.
PAGE 902
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) External Signal Description This section lists and describes the signals that do connect off-chip. 23.0.3 Signal Properties Table 23-1 shows all the pins and their functions that are controlled by the PIM. Refer to Section , “Functional Description” for the availability of the individual pins in the different package options.
PAGE 903
Table 23-1.
PAGE 904
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-1.
PAGE 905
Table 23-1. Pin Functions and Priorities (Sheet 4 of 7) Port Pin Name Pin Function and Priority I/O TXCAN4 O MSCAN4 transmit pin GPIO I/O General-purpose I/O RXCAN4 I MSCAN4 receive pin GPIO I/O General-purpose I/O TXCAN2 O MSCAN2 transmit pin TXCAN0 O MSCAN0 transmit pin TXCAN4 O MSCAN4 transmit pin SCK0 I/O Serial Peripheral Interface 0 serial clock pin If CAN0 is routed to PM[3:2] the SPI0 can still be used in bidirectional master mode.
PAGE 906
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-1.
PAGE 907
Table 23-1.
PAGE 908
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-1.
PAGE 909
Table 23-2.
PAGE 910
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-2.
PAGE 911
Table 23-2.
PAGE 912
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-3.
PAGE 913
Register Name PORTC R W PORTD R W DDRC R W DDRD R W PORTE R W DDRE R W Bit 7 6 5 4 3 2 1 Bit 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0 R Non-PIM W Address Range PUCR R W RDRIV R W Non-PIM Address Range PUPKE RDPK BKPUE 0 0 W Reserved R PUPDE
PAGE 914
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Register Name Bit 7 6 5 Non-PIM R Address W Range PORTK R W DDRK R W R W PTIT R 3 2 1 Bit 0 Non-PIM Address Range PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 DDRK7 DDRK6 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 Non-PIM R Address W Range PTT 4 Non-PIM Address Range PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 RDRT7 RDR
PAGE 915
Register Name DDRS R W RDRS R W PERS R W PPSS R W WOMS R W Reserved R Bit 7 6 5 4 3 2 1 Bit 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 0 0 0 0 0 0 0 0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM
PAGE 916
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Register Name PTIP R Bit 7 6 5 4 3 2 1 Bit 0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 PTH7
PAGE 917
Register Name PTJ R W PTIJ R Bit 7 6 5 4 PTJ7 PTJ6 PTJ5 PTJ4 PTIJ7 PTIJ6 PTIJ5 PTIJ4 DDRJ7 DDRJ6 DDRJ5 DDRJ4 RDRJ7 RDRJ6 RDRJ5 RDRJ4 PERJ7 PERJ6 PERJ5 PERJ4 PPSJ7 PPSJ6 PPSJ5 PPSJ4 PIEJ7 PIEJ6 PIEJ5 PIEJ4 PPSJ7 PPSJ6 PPSJ5 PPSJ4 0 0 0 0 PT1AD07 PT1AD06 PT1AD05 0 0 0 3 2 1 Bit 0 PTJ2 PTJ1 PTJ0 PTIJ2 PTIJ1 PTIJ0 DDRJ2 DDRJ1 DDRJ0 RDRJ2 RDRJ1 RDRJ0 PERJ2 PERJ1 PERJ0 PPSJ2 PPSJ1 PPSJ0 PIEJ2 PIEJ1 PIEJ0 PPSJ2 PPSJ1 PPSJ0 0 0 0 0 PT
PAGE 918
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Register Name PER1AD0 R W PT0AD1 R W PT1AD1 R W DDR0AD1 R W DDR1AD1 R W RDR0AD1 R W RDR1AD1 R W PER0AD1 R W PER1AD1 R W Bit 7 6 5 4 3 2 1 Bit 0 PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 PT0AD123 PT0AD122 PT0AD121 PT0AD120 PT0AD119 PT0AD118 PT0AD117 PT0AD116 PT1AD115 PT1AD114 PT1AD113 PT1AD112 PT1AD111 PT1AD110 PT1AD19 PT1AD18 DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD11
PAGE 919
Table 23-4. PORTA Field Descriptions Field Description 7–0 PA[7:0] Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively inexpanded modesWhen this port is not used for external addresses, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. 23.0.5.
PAGE 920
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-6. DDRA Field Descriptions Field Description 7–0 DDRA[7:0] Data Direction Port A — This register controls the data direction for port A. When Port A is operating as a general purpose I/O port, DDRA determines whether each pin is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input. 0 Associated pin is configured as input.
PAGE 921
Table 23-8. PORTC Field Descriptions Field Description 7–0 PC[7:0] Port C — Port C pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. 23.0.5.6 Port D Data Register (PORTD) 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0 0 0 0 0 0 0 R W Reset Figure 23-8. Port D Data Register (PORTD) Read: Anytime.
PAGE 922
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.8 Port D Data Direction Register (DDRD) 7 6 5 4 3 2 1 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 R W Reset Figure 23-10. Port D Data Direction Register (DDRD) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data are read from this register. Write: Anytime.
PAGE 923
Table 23-12. PORTE Field Descriptions Field Description 7–0 PE[7:0] Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include mode select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI, TAGLO), Read/Write (R/W), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ.
PAGE 924
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.11 S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) 7 6 PUPKE BKPUE 1 1 5 R 4 3 2 1 0 PUPEE PUPDE PUPCE PUPBE PUPAE 1 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 23-13. S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) Read: Anytime in single-chip modes. Write: Anytime, except BKPUE which is writable in special test mode only.
PAGE 925
23.0.5.12 S12X_EBI Ports Reduced Drive Register (RDRIV) 7 R 6 5 0 0 RDPK 4 3 2 1 0 RDPE RDPD RDPC RDPB RDPA 0 0 0 0 0 W Reset 0 0 0 = Unimplemented or Reserved Figure 23-14. S12X_EBI Ports Reduced Drive Register (RDRIV) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime.
PAGE 926
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.
PAGE 927
Table 23-16. ECLKCTL Field Descriptions (continued) Field Description 6 NCLKX2 No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other operating modes. 0 ECLKX2 is enabled 1 ECLKX2 is disabled 1–0 EDIV[1:0] Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin.
PAGE 928
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.15 Port K Data Register (PORTK) 7 6 5 4 3 2 1 0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 Alt. Func. ROMCTL or EWAIT ADDR22 mux NOACC ADDR21 ADDR20 ADDR19 mux IQSTAT3 ADDR18 mux IQSTAT2 ADDR17 mux IQSTAT1 ADDR16 mux IQSTAT0 Reset 0 0 0 0 0 0 0 0 R W Figure 23-17. Port K Data Register (PORTK) Read: Anytime.
PAGE 929
Table 23-20. DDRK Field Descriptions Field Description 7–0 DDRK[7:0] Data Direction Port K 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PORTK after changing the DDRK register. 23.0.5.
PAGE 930
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-22. PTIT Field Descriptions Field Description 7–0 PTIT[7:0] Port T Input — This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. 23.0.5.19 Port T Data Direction Register (DDRT) 7 6 5 4 3 2 1 0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 0 0 0 0 0 0 0 0 R W Reset Figure 23-21.
PAGE 931
This register configures the drive strength of each port T output pin as either full or reduced. If the port is used as input this bit is ignored. Table 23-24. RDRT Field Descriptions Field 7–0 RDRT[7:0] Description Reduced Drive Port T 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 23.0.5.
PAGE 932
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-26. PPST Field Descriptions Field Description 7–0 PPST[7:0] Pull Select Port T 0 A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. 1 A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT and if the port is used as input. 23.0.5.
PAGE 933
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins. This also can be used to detect overload or short circuit conditions on output pins. 23.0.5.25 Port S Data Direction Register (DDRS) 7 6 5 4 3 2 1 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 0 0 0 0 0 0 0 0 R W Reset Figure 23-27. Port S Data Direction Register (DDRS) Read: Anytime. Write: Anytime.
PAGE 934
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) This register configures the drive strength of each port S output pin as either full or reduced. If the port is used as input this bit is ignored. Table 23-28. RDRS Field Descriptions Field 7–0 RDRS[7:0] Description Reduced Drive Port S 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 23.0.5.
PAGE 935
Table 23-30. PPSS Field Descriptions Field Description 7–0 PPSS[7:0] Pull Select Port S 0 A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input or as wired-OR output. 1 A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS and if the port is used as input. 23.0.5.
PAGE 936
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.30 Port M Data Register (PTM) 7 6 5 4 3 2 1 0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 CAN TXCAN2 RXCAN2 TXCAN1 RXCAN1 TXCAN0 RXCAN0 Routed CAN0 TXCAN0 RXCAN0 TXCAN0 RXCAN0 TXCAN4 RXCAN4 SCK0 MOSI0 SS0 MISO0 0 0 0 0 0 0 R W Routed CAN4 TXCAN4 RXCAN4 Routed SPI0 Reset 0 0 Figure 23-32. Port M Data Register (PTM) Read: Anytime. Write: Anytime.
PAGE 937
23.0.5.31 Port M Input Register (PTIM) R 7 6 5 4 3 2 1 0 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 23-33. Port M Input Register (PTIM) 1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
PAGE 938
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.33 Port M Reduced Drive Register (RDRM) 7 6 5 4 3 2 1 0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 0 0 0 0 0 0 0 0 R W Reset Figure 23-35. Port M Reduced Drive Register (RDRM) Read: Anytime. Write: Anytime. This register configures the drive strength of each Port M output pin as either full or reduced. If the port is used as input this bit is ignored. Table 23-34.
PAGE 939
23.0.5.35 Port M Polarity Select Register (PPSM) 7 6 5 4 3 2 1 0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 0 0 0 0 0 0 0 0 R W Reset Figure 23-37. Port M Polarity Select Register (PPSM) Read: Anytime. Write: Anytime. This register selects whether a pull-down or a pull-up device is connected to the pin. If CAN is active, a pull-up device can be activated on the related RXCAN inputs, but not a pull-down. Table 23-36.
PAGE 940
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.37 Module Routing Register (MODRR) 7 R 6 5 4 3 2 1 0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 0 0 0 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 23-39. Module Routing Register (MODRR) Read: Anytime. Write: Anytime. This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports. Table 23-38.
PAGE 941
23.0.5.38 Port P Data Register (PTP) 7 6 5 4 3 2 1 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PWM PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 SPI SCK2 SS2 MOSI2 MISO2 SS1 SCK1 MOSI1 MISO1 0 0 0 0 0 0 0 0 R W Reset Figure 23-40. Port P Data Register (PTP) Read: Anytime. Write: Anytime. Port P pins 7–0 are associated with the PWM as well as the SPI1 and SPI2. These pins can be used as general purpose I/O when not used with any of the peripherals.
PAGE 942
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.40 Port P Data Direction Register (DDRP) 7 6 5 4 3 2 1 0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 23-42. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output. If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
PAGE 943
Table 23-40. RDRP Field Descriptions Field 7–0 RDRP[7:0] Description Reduced Drive Port P 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 23.0.5.42 Port P Pull Device Enable Register (PERP) 7 6 5 4 3 2 1 0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 0 0 0 0 0 0 0 0 R W Reset Figure 23-44. Port P Pull Device Enable Register (PERP) Read: Anytime. Write: Anytime.
PAGE 944
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-42. PPSP Field Descriptions Field Description 7–0 PPSP[7:0] Polarity Select Port P 0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.
PAGE 945
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSP register. To clear this flag, write logic level “1” to the corresponding bit in the PIFP register. Writing a “0” has no effect. Table 23-44. PIFP Field Descriptions Field 7–0 PIFP[7:0] Description Interrupt Flags Port P 0 No active edge pending. Writing a “0” has no effect.
PAGE 946
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.47 Port H Input Register (PTIH) R 7 6 5 4 3 2 1 0 PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 — — — — — — — — W Reset1 = Unimplemented or Reserved Figure 23-49. Port H Input Register (PTIH) 1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect.
PAGE 947
Table 23-45. DDRH Field Descriptions Field Description 7–0 DDRH[7:0] Data Direction Port H 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTH or PTIH registers, when changing the DDRH register. 23.0.5.
PAGE 948
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-47. PERH Field Descriptions Field 7–0 PERH[7:0] Description Pull Device Enable Port H 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 23.0.5.51 Port H Polarity Select Register (PPSH) 7 6 5 4 3 2 1 0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 0 0 0 0 0 0 0 0 R W Reset Figure 23-53. Port H Polarity Select Register (PPSH) Read: Anytime. Write: Anytime.
PAGE 949
Table 23-49. PIEH Field Descriptions Field 7–0 PIEH[7:0] Description Interrupt Enable Port H 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. 23.0.5.53 Port H Interrupt Flag Register (PIFH) 7 6 5 4 3 2 1 0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 0 0 0 0 0 0 0 0 R W Reset Figure 23-55. Port H Interrupt Flag Register (PIFH) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin.
PAGE 950
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.54 Port J Data Register (PTJ) 7 6 5 4 PTJ7 PTJ6 PTJ5 PTJ4 TXCAN4 RXCAN4 R 3 2 1 0 PTJ2 PTJ1 PTJ0 TXD2 RXD2 0 W CAN4 SCI2 IIC0 Routed CAN0 SCL0 SDA0 TXCAN0 RXCAN0 Alt. Function Reset 0 0 CS2 CS0 0 0 CS1 0 0 CS3 0 0 = Unimplemented or Reserved Figure 23-56. Port J Data Register (PTJ) Read: Anytime. Write: Anytime.
PAGE 951
23.0.5.55 Port J Input Register (PTIJ) R 7 6 5 4 3 2 1 0 PTIJ7 PTIJ6 PTIJ5 PTIJ4 0 PTIJ2 PTIJ1 PTIJ0 0 0 0 0 0 0 0 0 W Reset1 = Unimplemented or Reserved Figure 23-57. Port J Input Register (PTIJ) 1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins.
PAGE 952
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-52. DDRJ Field Descriptions Field Description 7–0 DDRJ[7:4] DDRJ[2:0] Data Direction Port J 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTJ or PTIJ registers, when changing the DDRJ register. 23.0.5.
PAGE 953
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. Table 23-54. PERJ Field Descriptions Field 7–0 PERJ[7:4] PERJ[2:0] Description Pull Device Enable Port J 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 23.0.5.
PAGE 954
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port J. Table 23-56. PIEJ Field Descriptions Field 7–0 PIEJ[7:4] PIEJ[2:0] Description Interrupt Enable Port J 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. 23.0.5.
PAGE 955
This register is associated with AD0 pins PAD[23:10]. These pins can also be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. 23.0.5.63 Port AD0 Data Direction Register 1 (DDR1AD0) 7 6 5 4 3 2 1 0 DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 23-65.
PAGE 956
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-59. RDR1AD0 Field Descriptions Field Description 7–0 RDR1AD0[7:0] Reduced Drive Port AD0 Register 1 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 23.0.5.65 Port AD0 Pull Up Enable Register 1 (PER1AD0) 7 6 5 4 3 2 1 0 PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00 0 0 0 0 0 0 0 0 R W Reset Figure 23-67.
PAGE 957
23.0.5.67 Port AD1 Data Register 1 (PT1AD1) 7 6 5 4 3 2 1 0 PT1AD115 PT1AD114 PT1AD113 PT1AD112 PT1AD111 PT1AD110 PT1AD19 PT1AD18 0 0 0 0 0 0 0 0 R W Reset Figure 23-69. Port AD1 Data Register 1 (PT1AD1) Read: Anytime. Write: Anytime. This register is associated with AD1 pins PAD[15:8]. These pins can also be used as general purpose I/O.
PAGE 958
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.69 Port AD1 Data Direction Register 1 (DDR1AD1) 7 6 5 4 3 2 1 0 R DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18 W Reset 0 0 0 0 0 0 0 0 Figure 23-71. Port AD1 Data Direction Register 1 (DDR1AD1) Read: Anytime. Write: Anytime. This register configures pins PAD as either input or output. Table 23-62.
PAGE 959
23.0.5.71 Port AD1 Reduced Drive Register 1 (RDR1AD1) 7 6 5 4 3 2 1 0 R RDR1AD115 RDR1AD114 RDR1AD113 RDR1AD112 RDR1AD111 RDR1AD110 RDR1AD19 RDR1AD18 W Reset 0 0 0 0 0 0 0 0 Figure 23-73. Port AD1 Reduced Drive Register 1 (RDR1AD1) Read: Anytime. Write: Anytime. This register configures the drive strength of each PAD[15:8] output pin as either full or reduced. If the port is used as input this bit is ignored. Table 23-64.
PAGE 960
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.5.73 Port AD1 Pull Up Enable Register 1 (PER1AD1) 7 6 5 4 3 2 1 0 PER1AD19 PER1AD18 0 0 R PER1AD115 PER1AD114 PER1AD113 PER1AD112 PER1AD111 PER1AD110 W Reset 0 0 0 0 0 0 Figure 23-75. Port AD1 Pull Up Enable Register 1 (PER1AD1) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective PAD[15:8] pin if the port is used as input. This bit has no effect if the port is used as output.
PAGE 961
Table 23-67. Register Availability per Port1 Port Data Data Direction Input Reduced Drive Pull Enable Polarity Select Wired-OR Mode Interrupt Enable Interrupt Flag P yes yes yes yes yes yes — yes yes H yes yes yes yes yes yes — yes yes J yes yes yes yes yes yes — yes yes AD0 yes yes — yes yes — — — — AD1 yes yes — yes yes — — — — 1. Each cell represents one register with individual configuration bits 23.0.6 23.0.6.
PAGE 962
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) PTI 0 1 PT 0 PIN 1 DDR 0 1 data out Module output enable module enable Figure 23-76. Illustration of I/O Pin Functionality 23.0.6.4 Reduced Drive Register If the pin is used as an output this register allows the configuration of the drive strength. 23.0.6.5 Pull Device Enable Register This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input or as a wired-OR output. 23.0.6.
PAGE 963
23.0.6.10 Module Routing Register This register supports the re-routing of the CAN0, CAN4, SPI0, SPI1, and SPI2 pins to alternative ports. This allows a software re-configuration of the pinouts of the different package options with respect to above peripherals. NOTE The purpose of the module routing register is to provide maximum flexibility for derivatives with a lower number of MSCAN and SPI modules. Table 23-68.
PAGE 964
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) 23.0.7.4 Port E Port E is associated with the external bus control outputs R/W, LSTRB, LDS and RE, the free-running clock outputs ECLK and ECLK2X, as well as with the TAGHI, TAGLO, MODA and MODB and interrupt inputs IRQ and XIRQ. Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.
PAGE 965
NOTE PS[7:4] are not available in 80-pin packages. 23.0.7.8 Port M This port is associated with the CAN40 and SPI0. Port M pins PM[7:0] can be used for either general purpose I/O, or with the CAN, SCI and SPI subsystems. The CAN0, CAN4 and SPI0 pins can be re-routed. Refer to Section 23.0.5.37, “Module Routing Register (MODRR)”. NOTE PM[7:6] are not available in 80-pin packages. 23.0.7.9 Port P This port is associated with the PWM, SPI1 and SPI2.
PAGE 966
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) open-drain output pins. The CAN4 pins can be re-routed. Refer to Section 23.0.5.37, “Module Routing Register (MODRR)”. Port J pins can be used with the routed CAN0 modules. Refer to Section 23.0.5.37, “Module Routing Register (MODRR)”. Port J offers 7 I/O pins with edge triggered interrupt capability (Section 23.0.8, “Pin Interrupts”). NOTE PJ[5,4,2] are not available in 112-pin packages. PJ[5,4,2,1,0] are not available in 80-pin packages. 23.0.7.
PAGE 967
Glitch, filtered out, no interrupt flag set Valid pulse, interrupt flag set uncertain tpign tpval Figure 23-77. Interrupt Glitch Filter on Port P, H, and J (PPS = 0) Table 23-69. Pulse Detection Criteria Mode Pulse STOP Unit STOP1 Ignored tpulse ≤ 3 Bus clocks tpulse ≤ tpign Uncertain 3 < tpulse < 4 Bus clocks tpign < tpulse < tpval Valid tpulse ≥ 4 Bus clocks tpulse ≥ tpval 1. These values include the spread of the oscillator frequency over temperature, voltage and process.
PAGE 968
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) Table 23-70 lists the pin functions in relationship with the different operating modes. If two entries per pin are displayed, a ‘mux’ indicates time-multiplexing between the two functions and an ‘or’ means that a configuration bit exists which can be altered after reset to select the respective function (displayed in italics). Refer to S12X_EBI section for details. Table 23-70.
PAGE 969
Table 23-70. Expanded Bus Pin Functions versus Operating Modes (continued) Single-Chip Modes Expanded Modes Pin Normal SingleChip Special SingleChip Normal Expanded Emulation Single-Chip Emulation Expanded Special Test PJ2 GPIO GPIO GPIO or CS1 GPIO GPIO or CS1 GPIO or CS1 PJ0 GPIO GPIO GPIO or CS3 GPIO GPIO or CS3 GPIO or CS3 1. Depending on ROMON bit. Refer to Device Guide, S12X_EBI section and S12X_MMC section for details. 23.0.10 Low-Power Options 23.0.10.
PAGE 970
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 971
PAGE 972
Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 973
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Introduction The S12XD family port integration module (below referred to as PIM) establishes the interface between the peripheral modules including the non-multiplexed external bus interface module (S12X_EBI) and the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins.
PAGE 974
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) • • • • • • • • • • • Data and data direction registers for Ports A, B, E, K, T, S, M, P, H, J, and AD1 when used as general-purpose I/O Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P, H, and J on per-pin basis Control registers to enable/disable pull-up devices on Port AD1 on per-pin basis Single control register to enable/disable pull-ups on Ports A, B, E, and K on per-port basis and on BKGD pin
PAGE 975
MOSI MISO Port AD1 SS SPI1 SCK Port T PWM IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 PAD09 PAD08 PAD07 PAD06 PAD05 PAD04 PAD03 PAD02 PAD01 PAD00 PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 Port P ECT SPI0 CAN0 CAN0 CAN4 CAN4 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Interrupt Logic ATD1 TXCAN CAN4 RXCAN SCL IIC0 SDA TXCAN CAN0 RXCAN Port A PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0
PAGE 976
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) External Signal Description This section lists and describes the signals that do connect off-chip. 24.0.3 Signal Properties Table 24-1 shows all the pins and their functions that are controlled by the PIM. Refer to Section , “Functional Description” for the availability of the individual pins in the different package options.
PAGE 977
Table 24-1. Pin Functions and Priorities (Sheet 2 of 5) Port Pin Name Pin Function and Priority I/O SS0 I/O Serial Peripheral Interface 0 slave select output in master mode, input in slave mode or master mode.
PAGE 978
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-1.
PAGE 979
Table 24-1.
PAGE 980
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-1.
PAGE 981
Memory Map and Register Definition This section provides a detailed description of all PIM registers. 24.0.4 Module Memory Map Table 24-2 shows the register map of the port integration module. Table 24-2.
PAGE 982
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-2.
PAGE 983
Table 24-2.
PAGE 984
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-3.
PAGE 985
Register Name Reserved R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 0 0 W Reserved R W Reserved R W Reserved R W PORTE R W DDRE R W R Non-PIM W Address Range PUCR R W RDRIV R W Non-PIM Address Range PUPKE RDPK BKPUE 0 0 W Reserved R PUPDE1 PUPCE1 PUPBE PUPAE RDPE RDPD1 RDPC1 RDPB RDPA EDIV1 EDIV0 0 R Non-PI
PAGE 986
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Register Name Bit 7 6 5 Non-PIM R Address W Range PORTK R W DDRK R W R W PTIT R 3 2 1 Bit 0 Non-PIM Address Range PK7 DDRK7 0 0 PK5 PK4 PK3 PK2 PK1 PK0 DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0 Non-PIM R Address W Range PTT 4 Non-PIM Address Range PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 RDRT7 RDRT6 RD
PAGE 987
Register Name DDRS R W RDRS R W PERS R W PPSS R W WOMS R W Reserved R Bit 7 6 5 4 3 2 1 Bit 0 DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 0 0 0 0 0 0 0 0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM
PAGE 988
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Register Name PTIP R Bit 7 6 5 4 3 2 1 Bit 0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 PTH7
PAGE 989
Register Name PTJ R W PTIJ R Bit 7 6 5 4 3 2 1 Bit 0 PTJ7 PTJ6 0 0 0 0 PTJ1 PTJ0 PTIJ7 PTIJ6 0 0 0 0 PTIJ1 PTIJ0 DDRJ7 DDRJ6 0 0 0 0 DDRJ1 DDRJ0 RDRJ7 RDRJ6 0 0 0 0 RDRJ1 RDRJ0 PERJ7 PERJ6 0 0 0 0 PERJ1 PERJ0 PPSJ7 PPSJ6 0 0 0 0 PPSJ1 PPSJ0 PIEJ7 PIEJ6 0 0 0 0 PIEJ1 PIEJ0 PPSJ7 PPSJ6 0 0 0 0 PPSJ1 PPSJ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PAGE 990
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Register Name Reserved Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 PT1AD115 PT1AD114 PT1AD113 PT1AD112 PT1AD111 PT1AD110 PT1AD19 PT1AD18 PT1AD17 PT1AD16 PT1AD15 PT1AD14 PT1AD13 PT1AD12 PT1AD11 PT1AD10 R W PT0AD1 R W PT1AD1 R W DDR0AD1 R W DDR1AD1 R W RDR0AD1 R W RDR1AD1 R W PER0AD1 R W PER1AD1 R W DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18 DDR1AD17 DDR1AD16 DDR1AD15 DDR1AD14 DDR1
PAGE 991
Table 24-4. PORTA Field Descriptions Field Description 7–0 PA[7:0] Port A — Port A pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. 24.0.5.2 Port B Data Register (PORTB) 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 0 0 0 0 0 0 0 0 R W Reset Figure 24-4. Port B Data Register (PORTB) Read: Anytime.
PAGE 992
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) 24.0.5.4 Port B Data Direction Register (DDRB) 7 6 5 4 3 2 1 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 R W Reset Figure 24-6. Port B Data Direction Register (DDRB) Read: Anytime. Write: Anytime. Table 24-7. DDRB Field Descriptions Field Description 7–0 DDRB[7:0] Data Direction Port B — This register controls the data direction for port B. DDRB determines whether each pin is an input or output.
PAGE 993
Table 24-8. PORTE Field Descriptions Field 7–0 PE[7:0] Description Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include mode select (MODB, MODA), E clock, double frequency E clock, IRQ, and XIRQ. When not used for any of these specific functions, Port E pins 7–2 can be used as general purpose I/O and pins 1–0 can be used as general purpose inputs.
PAGE 994
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) 24.0.5.7 S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) 7 6 PUPKE BKPUE 1 1 5 R 4 3 2 1 0 PUPEE PUPDE1 PUPCE1 PUPBE PUPAE 1 0 0 0 0 0 W Reset 0 = Unimplemented or Reserved Figure 24-9. S12X_EBI Ports, BKGD, VREGEN Pin Pull-up Control Register (PUCR) 1. Register implemented, function disabled: Written values can be read back. Read: Anytime in single-chip modes.
PAGE 995
24.0.5.8 S12X_EBI Ports Reduced Drive Register (RDRIV) 7 R 6 5 0 0 RDPK 4 3 2 1 0 RDPE RDPD1 RDPC1 RDPB RDPA 0 0 0 0 0 W Reset 0 0 0 = Unimplemented or Reserved Figure 24-10. S12X_EBI Ports Reduced Drive Register (RDRIV) 1. Register implemented, function disabled: Written values can be read back. Read: Anytime. Write: Anytime. This register is used to select reduced drive for the pins associated with ports A, B, E, and K.
PAGE 996
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) 24.0.5.
PAGE 997
Table 24-13. Free-Running ECLK Clock Rate EDIV[1:0] Rate of Free-Running ECLK 00 ECLK = Bus clock rate 01 ECLK = Bus clock rate divided by 2 10 ECLK = Bus clock rate divided by 3 11 ECLK = Bus clock rate divided by 4 24.0.5.10 IRQ Control Register (IRQCR) 7 6 IRQE IRQEN 0 1 R 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 24-12. IRQ Control Register (IRQCR) Read: See individual bit descriptions below.
PAGE 998
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-15. PORTK Field Descriptions Field Description 7–0 PK[7,5:0] Port K — Port K pins 7–0 can be used as general-purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read except for bit 6 which reads “0”. 24.0.5.
PAGE 999
Table 24-17. PTT Field Descriptions Field Description 7–0 PTT[7:0] Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used with the ECT, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. 24.0.5.
PAGE 1000
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare is disabled. The timer input capture always monitors the state of the pin. Table 24-19. DDRT Field Descriptions Field Description 7–0 DDRT[7:0] Data Direction Port T 0 Associated pin is configured as input. 1 Associated pin is configured as output.
PAGE 1001
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled. Table 24-21. PERT Field Descriptions Field 7–0 PERT[7:0] Description Pull Device Enable Port T 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 24.0.5.
PAGE 1002
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be used as general purpose I/O. Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and 1 are configured as outputs if the transmitter is enabled.
PAGE 1003
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled. The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled. Table 24-23. DDRS Field Descriptions Field Description 7–0 DDRS[7:0] Data Direction Port S 0 Associated pin is configured as input.
PAGE 1004
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Write: Anytime. This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or as output in wired-OR (open drain) mode. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up device is enabled. Table 24-25. PERS Field Descriptions Field 7–0 PERS[7:0] Description Pull Device Enable Port S 0 Pull-up or pull-down device is disabled.
PAGE 1005
This register configures the output pins as wired-OR. If enabled the output is driven active low only (open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows a multipoint connection of several serial modules. These bits have no influence on pins used as inputs. Table 24-27. WOMS Field Descriptions Field Description 7–0 Wired-OR Mode Port S WOMS[7:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 24.0.5.
PAGE 1006
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-28. PTM Field Descriptions (continued) Field 3–2 PTM[3:2] Description The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. Refer to MSCAN section for details. The routed SPI0 function (SS0 and MISO0) takes precedence of the general purpose I/O function if the routed SPI0 is enabled and not in bidirectional mode.
PAGE 1007
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled. Table 24-29. DDRM Field Descriptions Field Description 7–0 DDRM[7:0] Data Direction Port M 0 Associated pin is configured as input. 1 Associated pin is configured as output. Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on PTM or PTIM registers, when changing the DDRM register. 24.0.5.
PAGE 1008
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset no pull device is enabled. Table 24-31. PERM Field Descriptions Field 7–0 PERM[7:0] Description Pull Device Enable Port M 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 24.0.5.
PAGE 1009
This register configures the output pins as wired-OR. If enabled the output is driven active low only (open-drain). A logic level of “1” is not driven. It applies also to the CAN outputs and allows a multipoint connection of several serial modules. This bit has no influence on pins used as inputs. Table 24-33. WOMM Field Descriptions Field Description 7–0 Wired-OR Mode Port M WOMM[7:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 24.0.5.
PAGE 1010
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) 24.0.5.34 Port P Data Register (PTP) 7 6 5 4 3 2 1 0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 SS1 SCK1 MOSI1 MISO1 0 0 0 0 R W PWM SPI Reset 0 0 0 0 Figure 24-36. Port P Data Register (PTP) Read: Anytime. Write: Anytime. Port P pins 7–0 are associated with the PWM as well as the SPI1. These pins can be used as general purpose I/O when not used with any of the peripherals.
PAGE 1011
24.0.5.36 Port P Data Direction Register (DDRP) 7 6 5 4 3 2 1 0 DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 0 0 0 0 0 0 0 0 R W Reset Figure 24-38. Port P Data Direction Register (DDRP) Read: Anytime. Write: Anytime. This register configures each port P pin as either input or output. If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-36. RDRP Field Descriptions Field 7–0 RDRP[7:0] Description Reduced Drive Port P 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 24.0.5.38 Port P Pull Device Enable Register (PERP) 7 6 5 4 3 2 1 0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 0 0 0 0 0 0 0 0 R W Reset Figure 24-40. Port P Pull Device Enable Register (PERP) Read: Anytime. Write: Anytime.
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Table 24-38. PPSP Field Descriptions Field Description 7–0 PPSP[7:0] Polarity Select Port P 0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-40. PIFP Field Descriptions Field 7–0 PIFP[7:0] Description Interrupt Flags Port P 0 No active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a logic level “1” clears the associated flag. 24.0.5.
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This register always reads back the buffered state of the associated pins. This can also be used to detect overload or short circuit conditions on output pins. 24.0.5.44 Port H Data Direction Register (DDRH) 7 6 5 4 3 2 1 0 DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 0 0 0 0 0 0 0 0 R W Reset Figure 24-46. Port H Data Direction Register (DDRH) Read: Anytime. Write: Anytime. This register configures each port H pin as either input or output.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-42. RDRH Field Descriptions Field 7–0 RDRH[7:0] Description Reduced Drive Port H 0 Full drive strength at output. 1 Associated pin drives at about 1/6 of the full drive strength. 24.0.5.46 Port H Pull Device Enable Register (PERH) 7 6 5 4 3 2 1 0 PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 0 0 0 0 0 0 0 0 R W Reset Figure 24-48. Port H Pull Device Enable Register (PERH) Read: Anytime. Write: Anytime.
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Table 24-44. PPSH Field Descriptions Field Description 7–0 PPSH[7:0] Polarity Select Port H 0 Falling edge on the associated port H pin sets the associated flag bit in the PIFH register. A pull-up device is connected to the associated port H pin, if enabled by the associated bit in register PERH and if the port is used as input. 1 Rising edge on the associated port H pin sets the associated flag bit in the PIFH register.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-46. PIFH Field Descriptions Field 7–0 PIFH[7:0] Description Interrupt Flags Port H 0 No active edge pending. Writing a “0” has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a logic level “1” clears the associated flag. 24.0.5.
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24.0.5.51 Port J Input Register (PTIJ) R 7 6 5 4 3 2 1 0 PTIJ7 PTIJ6 0 0 0 0 PTIJ1 PTIJ0 0 0 0 0 0 0 0 0 W Reset1 = Unimplemented or Reserved Figure 24-53. Port J Input Register (PTIJ) 1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated pin values. Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the buffered state of the associated pins.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) 24.0.5.53 Port J Reduced Drive Register (RDRJ) 7 6 RDRJ7 RDRJ6 0 0 R 5 4 3 2 0 0 0 0 1 0 RDRJ1 RDRJ0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 24-55. Port J Reduced Drive Register (RDRJ) Read: Anytime. Write: Anytime. This register configures the drive strength of each port J output pin as either full or reduced. If the port is used as input this bit is ignored. Table 24-49.
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Table 24-50. PERJ Field Descriptions Field 7–0 PERJ[7:6] PERJ[1:0] Description Pull Device Enable Port J 0 Pull-up or pull-down device is disabled. 1 Either a pull-up or pull-down device is enabled. 24.0.5.55 Port J Polarity Select Register (PPSJ) 7 6 PPSJ7 PPSJ6 0 0 R 5 4 3 2 0 0 0 0 1 0 PPSJ1 PPSJ0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 24-57. Port J Polarity Select Register (PPSJ) Read: Anytime. Write: Anytime.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Table 24-52. PIEJ Field Descriptions Field 7–0 PIEJ[7:6] PIEJ[1:0] Description Interrupt Enable Port J 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. 24.0.5.57 Port J Interrupt Flag Register (PIFJ) 7 6 PIFJ7 PIFJ6 0 0 R 5 4 3 2 0 0 0 0 1 0 PIFJ1 PIFJ0 0 0 W Reset 0 0 0 0 = Unimplemented or Reserved Figure 24-59. Port J Interrupt Flag Register (PIFJ) Read: Anytime. Write: Anytime.
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If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register, otherwise the value at the pins is read. 24.0.5.59 Port AD1 Data Register 1 (PT1AD1) 7 6 5 4 3 2 1 0 PT1AD17 PT1AD16 PT1AD15 PT1AD14 PT1AD13 PT1AD12 PT1AD11 PT1AD10 0 0 0 0 0 0 0 0 R W Reset Figure 24-61. Port AD1 Data Register 1 (PT1AD1) Read: Anytime. Write: Anytime. This register is associated with AD1 pins PAD[7:0].
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) 24.0.5.61 Port AD1 Data Direction Register 1 (DDR1AD1) 7 6 5 4 3 2 1 0 DDR1AD17 DDR1AD16 DDR1AD15 DDR1AD14 DDR1AD13 DDR1AD12 DDR1AD11 DDR1AD10 0 0 0 0 0 0 0 0 R W Reset Figure 24-63. Port AD1 Data Direction Register 1 (DDR1AD1) Read: Anytime. Write: Anytime. This register configures pins PAD[7:0] as either input or output. Table 24-55.
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24.0.5.63 Port AD1 Reduced Drive Register 1 (RDR1AD1) 7 6 5 4 3 2 1 0 RDR1AD17 RDR1AD16 RDR1AD15 RDR1AD14 RDR1AD13 RDR1AD12 RDR1AD11 RDR1AD10 0 0 0 0 0 0 0 0 R W Reset Figure 24-65. Port AD1 Reduced Drive Register 1 (RDR1AD1) Read: Anytime. Write: Anytime. This register configures the drive strength of each PAD[7:0] output pin as either full or reduced. If the port is used as input this bit is ignored. Table 24-57.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) 24.0.5.65 Port AD1 Pull Up Enable Register 1 (PER1AD1) 7 6 5 4 3 2 1 0 PER1AD17 PER1AD16 PER1AD15 PER1AD14 PER1AD13 PER1AD12 PER1AD11 PER1AD10 0 0 0 0 0 0 0 0 R W Reset Figure 24-67. Port AD1 Pull Up Enable Register 1 (PER1AD1) Read: Anytime. Write: Anytime. This register activates a pull-up device on the respective PAD[7:0] pin if the port is used as input. This bit has no effect if the port is used as output.
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Table 24-60. Register Availability per Port1 Port Data Data Direction Input Reduced Drive Pull Enable Polarity Select Wired-OR Mode Interrupt Enable Interrupt Flag J yes yes yes yes yes yes — yes yes AD1 yes yes — yes yes — — — — 1. Each cell represents one register with individual configuration bits 24.0.6 24.0.6.1 Registers Data Register This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) 24.0.6.4 Reduced Drive Register If the pin is used as an output this register allows the configuration of the drive strength. 24.0.6.5 Pull Device Enable Register This register turns on a pull-up or pull-down device. It becomes active only if the pin is used as an input or as a wired-OR output. 24.0.6.6 Polarity Select Register This register selects either a pull-up or pull-down device if enabled.
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Table 24-61. Module Implementations on Derivatives MSCAN Modules SPI Modules Number of Modules CAN0 CAN1 CAN2 CAN3 CAN4 SPI0 SPI1 SPI2 5 yes yes yes yes yes — — — 4 yes yes yes — yes — — — 3 yes yes — — yes yes yes yes 2 yes — — — yes yes yes — 1 yes — — — — yes — — 24.0.7 24.0.7.1 Ports BKGD Pin The BKGD pin is associated with the S12X_BDM and S12X_EBI modules. During reset, the BKGD pin is used as MODC input. 24.0.7.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section). NOTE Port K is not available in 80-pin packages. 24.0.7.5 Port T This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the enhanced capture timer. 24.0.7.6 Port S This port is associated with SCI0, SCI1 and SPI0.
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24.0.7.9 Port H This port is associated with the SPI1, . Port H pins PH[7:0] can be used for either general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1. Refer to Section 24.0.5.33, “Module Routing Register (MODRR)”. Port H offers 8 I/O pins with edge triggered interrupt capability (Section 24.0.8, “Pin Interrupts”). NOTE Port H is not available in 80-pin packages. 24.0.7.10 Port J This port is associated with CAN4, CAN0, IIC0.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) Glitch, filtered out, no interrupt flag set Valid pulse, interrupt flag set uncertain tpign tpval Figure 24-69. Interrupt Glitch Filter on Port P, H, and J (PPS = 0) Table 24-62. Pulse Detection Criteria Mode Pulse STOP Unit STOP1 Ignored tpulse ≤ 3 Bus clocks tpulse ≤ tpign Uncertain 3 < tpulse < 4 Bus clocks tpign < tpulse < tpval Valid tpulse ≥ 4 Bus clocks tpulse ≥ tpval 1.
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24.0.9.2 Wait Mode No low-power options exist for this module in wait mode. 24.0.9.3 Stop Mode All clocks are stopped. There are asynchronous paths to generate interrupts from stop on port P, H, and J. Initialization and Application Information • It is not recommended to write PORTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs.
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Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1035
PAGE 1036
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.1 Introduction This document describes the EETX2K module which includes a 2Kbyte EEPROM (nonvolatile) memory. The EEPROM memory may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.1.4 Block Diagram A block diagram of the EEPROM module is shown in Figure 25-1. EETX2K EEPROM Interface Command Interrupt Request Command Pipeline EEPROM cmd2 addr2 data2 cmd1 addr1 data1 Registers 1K * 16 Bits sector 0 sector 1 Protection sector 511 Oscillator Clock Clock Divider EECLK Figure 25-1. EETX2K Block Diagram 25.2 External Signal Description The EEPROM module contains no signals that connect off-chip. 25.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) region are shown in the EEPROM memory map. The default protection setting is stored in the EEPROM configuration field as described in Table 25-1. Table 25-1. EEPROM Configuration Field Global Address Size (bytes) Description 0x13_FFFC 1 Reserved 0x13_FFFD 1 EEPROM Protection byte Refer to Section 25.3.2.5, “EEPROM Protection Register (EPROT)” 0x13_FFFE – 0x13_FFFF 2 Reserved MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) MODULE BASE + 0x0000 MODULE BASE + 0x000B EEPROM Registers 12 bytes EEPROM START = 0x13_F800 EEPROM Memory 1536 bytes (up to 1984 bytes) 0x13_FE00 0x13_FE40 0x13_FE80 0x13_FEC0 0x13_FF00 EEPROM Memory Protected Region 64, 128, 192, 256, 320, 384, 448, or 512 bytes 0x13_FF40 0x13_FF80 0x13_FFC0 EEPROM END = 0x13_FFFF EEPROM Configuration Field 4 bytes (0x13_FFFC - 0x13_FFFF) Figure 25-2. EEPROM Memory Map MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.3.2 Register Descriptions The EEPROM module also contains a set of 12 control and status registers located between EEPROM module base + 0x0000 and 0x000B. A summary of the EEPROM module registers is given in Figure 25-3. Detailed descriptions of each register bit are provided.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.3.2.1 EEPROM Clock Divider Register (ECLKDIV) The ECLKDIV register is used to control timed events in program and erase algorithms. 7 R 6 5 4 3 2 1 0 PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 EDIVLD W Reset 0 = Unimplemented or Reserved Figure 25-4. EEPROM Clock Divider Register (ECLKDIV) All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. Table 25-2.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-6. RESERVED2 All bits read 0 and are not writable. 25.3.2.4 EEPROM Configuration Register (ECNFG) The ECNFG register enables the EEPROM interrupts. 7 6 CBEIE CCIE 0 0 R 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 25-7.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.3.2.5 EEPROM Protection Register (EPROT) The EPROT register defines which EEPROM sectors are protected against program or erase operations. 7 R 6 5 4 RNV6 RNV5 RNV4 EPOPEN 3 2 1 0 EPDIS EPS2 EPS1 EPS0 F F F F W Reset F F F F = Unimplemented or Reserved Figure 25-8.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) Table 25-5. EEPROM Protection Address Range 25.3.2.6 EPS[2:0] Address Offset Range Protected Size 000 0x0FC0 – 0x0FFF 64 bytes 001 0x0F80 – 0x0FFF 128 bytes 010 0x0F40 – 0x0FFF 192 bytes 011 0x0F00 – 0x0FFF 256 bytes 100 0x0EC0 – 0x0FFF 320 bytes 101 0x0E80 – 0x0FFF 384 bytes 110 0x0E40 – 0x0FFF 448 bytes 111 0x0E00 – 0x0FFF 512 bytes EEPROM Status Register (ESTAT) The ESTAT register defines the operational status of the module.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) Table 25-6. ESTAT Field Descriptions Field Description 7 CBEIF Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data, and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.3.2.7 EEPROM Command Register (ECMD) The ECMD register is the EEPROM command register. 7 R 6 5 4 3 2 1 0 0 0 0 0 CMDB W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 25-11. EEPROM Command Register (ECMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 25-7.
PAGE 1048
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) The EADDRHI and EADDRLO registers are the EEPROM address registers. R 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 EABHI W Reset 0 0 = Unimplemented or Reserved Figure 25-13. EEPROM Address High Register (EADDRHI) 7 6 5 4 R 3 2 1 0 0 0 0 0 EABLO W Reset 0 0 0 0 = Unimplemented or Reserved Figure 25-14. EEPROM Address Low Register (EADDRLO) All EABHI and EABLO bits read 0 and are not writable in normal modes.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) All EDHI and EDLO bits are readable and writable in special modes. 25.4 Functional Description 25.4.1 EEPROM Command Operations Write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify algorithms described in this section. The program, erase, and sector modify algorithms are controlled by a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider.
PAGE 1050
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the optimum target by: ( 200 – 182 ) ⁄ 200 × 100 = 9% CAUTION Program and erase command execution time will increase proportionally with the period of EECLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the EEPROM memory cannot be performed if the bus clock runs at less than 1 MHz.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8 = 0 (reset) oscillator_clock >12.8 MHz? no yes PRDIV8 = 1 PRDCLK = oscillator_clock/8 PRDCLK = oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no EDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])–1 TRY TO DECREASE Tbus EECLK = (PRDCLK)/(1+EDIV[5:0]) 1/EECLK[MHz] + Tbus[ms] > 5 AND EECLK > 0.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.1.2 Command Write Sequence The EEPROM command controller is used to supervise the command write sequence to execute program, erase, erase verify, sector erase abort, and sector modify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the ESTAT register must be clear (see Section 25.3.2.
PAGE 1053
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) Table 25-9. EEPROM Command Description ECMDB Command Function on EEPROM Memory 0x41 Mass Erase Erase all memory bytes in the EEPROM block. A mass erase of the full EEPROM block is only possible when EPOPEN and EPDIS bits in the EPROT register are set prior to launching the command. 0x47 Sector Erase Abort Abort the sector erase operation. The sector erase operation will terminate according to a set procedure.
PAGE 1054
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.1 Erase Verify Command The erase verify operation will verify that the EEPROM memory is erased. An example flow to execute the erase verify operation is shown in Figure 25-18. The erase verify command write sequence is as follows: 1. Write to an EEPROM address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the ECMD register. 3.
PAGE 1055
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Address and Dummy Data 2. Write: ECMD register Erase Verify Command 0x05 3.
PAGE 1056
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.2 Program Command The program operation will program a previously erased word in the EEPROM memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 25-19. The program command write sequence is as follows: 1. Write to an EEPROM block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2.
PAGE 1057
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check 1. Write: EEPROM Address and program Data 2. Write: ECMD register Program Command 0x20 3.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.3 Sector Erase Command The sector erase operation will erase both words in a sector of EEPROM memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 25-20. The sector erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector erase command.
PAGE 1059
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Sector Address and Dummy Data 2. Write: ECMD register Sector Erase Command 0x40 3.
PAGE 1060
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.4 Mass Erase Command The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 25-21. The mass erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2.
PAGE 1061
Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Address and Dummy Data 2. Write: ECMD register Mass Erase Command 0x41 3.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.5 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase or sector modify operation so that other sectors in an EEPROM block are available for read and program operations without waiting for the sector erase or sector modify operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 25-22. The sector erase abort command write sequence is as follows: 1.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) Execute Sector Erase/Modify Command Flow Read: ESTAT register Bit Polling for Command Completion Check CCIF Set? Erase Abort Needed? no yes Sector Erase Completed no yes EXIT 1. Write: Dummy EEPROM Address and Dummy Data NOTE: command write sequence aborted by writing 0x00 to ESTAT register. 2. Write: ECMD register Sector Erase Abort Cmd 0x47 NOTE: command write sequence aborted by writing 0x00 to ESTAT register. 3.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.2.6 Sector Modify Command The sector modify operation will erase both words in a sector of EEPROM memory followed by a reprogram of the addressed word using an embedded algorithm. An example flow to execute the sector modify operation is shown in Figure 25-23. The sector modify command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector modify command.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Word Address and program Data 2. Write: ECMD register Sector Modify Command 0x60 3.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.4.3 Illegal EEPROM Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to an EEPROM address before initializing the ECLKDIV register. 2. Writing a byte or misaligned word to a valid EEPROM address. 3. Starting a command write sequence while a sector erase abort operation is active. 4.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.5 25.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters the wait mode, the active command and any buffered command will be completed. The EEPROM module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 25.8, “Interrupts”). 25.5.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased using the following method : • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a mass erase command write sequence to erase the EEPROM memory.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) 25.8.1 Description of EEPROM Interrupt Operation The logic used for generating interrupts is shown in Figure 25-24. The EEPROM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the EEPROM command interrupt request. CBEIF CBEIE EEPROM Command Interrupt Request CCIF CCIE Figure 25-24. EEPROM Interrupt Implementation For a detailed description of the register bits, refer to Section 25.3.2.
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Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.1 Introduction This document describes the EETX4K module which includes a 4 Kbyte EEPROM (nonvolatile) memory. The EEPROM memory may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.1.4 Block Diagram A block diagram of the EEPROM module is shown in Figure 26-1. EETX4K Command Interrupt Request EEPROM Interface Command Pipeline EEPROM cmd2 addr2 data2 cmd1 addr1 data1 Registers 2K * 16 Bits sector 0 sector 1 Protection sector 1023 Oscillator Clock Clock Divider EECLK Figure 26-1. EETX4K Block Diagram 26.2 External Signal Description The EEPROM module contains no signals that connect off-chip. 26.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) region are shown in the EEPROM memory map. The default protection setting is stored in the EEPROM configuration field as described in Table 26-1. Table 26-1. EEPROM Configuration Field Global Address Size (bytes) Description 0x13_FFFC 1 Reserved 0x13_FFFD 1 EEPROM Protection byte Refer to Section 26.3.2.5, “EEPROM Protection Register (EPROT)” 0x13_FFFE – 0x13_FFFF 2 Reserved MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) MODULE BASE+ 0x0000 EEPROM Registers 12 bytes MODULE BASE + 0x000B EEPROM START = 0x13_F000 EEPROM Memory 3584 bytes (up to 4032 bytes) 0x13_FE00 0x13_FE40 0x13_FE80 0x13_FEC0 0x13_FF00 EEPROM Memory Protected Region 64, 128, 192, 256, 320, 384, 448, 512 bytes 0x13_FF40 0x13_FF80 0x13_FFC0 EEPROM END = 0x13_FFFF EEPROM Configuration Field 4 bytes (0x13_FFFC – 0x13_FFFF) Figure 26-2. EEPROM Memory Map MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) The EEPROM module also contains a set of 12 control and status registers located between EEPROM module base + 0x0000 and 0x000B. A summary of the EEPROM module registers is given in Table 26-2 while their accessibility is detailed in Section 26.3.2, “Register Descriptions”. Table 26-2.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.3.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 7 R 6 5 4 3 2 1 0 PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 EDIVLD W Reset 0 = Unimplemented or Reserved Figure 26-4. EEPROM Clock Divider Register (ECLKDIV) All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable. Table 26-3. ECLKDIV Field Descriptions Field Description 7 EDIVLD Clock Divider Loaded 0 Register has not been written.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-6. RESERVED2 All bits read 0 and are not writable. 26.3.2.4 EEPROM Configuration Register (ECNFG) The ECNFG register enables the EEPROM interrupts. 7 6 CBEIE CCIE 0 0 R 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 26-7.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.3.2.5 EEPROM Protection Register (EPROT) The EPROT register defines which EEPROM sectors are protected against program or erase operations. 7 R 6 5 4 RNV6 RNV5 RNV4 EPOPEN 3 2 1 0 EPDIS EPS2 EPS1 EPS0 F F F F W Reset F F F F = Unimplemented or Reserved Figure 26-8.
PAGE 1080
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) Table 26-6. EEPROM Protection Address Range 26.3.2.6 EPS[2:0] Address Offset Range Protected Size 000 0x0FC0 – 0x0FFF 64 bytes 001 0x0F80 – 0x0FFF 128 bytes 010 0x0F40 – 0x0FFF 192 bytes 011 0x0F00 – 0x0FFF 256 bytes 100 0x0EC0 – 0x0FFF 320 bytes 101 0x0E80 – 0x0FFF 384 bytes 110 0x0E40 – 0x0FFF 448 bytes 111 0x0E00 – 0x0FFF 512 bytes EEPROM Status Register (ESTAT) The ESTAT register defines the operational status of the module.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) Table 26-7. ESTAT Field Descriptions Field Description 7 CBEIF Command Buffer Empty Interrupt Flag — The CBEIF flag indicates that the address, data, and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF.
PAGE 1082
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.3.2.7 EEPROM Command Register (ECMD) The ECMD register is the EEPROM command register. 7 R 6 5 4 3 2 1 0 0 0 0 0 CMDB W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 26-11. EEPROM Command Register (ECMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 26-8.
PAGE 1083
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) The EADDRHI and EADDRLO registers are the EEPROM address registers. R 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 2 1 0 EABHI W Reset 0 0 0 = Unimplemented or Reserved Figure 26-13. EEPROM Address High Register (EADDRHI) 7 6 5 4 R 3 2 1 0 0 0 0 0 EABLO W Reset 0 0 0 0 = Unimplemented or Reserved Figure 26-14. EEPROM Address Low Register (EADDRLO) All EABHI and EABLO bits read 0 and are not writable in normal modes.
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Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) All EDHI and EDLO bits are readable and writable in special modes. 26.4 Functional Description 26.4.1 EEPROM Command Operations Write operations are used to execute program, erase, erase verify, sector erase abort, and sector modify algorithms described in this section. The program, erase, and sector modify algorithms are controlled by a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider.
PAGE 1085
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) then 182 kHz. In this case, the EEPROM program and erase algorithm timings are increased over the optimum target by: ( 200 – 182 ) ⁄ 200 × 100 = 9% CAUTION Program and erase command execution time will increase proportionally with the period of EECLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the EEPROM memory cannot be performed if the bus clock runs at less than 1 MHz.
PAGE 1086
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8 = 0 (reset) oscillator_clock >12.8 MHz? no yes PRDIV8 = 1 PRDCLK = oscillator_clock/8 PRDCLK = oscillator_clock PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes no EDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) EDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])–1 TRY TO DECREASE Tbus EECLK = (PRDCLK)/(1+EDIV[5:0]) 1/EECLK[MHz] + Tbus[ms] > 5 AND EECLK > 0.
PAGE 1087
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.1.2 Command Write Sequence The EEPROM command controller is used to supervise the command write sequence to execute program, erase, erase verify, sector erase abort, and sector modify algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the ESTAT register must be clear (see Section 26.3.2.
PAGE 1088
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) Table 26-10. EEPROM Command Description ECMDB Command Function on EEPROM Memory 0x41 Mass Erase Erase all memory bytes in the EEPROM block. A mass erase of the full EEPROM block is only possible when EPOPEN and EPDIS bits in the EPROT register are set prior to launching the command. 0x47 Sector Erase Abort Abort the sector erase operation. The sector erase operation will terminate according to a set procedure.
PAGE 1089
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.1 Erase Verify Command The erase verify operation will verify that the EEPROM memory is erased. An example flow to execute the erase verify operation is shown in Figure 26-18. The erase verify command write sequence is as follows: 1. Write to an EEPROM address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the ECMD register. 3.
PAGE 1090
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Address and Dummy Data 2. Write: ECMD register Erase Verify Command 0x05 3.
PAGE 1091
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.2 Program Command The program operation will program a previously erased word in the EEPROM memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 26-19. The program command write sequence is as follows: 1. Write to an EEPROM block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2.
PAGE 1092
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check 1. Write: EEPROM Address and program Data 2. Write: ECMD register Program Command 0x20 3.
PAGE 1093
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.3 Sector Erase Command The sector erase operation will erase both words in a sector of EEPROM memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 26-20. The sector erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector erase command.
PAGE 1094
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Sector Address and Dummy Data 2. Write: ECMD register Sector Erase Command 0x40 3.
PAGE 1095
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.4 Mass Erase Command The mass erase operation will erase all addresses in an EEPROM block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 26-21. The mass erase command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2.
PAGE 1096
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Address and Dummy Data 2. Write: ECMD register Mass Erase Command 0x41 3.
PAGE 1097
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.5 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase or sector modify operation so that other sectors in an EEPROM block are available for read and program operations without waiting for the sector erase or sector modify operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 26-22. The sector erase abort command write sequence is as follows: 1.
PAGE 1098
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) Execute Sector Erase/Modify Command Flow Read: ESTAT register Bit Polling for Command Completion Check CCIF Set? Erase Abort Needed? no yes Sector Erase Completed no yes EXIT 1. Write: Dummy EEPROM Address and Dummy Data NOTE: command write sequence aborted by writing 0x00 to ESTAT register. 2. Write: ECMD register Sector Erase Abort Cmd 0x47 NOTE: command write sequence aborted by writing 0x00 to ESTAT register. 3.
PAGE 1099
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.2.6 Sector Modify Command The sector modify operation will erase both words in a sector of EEPROM memory followed by a reprogram of the addressed word using an embedded algorithm. An example flow to execute the sector modify operation is shown in Figure 26-23. The sector modify command write sequence is as follows: 1. Write to an EEPROM memory address to start the command write sequence for the sector modify command.
PAGE 1100
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) START Read: ECLKDIV register Clock Register Written Check EDIVLD Set? yes NOTE: ECLKDIV needs to be set once after each reset. no Write: ECLKDIV register Read: ESTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check ACCERR/ PVIOL Set? no yes 1. Write: EEPROM Word Address and program Data 2. Write: ECMD register Sector Modify Command 0x60 3.
PAGE 1101
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.4.3 Illegal EEPROM Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to an EEPROM address before initializing the ECLKDIV register. 2. Writing a byte or misaligned word to a valid EEPROM address. 3. Starting a command write sequence while a sector erase abort operation is active. 4.
PAGE 1102
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.5 26.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters the wait mode, the active command and any buffered command will be completed. The EEPROM module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 26.8, “Interrupts”). 26.5.
PAGE 1103
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased using the following method : • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a mass erase command write sequence to erase the EEPROM memory.
PAGE 1104
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2) 26.8.1 Description of EEPROM Interrupt Operation The logic used for generating interrupts is shown in Figure 26-24. The EEPROM module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the EEPROM command interrupt request. CBEIF CBEIE EEPROM Command Interrupt Request CCIF CCIE Figure 26-24. EEPROM Interrupt Implementation For a detailed description of the register bits, refer to Section 26.3.2.
PAGE 1105
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.1 Introduction This document describes the FTX512K4 module that includes a 512K Kbyte Flash (nonvolatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) • • Security feature to prevent unauthorized access to the Flash memory Code integrity check using built-in data compression 27.1.3 Modes of Operation Program, erase, erase verify, and data compress operations (please refer to Section 27.4.1, “Flash Command Operations” for details). 27.1.4 Block Diagram A block diagram of the Flash module is shown in Figure 27-1. MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) FTX512K4 Flash Block 0 64K * 16 Bits sector 0 sector 1 Flash Interface Command Interrupt Request sector 127 Command Pipeline cmd2 addr2 data2_0 data2_1 data2_2 data2_3 cmd1 addr1 data1_0 data1_1 data1_2 data1_3 Flash Block 1 64K * 16 Bits sector 0 sector 1 Registers Protection sector 127 Flash Block 2 64K * 16 Bits sector 0 sector 1 Security sector 127 Oscillator Clock Clock Divider FCLK Flash Block 3 64K * 16 Bits sector 0 sector 1 sector 127
PAGE 1108
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.3 Memory Map and Register Definition This section describes the memory map and registers for the Flash module. 27.3.1 Module Memory Map The Flash memory map is shown in Figure 27-2. The HCS12X architecture places the Flash memory addresses between global addresses 0x78_0000 and 0x7F_FFFF. The FPROT register, described in Section 27.3.2.
PAGE 1109
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) MODULE BASE + 0x0000 Flash Registers 16 bytes MODULE BASE + 0x000F FLASH START = 0x78_0000 Flash Protected/Unprotected Region 480 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 FLASH END = 0x7F_FFFF Flash Configuration F
PAGE 1110
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) The Flash module also contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Table 27-2 while their accessibility is detailed in Section 27.3.2, “Register Descriptions”. Table 27-2.
PAGE 1111
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.3.
PAGE 1112
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Register Name RESERVED2 R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESERVED3 R W RESERVED4 R W Figure 27-3. FTX512K4 Register Summary (continued) 27.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 7 R 6 KEYEN 5 4 3 2 RNV5 RNV4 RNV3 RNV2 F F F F 1 0 SEC W Reset F F F F = Unimplemented or Reserved Figure 27-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but are not writable. The FSEC register is loaded from the Flash Configuration Field at address 0x7F_FF0F during the reset sequence, indicated by F in Figure 27-5. Table 27-4.
PAGE 1114
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 7 R 6 5 0 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 MRDS W Reset 0 0 0 = Unimplemented or Reserved Figure 27-6. Flash Test Mode Register (FTSTMOD —Normal Mode) 7 R 6 5 4 0 MRDS 3 2 1 0 0 0 0 0 0 0 0 0 WRALL W Reset 0 0 0 0 = Unimplemented or Reserved Figure 27-7. Flash Test Mode Register (FTSTMOD — Special Mode) MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
PAGE 1115
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 7 6 5 CBEIE CCIE KEYACC 0 0 0 R 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 1 0 W Reset = Unimplemented or Reserved Figure 27-8. Flash Configuration Register (FCNFG — Normal Mode) 7 6 5 R CBEIE CCIE KEYACC 0 0 0 4 3 2 Undefined 0 0 BKSEL W Reset Undefined 0 0 0 0 = Unimplemented or Reserved Figure 27-9.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Table 27-10. Flash Register Bank Selects 27.3.2.5 BKSEL[1:0] Selected Block 10 Flash Block 2 11 Flash Block 3 Flash Protection Register (FPROT) The FPROT register defines which Flash sectors are protected against program or erase operations. 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS FPLDIS FPLS W Reset F F F F F F F F = Unimplemented or Reserved Figure 27-10.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Table 27-11. FPROT Field Descriptions (continued) Field Description 2 FPLDIS Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a protected/unprotected area in a specific region of the Flash memory beginning with global address 0x7F_8000. 0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) FPHDIS=1 FPLDIS=1 FPHDIS=1 FPLDIS=0 FPHDIS=0 FPLDIS=1 FPHDIS=0 FPLDIS=0 7 6 5 4 0x78_0000 Scenario 0x7F_8000 FPLS[1:0] FPOPEN=1 FPHS[1:0] 0x7F_FFFF 3 2 Scenario 1 0 0x78_0000 0x7F_8000 FPLS[1:0] FPOPEN=0 FPHS[1:0] 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 27-11.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.3.2.5.1 Flash Protection Restrictions The general guideline is that Flash protection can only be added and not removed. Table 27-15 specifies all valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario.
PAGE 1120
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear in special mode when starting a command write sequence. Table 27-16.
PAGE 1121
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. 7 R 6 5 4 3 2 1 0 0 0 0 0 CMDB W Reset 1 1 0 0 0 = Unimplemented or Reserved Figure 27-14. Flash Command Register (FCMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 27-17.
PAGE 1122
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) The FCTL register is loaded from the Flash Configuration Field byte at global address 0x7F_FF0E during the reset sequence, indicated by F in Figure 27-15. Table 27-19. FCTL Field Descriptions Field Description 7-0 NV[7:0] Non volatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits. 27.3.2.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 7 6 5 4 R 3 2 1 0 0 0 0 0 FDATALO W Reset 0 0 0 0 = Unimplemented or Reserved Figure 27-19. Flash Data Low Register (FDATALO) All FDATAHI and FDATALO bits are readable but are not writable. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression signature is readable in the FDATA registers until a new command write sequence is started. 27.3.2.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-22. RESERVED3 All bits read 0 and are not writable. 27.3.2.14 RESERVED4 This register is reserved for factory testing and is not accessible. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 27-23. RESERVED4 All bits read 0 and are not writable. 27.4 27.4.
PAGE 1125
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account.
PAGE 1126
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.
PAGE 1127
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 27.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers.
PAGE 1128
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Table 27-20. Flash Command Description NVM Command Function on Flash Memory 0x06 Data Compress Compress data from a selected portion of the Flash block. The resulting signature is stored in the FDATA register. 0x20 Program 0x40 Sector Erase Erase all memory bytes in a sector of the Flash block. 0x41 Mass Erase Erase all memory bytes in the Flash block.
PAGE 1129
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.1 Erase Verify Command The erase verify operation will verify that a Flash block is erased. An example flow to execute the erase verify operation is shown in Figure 27-25. The erase verify command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored.
PAGE 1130
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check 1.
PAGE 1131
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.2 Data Compress Command The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flow to execute the data compress operation is shown in Figure 27-26. The data compress command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the data compress command.
PAGE 1132
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Address to start compression and number of word addresses to compress 1.
PAGE 1133
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.2.1 Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for simultaneous compression, then the signature from each Flash block is further compressed to generate a single 16-bit signature.
PAGE 1134
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.3 Program Command The program operation will program a previously erased word in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 27-28. The program command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the program command. The data written will be programmed to the address written.
PAGE 1135
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Address and program Data 1.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 27-29. The sector erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the sector erase command.
PAGE 1137
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check 1.
PAGE 1138
Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.5 Mass Erase Command The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 27-30. The mass erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the mass erase command. The address and data written will be ignored.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check 1.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.2.6 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase operation so that other sectors in a Flash block are available for read and program operations without waiting for the sector erase operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 27-31. The sector erase abort command write sequence is as follows: 1.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Execute Sector Erase Command Flow Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? Erase Abort Needed? no yes Sector Erase Completed no yes EXIT 1. Write: Dummy Flash Address and Dummy Data 2. Write: FCMD register Sector Erase Abort Cmd 0x47 3.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.4.3 Illegal Flash Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing a byte or misaligned word to a valid Flash address. 3. Starting a command write sequence while a data compress operation is active. 4.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 27.3.2.6, “Flash Status Register (FSTAT)”). 27.5 27.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 27.6.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 27.3.2.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access sequence in background debug mode (BDM). 27.6.
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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) Table 27-21. Flash Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global (CCR) Mask Flash Address, Data and Command Buffers empty CBEIF (FSTAT register) CBEIE (FCNFG register) I Bit All Flash commands completed CCIF (FSTAT register) CCIE (FCNFG register) I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 27.8.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.1 Introduction This document describes the FTX256K2 module that includes a 256 Kbyte Flash (nonvolatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) • • Security feature to prevent unauthorized access to the Flash memory Code integrity check using built-in data compression 28.1.3 Modes of Operation Program, erase, erase verify, and data compress operations (please refer to Section 28.4.1, “Flash Command Operations” for details). 28.1.4 Block Diagram A block diagram of the Flash module is shown in Figure 28-1.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.3 Memory Map and Register Definition This section describes the memory map and registers for the Flash module. 28.3.1 Module Memory Map The Flash memory map is shown in Figure 28-2. The HCS12X architecture places the Flash memory addresses between global addresses 0x78_0000 and 0x7F_FFFF. The FPROT register, described in Section 28.3.2.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) MODULE BASE + 0x0000 MODULE BASE + 0x000F Flash Registers 16 bytes FLASH START = 0x78_0000 Flash Protected/Unprotected Region 128 Kbytes 0x79_FFFF Unimplemented Flash Region 256 Kbytes 0x7E_0000 Flash Protected/Unprotected Region 96 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/U
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 28-3. Detailed descriptions of each register bit are provided.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Register Name RESERVED1 R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESERVED2 R W RESERVED3 R W RESERVED4 R W Figure 28-3. FTX256K2 Register Summary (continued) 28.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 R 6 KEYEN 5 4 3 2 RNV5 RNV4 RNV3 RNV2 F F F F 1 0 SEC W Reset F F F F = Unimplemented or Reserved Figure 28-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but are not writable. The FSEC register is loaded from the Flash Configuration Field at address 0x7F_FF0F during the reset sequence, indicated by F in Figure 28-5. Table 28-3.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 R 6 5 0 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 MRDS W Reset 0 0 0 = Unimplemented or Reserved Figure 28-6. Flash Test Mode Register (FTSTMOD —Normal Mode) 7 R 6 5 4 0 MRDS 3 2 1 0 0 0 0 0 0 0 0 0 WRALL W Reset 0 0 0 0 = Unimplemented or Reserved Figure 28-7. Flash Test Mode Register (FTSTMOD — Special Mode) MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 6 5 CBEIE CCIE KEYACC 0 0 0 R 4 3 2 1 0 Undefined 0 0 0 0 Undefined 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-8. Flash Configuration Register (FCNFG — Normal Mode) 7 6 5 R CBEIE CCIE KEYACC 0 0 0 4 3 2 1 0 0 0 0 BKSEL W Reset 0 0 0 0 0 = Unimplemented or Reserved Figure 28-9.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 R 6 5 4 3 2 1 0 RNV6 FPOPEN FPHDIS FPHS FPLDIS FPLS W Reset F F F F F F F F = Unimplemented or Reserved Figure 28-10. Flash Protection Register (FPROT) All bits in the FPROT register are readable and writable with restrictions (see Section 28.3.2.5.1, “Flash Protection Restrictions”) except for RNV[6] which is only readable.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Table 28-10. Flash Protection Function Function1 FPOPEN FPHDIS FPLDIS 1 1 1 No Protection 1 1 0 Protected Low Range 1 0 1 Protected High Range 1 0 0 Protected High and Low Ranges 0 1 1 Full Flash memory Protected 0 1 0 Unprotected Low Range 0 0 1 Unprotected High Range 0 0 0 Unprotected High and Low Ranges 1 For range sizes, refer to Table 28-11 and Table 28-12. Table 28-11.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 0x78_0000 FPHDIS=1 FPLDIS=1 FPHDIS=1 FPLDIS=0 FPHDIS=0 FPLDIS=1 FPHDIS=0 FPLDIS=0 7 6 5 4 Scenario 0x7F_8000 FPLS[1:0] FPOPEN=1 FPHS[1:0] 0x7F_FFFF 3 2 Scenario 1 0 0x78_0000 0x7F_8000 FPLS[1:0] FPOPEN=0 FPHS[1:0] 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 28-11.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.3.2.5.1 Flash Protection Restrictions The general guideline is that Flash protection can only be added and not removed. Table 28-13 specifies all valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear in special mode when starting a command write sequence. Table 28-14.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. 7 R 6 5 4 3 2 1 0 0 0 0 0 CMDB W Reset 1 1 0 0 0 = Unimplemented or Reserved Figure 28-14. Flash Command Register (FCMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 28-15.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Table 28-17. FCTL Field Descriptions Field Description 6:0 NV[6:0] Nonvolatile Bits — The NV[6:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits. 28.3.2.9 Flash Address Registers (FADDR) The FADDRHI and FADDRLO registers are the Flash address registers. 7 6 5 4 R 3 2 1 0 0 0 0 0 FADDRHI W Reset 0 0 0 0 = Unimplemented or Reserved Figure 28-16.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 7 6 5 4 R 3 2 1 0 0 0 0 0 FDATALO W Reset 0 0 0 0 = Unimplemented or Reserved Figure 28-19. Flash Data Low Register (FDATALO) All FDATAHI and FDATALO bits are readable but are not writable. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression signature is readable in the FDATA registers until a new command write sequence is started. 28.3.2.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-22. RESERVED3 All bits read 0 and are not writable. 28.3.2.14 RESERVED4 This register is reserved for factory testing and is not accessible. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 28-23. RESERVED4 All bits read 0 and are not writable. 28.4 28.4.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 28.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Table 28-18. Flash Command Description NVM Command Function on Flash Memory 0x06 Data Compress Compress data from a selected portion of the Flash block. The resulting signature is stored in the FDATA register. 0x20 Program 0x40 Sector Erase Erase all memory bytes in a sector of the Flash block. 0x41 Mass Erase Erase all memory bytes in the Flash block.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.1 Erase Verify Command The erase verify operation will verify that a Flash block is erased. An example flow to execute the erase verify operation is shown in Figure 28-25. The erase verify command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check 1.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.2 Data Compress Command The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flow to execute the data compress operation is shown in Figure 28-26. The data compress command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the data compress command.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Address to start compression and number of word addresses to compress 1.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.2.1 Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) for each Flash block to generate a 16-bit signature based on selected Flash array data. If multiple Flash blocks are selected for simultaneous compression, then the signature from each Flash block is further compressed to generate a single 16-bit signature.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 10. If Flash block 5 is selected for compression, DATA equal to the contents of the MISR for Flash block 5 is compressed into the MISR for Flash block 0. 11. If Flash block 6 is selected for compression, DATA equal to the contents of the MISR for Flash block 6 is compressed into the MISR for Flash block 0. 12.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.3 Program Command The program operation will program a previously erased word in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 28-28. The program command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the program command. The data written will be programmed to the address written.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 Write: Flash Address and program Data 1.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 28-29. The sector erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the sector erase command.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check 1.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.5 Mass Erase Command The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 28-30. The mass erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the mass erase command. The address and data written will be ignored.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes Access Error and Protection Violation Check 1.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.2.6 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase operation so that other sectors in a Flash block are available for read and program operations without waiting for the sector erase operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 28-31. The sector erase abort command write sequence is as follows: 1.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Execute Sector Erase Command Flow Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? Erase Abort Needed? no yes Sector Erase Completed no yes EXIT 1. Write: Dummy Flash Address and Dummy Data 2. Write: FCMD register Sector Erase Abort Cmd 0x47 3.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.4.3 Illegal Flash Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing a byte or misaligned word to a valid Flash address. 3. Starting a command write sequence while a data compress operation is active. 4.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 28.3.2.6, “Flash Status Register (FSTAT)”). 28.5 28.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 28.6.1 Unsecuring the MCU using Backdoor Key Access The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0x7F_FF00–0x7F_FF07). If the KEYEN[1:0] bits are in the enabled state (see Section 28.3.2.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access sequence in background debug mode (BDM). 28.6.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) Table 28-19. Flash Interrupt Sources Interrupt Source Interrupt Flag Local Enable Global (CCR) Mask Flash Address, Data and Command Buffers empty CBEIF (FSTAT register) CBEIE (FCNFG register) I Bit All Flash commands completed CCIF (FSTAT register) CCIE (FCNFG register) I Bit NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 28.8.
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) MC9S12XDP512 Data Sheet, Rev. 2.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.1 Introduction This document describes the FTX128K1 module that includes a 128 Kbyte Flash (nonvolatile) memory. The Flash memory may be read as either bytes, aligned words or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) • • Security feature to prevent unauthorized access to the Flash memory Code integrity check using built-in data compression 29.1.3 Modes of Operation Program, erase, erase verify, and data compress operations (please refer to Section 29.4.1, “Flash Command Operations” for details). 29.1.4 Block Diagram A block diagram of the Flash module is shown in Figure 29-1.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.3 Memory Map and Register Definition This section describes the memory map and registers for the Flash module. 29.3.1 Module Memory Map The Flash memory map is shown in Figure 29-2. The HCS12X architecture places the Flash memory addresses between global addresses 0x7E_0000 and 0x7F_FFFF. The FPROT register, described in Section 29.3.2.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) MODULE BASE + 0x0000 MODULE BASE + 0x000F Flash Registers 16 bytes FLASH START = 0x7E_0000 Flash Protected/Unprotected Region 96 Kbytes 0x7F_8000 0x7F_8400 0x7F_8800 0x7F_9000 Flash Protected/Unprotected Lower Region 1, 2, 4, 8 Kbytes 0x7F_A000 Flash Protected/Unprotected Region 8 Kbytes (up to 29 Kbytes) 0x7F_C000 0x7F_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 0x7F_F000 0x7F_F800 FLASH END = 0x7F_FFFF Flash Configuration
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.3.2 Register Descriptions The Flash module contains a set of 16 control and status registers located between module base + 0x0000 and 0x000F. A summary of the Flash module registers is given in Figure 29-3. Detailed descriptions of each register bit are provided.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Register Name RESERVED1 R Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESERVED2 R W RESERVED3 R W RESERVED4 R W Figure 29-3. FTX128K1 Register Summary (continued) 29.3.2.1 Flash Clock Divider Register (FCLKDIV) The FCLKDIV register is used to control timed events in program and erase algorithms.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 7 R 6 KEYEN 5 4 3 2 RNV5 RNV4 RNV3 RNV2 F F F F 1 0 SEC W Reset F F F F = Unimplemented or Reserved Figure 29-5. Flash Security Register (FSEC) All bits in the FSEC register are readable but are not writable. The FSEC register is loaded from the Flash Configuration Field at address 0x7F_FF0F during the reset sequence, indicated by F in Figure 29-5. Table 29-3.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 7 R 6 5 0 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 MRDS W Reset 0 0 0 = Unimplemented or Reserved Figure 29-6. Flash Test Mode Register (FTSTMOD) MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode. Table 29-6.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-8. FCNFG Field Descriptions Field Description 7 CBEIE Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command buffer in the Flash module. 0 Command buffer empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 29.3.2.6, “Flash Status Register (FSTAT)”) is set.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-9. FPROT Field Descriptions Field Description 7 FPOPEN Flash Protection Open — The FPOPEN bit determines the protection function for program or erase as shown in Table 29-10. 0 The FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS[1:0] and FPLS[1:0] bits.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-12. Flash Protection Lower Address Range FPLS[1:0] Global Address Range Protected Size 00 0x7F_8000–0x7F_83FF 1 Kbytes 01 0x7F_8000–0x7F_87FF 2 Kbytes 10 0x7F_8000–0x7F_8FFF 4 Kbytes 11 0x7F_8000–0x7F_9FFF 8 Kbytes All possible Flash protection scenarios are shown in Figure 29-9. Although the protection scheme is loaded from the Flash array at global address 0x7F_FF0D during the reset sequence, it can be changed by the user.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) FPHDIS=1 FPLDIS=1 FPHDIS=1 FPLDIS=0 7 6 0x7E_0000 FPHDIS=0 FPLDIS=1 Scenario FPHDIS=0 FPLDIS=0 5 4 0x7F_8000 FPLS[1:0] FPOPEN=1 FPHS[1:0] 0x7F_FFFF 3 2 Scenario 1 0 0x7E_0000 0x7F_8000 FPLS[1:0] FPOPEN=0 FPHS[1:0] 0x7F_FFFF Unprotected region Protected region with size defined by FPLS Protected region not defined by FPLS, FPHS Protected region with size defined by FPHS Figure 29-9.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.3.2.5.1 Flash Protection Restrictions The general guideline is that Flash protection can only be added and not removed. Table 29-13 specifies all valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the FPROT register reflect the active protection scenario.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear in special mode when starting a command write sequence. Table 29-14.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.3.2.7 Flash Command Register (FCMD) The FCMD register is the Flash command register. 7 R 6 5 4 3 2 1 0 0 0 0 0 CMDB W Reset 1 1 0 0 0 = Unimplemented or Reserved Figure 29-12. Flash Command Register (FCMD) All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable. Table 29-15.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-17. FCTL Field Descriptions Field Description 6:0 NV[6:0] Nonvolatile Bits — The NV[6:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits. 29.3.2.9 Flash Address Registers (FADDR) The FADDRHI and FADDRLO registers are the Flash address registers. 7 6 5 4 R 3 2 1 0 0 0 0 0 FADDRHI W Reset 0 0 0 0 = Unimplemented or Reserved Figure 29-14.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 7 6 5 4 R 3 2 1 0 0 0 0 0 FDATALO W Reset 0 0 0 0 = Unimplemented or Reserved Figure 29-17. Flash Data Low Register (FDATALO) All FDATAHI and FDATALO bits are readable but are not writable. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression signature is readable in the FDATA registers until a new command write sequence is started. 29.3.2.
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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-20. RESERVED3 All bits read 0 and are not writable. 29.3.2.14 RESERVED4 This register is reserved for factory testing and is not accessible. R 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset = Unimplemented or Reserved Figure 29-21. RESERVED4 All bits read 0 and are not writable. 29.4 29.4.
PAGE 1207
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.1.1 Writing the FCLKDIV Register Prior to issuing any Flash command after a reset, the user is required to write the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Since the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account.
PAGE 1208
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Tbus < 1µs? no ALL COMMANDS IMPOSSIBLE yes PRDIV8=0 (reset) oscillator_clock 12.8MHz? no yes PRDIV8=1 PRDCLK=oscillator_clock/8 PRDCLK[MHz]*(5+Tbus[µs]) an integer? yes PRDCLK=oscillator_clock no FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs])) FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1 TRY TO DECREASE Tbus FCLK=(PRDCLK)/(1+FDIV[5:0]) 1/FCLK[MHz] + Tbus[µs] > 5 AND FCLK > 0.
PAGE 1209
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.1.2 Command Write Sequence The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, erase abort, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 29.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF flag should be tested to determine the state of the address, data and command buffers.
PAGE 1210
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Table 29-18. Flash Command Description FCMDB NVM Command Function on Flash Memory 0x40 Sector Erase Erase all memory bytes in a sector of the Flash block. 0x41 Mass Erase Erase all memory bytes in the Flash block. A mass erase of the full Flash block is only possible when FPLDIS, FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command. 0x47 Sector Erase Abort Abort the sector erase operation.
PAGE 1211
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.1 Erase Verify Command The erase verify operation will verify that a Flash block is erased. An example flow to execute the erase verify operation is shown in Figure 29-23. The erase verify command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the erase verify command. The address and data written will be ignored. 2. Write the erase verify command, 0x05, to the FCMD register. 3.
PAGE 1212
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Block Address and Dummy Data 2. Write: FCMD register Erase Verify Command 0x05 3.
PAGE 1213
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.2 Data Compress Command The data compress operation will check Flash code integrity by compressing data from a selected portion of the Flash memory into a signature analyzer. An example flow to execute the data compress operation is shown in Figure 29-24. The data compress command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the data compress command.
PAGE 1214
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes Write: FSTAT register Clear ACCERR/PVIOL 0x30 1. Write: Flash Address to start compression and number of word addresses to compress 2.
PAGE 1215
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.2.1 Data Compress Operation The Flash module contains a 16-bit multiple-input signature register (MISR) to generate a 16-bit signature based on selected Flash array data. The final 16-bit signature, found in the FDATA registers after the data compress operation has completed, is based on the following logic equation which is executed on every data compression cycle during the operation: MISR[15:0] = {MISR[14:0], ^MISR[15,4,2,1]} ^ DATA[15:0] Eqn.
PAGE 1216
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.3 Program Command The program operation will program a previously erased word in the Flash memory using an embedded algorithm. An example flow to execute the program operation is shown in Figure 29-26. The program command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the program command. The data written will be programmed to the address written. 2.
PAGE 1217
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Address and program Data 2. Write: FCMD register Program Command 0x20 3.
PAGE 1218
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.4 Sector Erase Command The sector erase operation will erase all addresses in a 1 Kbyte sector of Flash memory using an embedded algorithm. An example flow to execute the sector erase operation is shown in Figure 29-27. The sector erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the sector erase command.
PAGE 1219
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Sector Address and Dummy Data 2. Write: FCMD register Sector Erase Command 0x40 3.
PAGE 1220
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.5 Mass Erase Command The mass erase operation will erase all addresses in a Flash block using an embedded algorithm. An example flow to execute the mass erase operation is shown in Figure 29-28. The mass erase command write sequence is as follows: 1. Write to a Flash block address to start the command write sequence for the mass erase command. The address and data written will be ignored. 2.
PAGE 1221
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) START Read: FCLKDIV register Clock Register Written Check FDIVLD Set? yes NOTE: FCLKDIV needs to be set once after each reset. no Write: FCLKDIV register Read: FSTAT register Address, Data, Command Buffer Empty Check CBEIF Set? no yes ACCERR/ PVIOL Set? no Access Error and Protection Violation Check yes 1. Write: Flash Block Address and Dummy Data 2. Write: FCMD register Mass Erase Command 0x41 3.
PAGE 1222
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.2.6 Sector Erase Abort Command The sector erase abort operation will terminate the active sector erase operation so that other sectors in a Flash block are available for read and program operations without waiting for the sector erase operation to complete. An example flow to execute the sector erase abort operation is shown in Figure 29-29. The sector erase abort command write sequence is as follows: 1.
PAGE 1223
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) Execute Sector Erase Command Flow Read: FSTAT register Bit Polling for Command Completion Check CCIF Set? Erase Abort Needed? no yes Sector Erase Completed no yes EXIT 1. Write: Dummy Flash Address and Dummy Data 2. Write: FCMD register Sector Erase Abort Cmd 0x47 3.
PAGE 1224
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.4.3 Illegal Flash Operations The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing a byte or misaligned word to a valid Flash address. 3. Starting a command write sequence while a data compress operation is active. 4.
PAGE 1225
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.5 29.5.1 Operating Modes Wait Mode If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (see Section 29.8, “Interrupts”). 29.5.
PAGE 1226
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) between the written data and the backdoor key data stored in the Flash memory. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially starting with 0x7F_FF00–1 and ending with 0x7F_FF06–7. 0x0000 and 0xFFFF are not permitted as backdoor keys.
PAGE 1227
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 29.6.2 Unsecuring the MCU in Special Single Chip Mode using BDM The MCU can be unsecured in special single chip mode by erasing the Flash module by the following method: • Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass erase command write sequence to erase the Flash memory.
PAGE 1228
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. 29.8.1 Description of Flash Interrupt Operation The logic used for generating interrupts is shown in Figure 29-30. The Flash module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the Flash command interrupt request. CBEIF CBEIE Flash Command Interrupt Request CCIF CCIE Figure 29-30.
PAGE 1229
Chapter 30 Security (S12X9SECV2) 30.1 Introduction This specification describes the function of the security mechanism in the S12X chip family (S12X9SECV2). 30.1.1 Features The user must be reminded that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to put a backdoor in the application program.
PAGE 1230
Chapter 30 Security (S12X9SECV2) Table 30-1.
PAGE 1231
Chapter 30 Security (S12X9SECV2) The meaning of the bits KEYEN[1:0] is shown in Table 30-2. Please refer to Section 30.1.5.1, “Unsecuring the MCU Using the Backdoor Key Access” for more information. Table 30-2. Backdoor Key Access Enable Bits KEYEN[1:0] Backdoor Key Access Enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) The meaning of the security bits SEC[1:0] is shown in Table 30-3. For security reasons, the state of device security is controlled by two bits.
PAGE 1232
Chapter 30 Security (S12X9SECV2) 30.1.4.1 • • • • Background debug module (BDM) operation is completely disabled. Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide (FTX) for details. Tracing code execution using the DBG module is disabled. Debugging XGATE code (breakpoints, single-stepping) is disabled. 30.1.4.2 • • • • • Normal Single Chip Mode (NS) Special Single Chip Mode (SS) BDM firmware commands are disabled.
PAGE 1233
Chapter 30 Security (S12X9SECV2) 30.1.5 Unsecuring the Microcontroller Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes) 30.1.5.1 Unsecuring the MCU Using the Backdoor Key Access In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method.
PAGE 1234
Chapter 30 Security (S12X9SECV2) If all four 16-bit words match the Flash contents at 0xFF00–0xFF07 (0x7F_FF00–0x7F_FF07), the microcontroller will be unsecured and the security bits SEC[1:0] in the Flash Security register FSEC will be forced to the unsecured state (‘10’). The contents of the Flash options/security byte are not changed by this procedure, and so the microcontroller will revert to the secure state after the next reset unless further action is taken as detailed below.
PAGE 1235
Chapter 30 Security (S12X9SECV2) Special single chip erase and unsecure sequence: 1. Reset into special single chip mode. 2. Write an appropriate value to the ECLKDIV register for correct timing. 3. Write 0xFF to the EPROT register to disable protection. 4. Write 0x30 to the ESTAT register to clear the PVIOL and ACCERR bits. 5. Write 0x0000 to the EDATA register (0x011A–0x011B). 6. Write 0x0000 to the EADDR register (0x0118–0x0119). 7. Write 0x41 (mass erase) to the ECMD register. 8.
PAGE 1236
Chapter 30 Security (S12X9SECV2) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1237
Appendix A Electrical Characteristics Appendix A Electrical Characteristics A.1 General This supplement contains the most accurate electrical information for the S12XD, S12XB & S12XA families microcontroller available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods.
PAGE 1238
Appendix A Electrical Characteristics NOTE In the following context VDD35 is used for either VDDA, VDDR, and VDDX; VSS35 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD35 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2. A.1.3 Pins There are four groups of functional pins. A.1.3.
PAGE 1239
Appendix A Electrical Characteristics A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.
PAGE 1240
Appendix A Electrical Characteristics specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2. ESD and Latch-up Test Conditions Model Description Human Body Latch-up Symbol Value Unit Series resistance R1 1500 Ohm Storage capacitance C 100 pF Number of pulse per pin Positive Negative — — 3 3 Minimum input voltage limit –2.5 V Maximum input voltage limit 7.5 V Table A-3.
PAGE 1241
Appendix A Electrical Characteristics A.1.7 Operating Conditions This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, “Power Dissipation and Thermal Characteristics”. Table A-4.
PAGE 1242
Appendix A Electrical Characteristics A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded.
PAGE 1243
Appendix A Electrical Characteristics Table A-5.
PAGE 1244
Appendix A Electrical Characteristics A.1.9 I/O Characteristics This section describes the characteristics of all I/O pins except EXTAL, XTAL,XFC,TEST,VREGEN and supply pins. CAUTION The internal pull up/pull down device specification is different depending on maskset. Table A-6. 3.3-V I/O Characteristics Conditions are 3.15 V < VDD35 < 3.6 V temperature from –40°C to +140°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,XFC,TEST, VREGEN and supply pins.
PAGE 1245
Appendix A Electrical Characteristics Table A-6. 3.3-V I/O Characteristics Conditions are 3.15 V < VDD35 < 3.6 V temperature from –40°C to +140°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,XFC,TEST, VREGEN and supply pins. 17 C Port H, J, P interrupt input pulse filtered3 tPULSE — — 3 µs 18 3 tPULSE 10 — — µs C Port H, J, P interrupt input pulse passed 1 Maximum leakage current occurs at maximum operating temperature.
PAGE 1246
Appendix A Electrical Characteristics Table A-7. 5-V I/O Characteristics Conditions are 4.5 V < VDD35 < 5.5 V temperature from –40°C to +140°C, unless otherwise noted I/O Characteristics for all I/O pins except EXTAL, XTAL,XFC,TEST, VREGEN and supply pins. Num C 1 Rating Symbol Min Typ Max Unit 0.65*VDD35 — — V P Input high voltage V T Input high voltage VIH — — VDD35 + 0.3 V P Input low voltage VIL — — 0.35*VDD35 V T Input low voltage VIL VSS35 – 0.
PAGE 1247
Appendix A Electrical Characteristics Table A-8. I/O Characteristics for Port C, D, PE5, PE6, and PK7 for Reduced Input Voltage Thresholds Conditions are 4.5 V < VDD35 < 5.5 V Temperature from –40°C to +140°C, unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Input high voltage VIH 1.75 — — V 2 P Input low voltage VIL — — 0.75 V 3 C Input hysteresis VHYS — 100 — mV A.1.
PAGE 1248
Appendix A Electrical Characteristics Table A-9. shows the configuration of the peripherals for run current measurement. Table A-9.
PAGE 1249
Appendix A Electrical Characteristics A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data, and control signals as well as on the duty cycle of those signals. No generally applicable numbers can given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-10.
PAGE 1250
Appendix A Electrical Characteristics Table A-11.
PAGE 1251
Appendix A Electrical Characteristics A.2 ATD Characteristics This section describes the characteristics of the analog-to-digital converter. A.2.1 ATD Operating Characteristics The Table A-12 and Table A-13 show conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to.
PAGE 1252
Appendix A Electrical Characteristics Table A-13. ATD Operating Characteristics 3.3V Conditions are shown in Table A-4 unless otherwise noted, Supply Voltage 3.15V < VDDA < 3.6V Num C 1 2 D Reference potential Low High Symbol Min Typ Max Unit VRL VRH VSSA VDDA/2 — — VDDA/2 VDDA V V 2 C Differential reference voltage1 VRH-VRL 3.15 3.3 3.6 V 3 D ATD clock frequency fATDCLK 0.5 — 2.0 MHz 4 D ATD 10-bit conversion period Clock cycles2 Conv, time at 2.
PAGE 1253
Appendix A Electrical Characteristics A.2.2.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted.
PAGE 1254
Appendix A Electrical Characteristics A.2.3 A.2.3.1 ATD Accuracy 5-V Range Table A-15 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance, and source resistance. Table A-15. 5-V ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH–VRL = 5.12 V. Resulting to one 8-bit count = 20 mV and one 10-bit count = 5 mV fATDCLK = 2.
PAGE 1255
Appendix A Electrical Characteristics A.2.3.3 ATD Accuracy Definitions For the following definitions see also Figure A-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps. V –V i i–1 DNL ( i ) = --------------------------- – 1 1LSB The integral non-linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = ∑ V –V n 0 DNL ( i ) = --------------------- – n 1LSB i=1 MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1256
Appendix A Electrical Characteristics DNL Vi-1 10-Bit Absolute Error Boundary LSB Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $FF $3FC $3FB $3FA $3F9 $FE $3F8 $3F7 $3F6 $3F5 10-Bit Resolution $3F3 9 Ideal Transfer Curve 2 8 8-Bit Resolution $FD $3F4 7 10-Bit Transfer Curve 6 5 1 4 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 50 50555060506550705075508050855090509551005105511051155120 Vin mV Figure A-1.
PAGE 1257
Appendix A Electrical Characteristics A.3 NVM, Flash, and EEPROM NOTE Unless otherwise noted the abbreviation NVM (nonvolatile memory) is used for both Flash and EEPROM. A.3.1 NVM Timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations.
PAGE 1258
Appendix A Electrical Characteristics A.3.1.3 Sector Erase Erasing a 1024-byte Flash sector or a 4-byte EEPROM sector takes: t era 1 ≈ 4000 ⋅ ------------------------f NVMOP The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: t mass 1 ≈ 20000 ⋅ ------------------------f NVMOP The setup time can be ignored for this operation. A.3.1.
PAGE 1259
Appendix A Electrical Characteristics Table A-17. NVM Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 6 7 Unit — 801 MHz 2 D Bus frequency for programming or erase operations fNVMBUS 1 — — MHz 3 D Operating frequency fNVMOP 150 — 200 tswpgm 2 P Single word programming time D Flash burst programming consecutive word 6 D Flash burst programming time for 64 words 7 P Sector erase time 10 5 Max 0.
PAGE 1260
Appendix A Electrical Characteristics A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed Table A-18.
PAGE 1261
Appendix A Electrical Characteristics Figure A-2. Typical Endurance vs Temperature 500 Typical Endurance [103 Cycles] 450 400 350 300 250 200 150 100 50 0 -40 -20 0 20 40 60 80 100 120 140 Operating Temperature TJ [°C] ------ Flash ------ EEPROM MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1262
Appendix A Electrical Characteristics A.4 Voltage Regulator Table A-19. Voltage Regulator Electrical Characteristics Num C 1 P Input voltages 2 P Output voltage core Full performance mode Reduced power mode Shutdown mode VDD Output Voltage PLL Full Performance Mode Reduced power mode Shutdown mode VDDPLL 3 4 5 6 7 1 2 3 4 5 6 7 P P P C C Characteristic Low-voltage interrupt3 Assert level Deassert level Low-voltage reset4 5 Assert level Symbol Min Typ Max Unit VVDDR,A 3.
PAGE 1263
Appendix A Electrical Characteristics A.4.1 Chip Power-up and Voltage Drops MC9S12XDP512 sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Figure 0-1 MC9S12XDP512 - Chip Power-up and Voltage Drops (not scaled) V VDDA VLVID VLVIA VDD VLVRD VLVRA VPORD t LVI LVI enabled LVI disabled due to LVR POR LVR A.4.2 A.4.2.
PAGE 1264
Appendix A Electrical Characteristics Table A-20. MC9S12XDP512 - Capacitive Loads Num Characteristic 1 VDD external capacitive load 2 VDDPLL external capacitive load Symbol Min Recommended Max Unit CDDext 400 440 12000 nF CDDPLLext 90 220 5000 nF MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1265
Appendix A Electrical Characteristics A.5 Reset, Oscillator, and PLL This section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked loop (PLL). A.5.1 Startup Table A-21 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide. Table A-21.
PAGE 1266
Appendix A Electrical Characteristics If the MCU is woken-up by an interrupt and the fast wake-up feature is enabled (FSTWKP = 1 and SCME = 1), the system will resume operation in self-clock mode after tfws. A.5.1.5 Pseudo Stop and Wait Recovery The recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector. A.5.
PAGE 1267
Appendix A Electrical Characteristics Table A-22. Oscillator Characteristics Conditions are shown in Table A-4 unless otherwise noted Num 1a C Rating C Crystal oscillator range (loop controlled Pierce) 1, 2 Symbol Min Typ Max Unit fOSC 4.0 — 16 MHz 1b C Crystal oscillator range (full swing Pierce) fOSC 0.5 — 40 MHz 2 P Startup current iOSC 100 — — µA 504 ms 2.
PAGE 1268
Appendix A Electrical Characteristics A.5.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s voltage controlled oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Cp VDDPLL Cs R XFC Pin Phase fosc fref 1 D refdv+1 VCO fvco KF fcmp KV Detector Loop Divider 1 synr+1 1 2 Figure A-3.
PAGE 1269
Appendix A Electrical Characteristics f f 2⋅ζ⋅f ref ref 1 < ------------------------------------------- ⋅ ----- → f < ------------- ;( ζ = 0.9 ) C C 4 ⋅ 10 10 2 π ⋅ ⎛ζ + 1 + ζ ⎞ ⎝ ⎠ fC < 100kHz And finally the frequency relationship is defined as f VCO n = --------------- = 2 ⋅ ( synr + 1 ) f ref = 20 With the above values the resistance can be calculated.
PAGE 1270
Appendix A Electrical Characteristics The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as: t (N) t (N) ⎞ ⎛ max min J ( N ) = max ⎜ 1 – ----------------------- , 1 – ----------------------- ⎟ N⋅t N⋅t ⎝ nom nom ⎠ For N < 1000, the following equation is a good fit for the maximum jitter: j 1 J ( N ) = -------- + j N 2 J(N) 1 5 10 20 N Figure A-5.
PAGE 1271
Appendix A Electrical Characteristics Table A-23. PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol Min Typ Max Unit 1 P Self clock mode frequency fSCM 1 — 5.5 MHz 2 D VCO locking range fVCO 8 — 80 MHz 3 D Lock detector transition from acquisition to tracking mode |∆trk| 3 — 4 %1 4 D Lock detection |∆Lock| 0 — 1.5 %1 5 D Unlock detection |∆unl| 0.5 — 2.
PAGE 1272
Appendix A Electrical Characteristics A.7 SPI Timing This section provides electrical parametrics and ratings for the SPI. In Table A-25 the measurement conditions are listed. Table A-25. Measurement Conditions Description Drive mode Load capacitance CLOAD1, on all outputs Thresholds for delay measurement points 1 Value Unit Full drive mode — 50 pF (20% / 80%) VDDX V Timing specified for equal load on all SPI output pins. Avoid asymmetric load. A.7.
PAGE 1273
Appendix A Electrical Characteristics SS1 (Output) 1 2 12 13 12 13 3 SCK (CPOL = 0) (Output) 4 4 SCK (CPOL = 1) (Output) 5 MISO (Input) 6 MSB IN2 Bit 6 . . . 1 11 9 MOSI (Output) Port Data LSB IN Master MSB OUT2 Bit 6 . . . 1 Master LSB OUT Port Data 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-7. SPI Master Timing (CPHA = 1) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1274
Appendix A Electrical Characteristics In Table A-26 the timing characteristics for master mode are listed. Table A-26.
PAGE 1275
Appendix A Electrical Characteristics SS (Input) 1 12 13 3 12 13 SCK (CPOL = 0) (Input) 4 2 4 SCK (CPOL = 1) (Input) 10 8 7 MISO (Output) 9 See Note Slave MSB 5 MOSI (Input) Bit 6 . . . 1 11 11 Slave LSB OUT See Note 6 MSB IN Bit 6 . . . 1 LSB IN NOTE: Not defined Figure A-9. SPI Slave Timing (CPHA = 0) MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1276
Appendix A Electrical Characteristics In Figure A-10 the timing diagram for slave mode with transmission format CPHA = 1 is depicted. SS (Input) 3 1 2 12 13 12 13 SCK (CPOL = 0) (Input) 4 4 SCK (CPOL = 1) (Input) See Note 7 Slave MSB OUT 5 MOSI (Input) 8 11 9 MISO (Output) Bit 6 . . . 1 Slave LSB OUT 6 MSB IN Bit 6 . . . 1 LSB IN NOTE: Not defined Figure A-10. SPI Slave Timing (CPHA = 1) In Table A-27 the timing characteristics for slave mode are listed. Table A-27.
PAGE 1277
Appendix A Electrical Characteristics A.8 External Bus Timing The following conditions are assumed for all following external bus timing values: • Crystal input within 45% to 55% duty • Equal loads of pins • Pad full drive (reduced drive must be off) A.8.1 Normal Expanded Mode (External Wait Feature Disabled) 1 1 CSx ADDRx ADDR1 2 ADDR2 3 RE 4 5 WE 8 6 7 10 DATAx (Read) DATA1 11 (Write) DATA2 9 EWAIT UDS, LDS Figure A-11.
PAGE 1278
Appendix A Electrical Characteristics Table A-28. Example 1a: Normal Expanded Mode Timing VDD35 = 5.0 V (EWAITE = 0) 1 No. C Characteristic — — Frequency of internal bus — — Internal cycle time — — Frequency of external bus 1 — External cycle time (selected by EXSTR) 1 Symbol Min Max Unit fi D.C. 40.0 MHz tcyc 25 ∞ ns fo D.C. 20.
PAGE 1279
Appendix A Electrical Characteristics A.8.2 Normal Expanded Mode (External Wait Feature Enabled) 1 CSx ADDRx ADDR1 2 ADDR2 3 RE WE 8 6 7 (Read) DATA1 DATAx 12 13 EWAIT UDS, LDS Figure A-12. Example 1b: Normal Expanded Mode — Stretched Read Access MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1280
Appendix A Electrical Characteristics 1 CSx ADDRx ADDR1 ADDR2 RE 4 5 WE 9 10 DATAx 11 (Write) DATA1 12 13 EWAIT UDS, LDS Figure A-13. Example 1b: Normal Expanded Mode — Stretched Write Access MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1281
Appendix A Electrical Characteristics Table A-29. Example 1b: Normal Expanded Mode Timing VDD35 = 5.0 V (EWAITE = 1) No. C Characteristic 2 Symbol 3 Stretch Cycles Unit Min Max Min Max fi D.C. 40.0 D.C. 40.0 MHz tcyc 25 ∞ 25 ∞ ns fo D.C. 13.3 D.C. 10.
PAGE 1282
Appendix A Electrical Characteristics A.8.3 Emulation Single-Chip Mode (Without Wait States) 1 1 2 3 ECLK2X ECLK 5 4 7 6 ADDR [22:20]/ ACC [2:0] ADDR1 ACC1 ADDR2 ACC2 ADDR3 ADDR [19:16]/ IQSTAT [3:0] ADDR1 IQSTAT0 ADDR2 IQSTAT1 ADDR3 ADDR [15:0]/ IVD [15:0] ADDR1 IVD0 ADDR2 IVD1 ADDR3 8 9 DATAx DATA0 (Read) DATA1 (Write) DATA2 10 12 11 12 R/W LSTRB Figure A-14. Example 2a: Emulation Single-Chip Mode — Read Followed by Write MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1283
Appendix A Electrical Characteristics Table A-30. Example 2a: Emulation Single-Chip Mode Timing VDD35 = 5.0 V (EWAITE = 0) Characteristic1 Symbol Min Max Unit fi D.C. 40.0 MHz tcyc 25 ∞ ns Pulse width, E high PWEH 11.5 — ns D Pulse width, E low PWEL 11.5 — ns 4 D Address delay time tAD — 5 ns 5 D Address hold time tAH 0 — ns No. C — — Frequency of internal bus 1 — Cycle time 2 D 3 2 6 D IVDx delay time tIVDD — 4.
PAGE 1284
Appendix A Electrical Characteristics A.8.4 Emulation Expanded Mode (With Optional Access Stretching) 1 2 3 ECLK2X ECLK 5 4 7 6 ADDR [22:20]/ ACC [2:0] ADDR1 ADDR [19:16]/ IQSTAT [3:0] ADDR1 ADDR [15:0]/ IVD [15:0] ADDR1 ACC1 IQSTAT0 ? ADDR1 ADDR1 ADDR1 000 IQSTAT1 ADDR2 ADDR2 IVD1 ADDR2 8 9 DATAx DATA0 (Read) DATA1 12 12 R/W LSTRB Figure A-15. Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1285
Appendix A Electrical Characteristics 1 2 3 ECLK2X ECLK 4 5 7 6 ADDR [22:20]/ ACC [2:0] ADDR1 ACC1 ADDR1 ADDR [19:16]/ IQSTAT [3:0] ADDR1 IQSTAT0 ADDR1 ADDR [15:0]/ IVD [15:0] ADDR1 ? ADDR1 000 IQSTAT1 x ADDR2 ADDR2 ADDR2 10 DATAx 11 (write) data1 12 12 R/W LSTRB Figure A-16. Example 2b: Emulation Expanded Mode Ò Write with 1 Stretch Cycle MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1286
Appendix A Electrical Characteristics Table A-31. Example 2b: Emulation Expanded Mode Timing VDD35 = 5.0 V (EWAITE = 0) No. 1 C Characteristic Symbol 1 Stretch Cycle Min Max 2 Stretch Cycles Min Max 3 Stretch Cycles Min Max Unit — — Internal cycle time tcyc 25 25 25 25 25 25 ns 1 — Cycle time tcyce 50 ∞ 75 ∞ 100 ∞ ns 2 D Pulse width, E high PWEH 11.5 14 11.5 14 11.5 14 ns 3 D E falling to sampling E rising tEFSR 35 39.5 60 64.5 85 89.
PAGE 1287
Appendix A Electrical Characteristics A.8.5 External Tag Trigger Timing 1 ECLK ADDR ADDR DATAx DATA R/W 2 TAGHI/TAGLO 3 Figure A-17. External Trigger Timing Table A-32. External Tag Trigger Timing VDD35 = 5.0 V 1 Characteristic 1 No. C 1 D Frequency of internal bus 2 D 3 4 Symbol Min Max Unit fi D.C. 40.0 MHz Cycle time tcyc 25 ∞ ns D TAGHI/TAGLO setup time tTS 11.
PAGE 1288
Appendix B Package Information Appendix B Package Information This section provides the physical dimensions of the MC9S12XD Family packages. MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1289
Appendix B Package Information B.1 144-Pin LQFP 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 36 TIPS 144 109 1 108 4X J1 P J1 L M CL B V X 140X B1 VIEW Y 36 V1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE.
PAGE 1290
Appendix B Package Information B.2 112-Pin LQFP Package 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X X X=L, M OR N G VIEW Y B L V M B1 28 57 29 F D 56 0.13 N S1 A S C2 VIEW AB θ2 0.050 0.10 T 112X SEATING PLANE θ3 T θ R R2 R 0.25 R1 GAGE PLANE (K) C1 M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 C AA J V1 E θ1 (Y) (Z) VIEW AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.
PAGE 1291
Appendix B Package Information B.3 80-Pin QFP Package L 60 41 61 D S M V P B C A-B D 0.20 M B B -A-,-B-,-D- 0.20 L H A-B -B- 0.05 D -A- S S S 40 DETAIL A DETAIL A 21 80 1 0.20 A H A-B M S F 20 -DD S 0.05 A-B J S 0.20 C A-B M S D S D M E DETAIL C C -H- -C- DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.10 H SEATING PLANE N M G U T DATUM PLANE -H- R K W Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.
PAGE 1292
Appendix C Recommended PCB Layout Appendix C Recommended PCB Layout The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1–C6). • Central point of the ground star should be the VSSR pin. • Use low ohmic low inductance connections between VSS1, VSS2, and VSSR.
PAGE 1293
Appendix C Recommended PCB Layout Table C-1.
PAGE 1294
Appendix C Recommended PCB Layout C6 VDDX Figure C-1. 144-Pin LQFP Recommended PCB Layout VSSA VREGEN C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VDDX2 VDDR2 C11 C12 VSSX2 VSSR2 C5 Q1 C7 VSSPLL C10 VDDPLL C9 C8 VDDR1 C4 VSSR1 R1 MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1295
Appendix C Recommended PCB Layout C6 VDDX Figure C-2. 112-Pin LQFP Recommended PCB Layout VSSA VREGEN VSSX C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 C5 C7 C10 C9 VDDPLL VSSPLL Q1 C8 VDDR C4 VSSR R1 MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1296
Appendix C Recommended PCB Layout VREGEN C6 VDDX Figure C-3. 80-Pin QFP Recommended PCB Layout VSSX VSSA C3 VDDA VDD1 VSS2 C1 C2 VSS1 C5 VSSPLL Q1 C8 VDDR C7 VSSR C4 VDD2 C10 C9 VSSPLL R1 VDDPLL MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1297
Appendix D Using L15Y Silicon Appendix D Using L15Y Silicon The following items should be considerd when using L15Y Silicon: • Do not write or read to registers which are marked “Reserved” in Table 1-1. • Fill the interrupt vector locations which are marked “Reserved” in Table 1-12. according to your coding policies for unused interrupts • L15Y Silicon includes two analog to digital converters ATD0 and ATD1.
PAGE 1298
Appendix E Derivative Differences Appendix E Derivative Differences E.1 Memory Sizes and Package Options S12XD - Family Table E-1.
PAGE 1299
Appendix E Derivative Differences Table E-1. Memory Sizes and Package Options S12XD-Family Device Package Flash RAM EEPROM 128K 8K 2K 64K 4K 1K ROM 112 LQFP 9S12XD128 80 QFP 9S12XD64 80 QFP MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1300
Appendix E Derivative Differences E.2 Memory Sizes and Package Options S12XA & S12XB Family Table E-2. S12XA - Family Memory Sizes Device Package Flash RAM 512K 32K EEPROM 144 LQFP 9S12XA512 112 LQFP 80 QFP 4K 144 LQFP 9S12XA256 112 LQFP 256K 16K 128K 12K 80 QFP 112 LQFP 9S12XA128 2K 80 QFP Table E-3. S12XB - Family Memory Sizes Device Package Flash RAM EEPROM 256K 10K 2K 128K 6K 1K 112 LQFP 9S12XB256 80 QFP 112 LQFP 9S12XB128 80 QFP MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1301
Appendix E Derivative Differences E.3 MC9S12XD-Family Flash Configuration1 2 3 4 5 Figure E-1. MC9S12XD Family Flash Configuration Global Address DP512 A512 DT384 DQ256 A/B256 128k 128k 128k DG128 A/B128 D64 $78_0000 (PPAGE $E0) $7A_0000 (PPAGE $E8) 128k $7C_0000 (PPAGE $F0) 128k 128k 128k 128k $7E_0000 (PPAGE $F8) 128k 128k 64k Shared XGATE/CPU area Not implemented 1. XGATE read access to Flash not possible on DG128/D128/A128/B128 and D64 2.
PAGE 1302
Appendix E Derivative Differences E.4 MC9S12XD/A/B -Family SRAM & EEPROM Configuration Figure E-2.
PAGE 1303
Appendix E Derivative Differences E.5 Peripheral Sets S12XD - Family Table E-5.
PAGE 1304
Appendix E Derivative Differences 2 ATD1 routed to PAD[23:8] ATD1 routed to PAD[15:8] 4 ATD1 routed to PAD[15:0] instead of PAD[23:8] 5 ATD1 routed to PAD[7:0] instead of PAD[15:8] 3 E.6 Peripheral Sets S12XA & S12XB - Family Table E-6.
PAGE 1305
Appendix E Derivative Differences E.7 Pinout explanations: • A/D is the number of modules/total number of A/D channels. • I/O is the sum of ports capable to act as digital input or output.
PAGE 1306
Appendix F Ordering Information Appendix F Ordering Information The following figure provides an ordering number example for the devices covered by this data book. There are two options when ordering a device.
PAGE 1307
Appendix G Detailed Register Map Appendix G Detailed Register Map The following tables show the detailed register map of the MC9S12XD-Family.
PAGE 1308
Appendix G Detailed Register Map 0x000E–0x000F External Bus Interface (S12XEBI) Map Address Name 0x000E EBICTL0 0x000F EBICTL1 Bit 7 R ITHRS W R EWAITE W Bit 6 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HDBE ASIZ4 ASIZ3 ASIZ2 ASIZ1 ASIZ0 0 0 0 EXSTR2 EXSTR1 EXSTR0 0x0010–0x0017 Module Mapping Control (S12XMMC) Map 2 of 4 Address Name 0x0010 GPAGE 0x0011 DIRECT 0x0012 Reserved 0x0013 MMCCTL1 0x0014 Reserved 0x0015 Reserved 0x0016 RPAGE 0x0017 EPAGE Bit 7 R W R W R W
PAGE 1309
Appendix G Detailed Register Map 0x001C–0x001F Port Integration Module (PIM) Map 3 of 5 Address Name 0x001D Reserved 0x001E IRQCR 0x001F Reserved R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 IRQE IRQEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XGSBPE BDM 0 0 0x0020–0x0027 Debug Module (S12XDBG) Map Address Name 0x0020 DBGC1 0x0021 DBGSR 0x0022 DBGTCR 0x0023 DBGC2 0x0024 DBGTBH 0x0025 DBGTBL
PAGE 1310
Appendix G Detailed Register Map 2 This represents the contents if the Comparator B or D control register is blended into this address MC9S12XDP512 Data Sheet, Rev. 2.
PAGE 1311
Appendix G Detailed Register Map 0x0030–0x0031 Module Mapping Control (S12XMMC) Map 3 of 4 Address Name 0x0030 PPAGE 0x0031 Reserved R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 0 0 0 0 0 0 0 0 0x0032–0x0033 Port Integration Module (PIM) Map 4 of 5 Address Name 0x0032 PORTK 0x0033 DDRK R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 DDRK7 DDRK6 DDRK5 DDRK4 DDR
PAGE 1312
Appendix G Detailed Register Map 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 1 of 3) Address Name 0x0040 TIOS 0x0041 CFORC 0x0042 OC7M 0x0043 OC7D 0x0044 TCNT (hi) 0x0045 TCNT (lo) 0x0046 TSCR1 0x0047 TTOV 0x0048 TCTL1 0x0049 TCTL2 0x004A TCTL3 0x004B TCTL4 0x004C TIE 0x004D TSCR2 0x004E TFLG1 0x004F TFLG2 0x0050 TC0 (hi) 0x0051 TC0 (lo) 0x0052 TC1 (hi) 0x0053 TC1 (lo) 0x0054 TC2 (hi) 0x0055 TC2 (lo) R W R W R W R W R W R W R W R W R
PAGE 1313
Appendix G Detailed Register Map 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 2 of 3) Address Name 0x0056 TC3 (hi) 0x0057 TC3 (lo) 0x0058 TC4 (hi) 0x0059 TC4 (lo) 0x005A TC5 (hi) 0x005B TC5 (lo) 0x005C TC6 (hi) 0x005D TC6 (lo) 0x005E TC7 (hi) 0x005F TC7 (lo) 0x0060 PACTL 0x0061 PAFLG 0x0062 PACN3 (hi) 0x0063 PACN2 (lo) 0x0064 PACN1 (hi) 0x0065 PACN0 (lo) 0x0066 MCCTL 0x0067 MCFLG 0x0068 ICPAR 0x0069 DLYCT 0x006A ICOVW 0x006B ICSYS 0x0
PAGE 1314
Appendix G Detailed Register Map 0x0040–0x007F Enhanced Capture Timer 16-Bit 8-Channels (ECT) Map (Sheet 3 of 3) Address Name 0x006D TIMTST 0x006E PTPSR 0x006F PTMCPSR 0x0070 PBCTL 0x0071 PBFLG 0x0072 PA3H 0x0073 PA2H 0x0074 PA1H 0x0075 PA0H 0x0076 MCCNT (hi) 0x0077 MCCNT (lo) 0x0078 TC0H (hi) 0x0079 TC0H (lo) 0x007A TC1H (hi) 0x007B TC1H (lo) 0x007C TC2H (hi) 0x007D TC2H (lo) 0x007E TC3H (hi) 0x007F TC3H (lo) Bit 7 R 0 W R PTPS7 W R PTMPS7 W R 0 W R 0 W R PA3H7 W R
PAGE 1315
Appendix G Detailed Register Map 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 1 of 3) Address Name 0x0080 ATD1CTL0 0x0081 ATD1CTL1 0x0082 ATD1CTL2 0x0083 ATD1CTL3 0x0084 ATD1CTL4 0x0085 ATD1CTL5 0x0086 ATD1STAT0 0x0087 Reserved 0x0088 ATD1TEST0 0x0089 ATD1TEST1 0x008A ATD1STAT2 0x008B ATD1STAT1 0x008C ATD1DIEN0 0x008D ATD1DIEN 0x008E ATD1PTAD0 0x008F ATD1PTAD1 0x0090 ATD1DR0H 0x0091 ATD1DR0L 0x0092 ATD1DR1H 0x0093 ATD1DR1L 0x0094
PAGE 1316
Appendix G Detailed Register Map 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 2 of 3) Address Name 0x0096 ATD1DR3H 0x0097 ATD1DR3L 0x0098 ATD1DR4H 0x0099 ATD1DR4L 0x009A ATD1DR5H 0x009B ATD1DR5L 0x009C ATD1DR6H 0x009D ATD1DR6L 0x009E ATD1DR7H 0x009F ATD1DR7L 0x00A0 ATD1DR8H 0x00A1 ATD1DR8L 0x00A2 ATD1DR9H 0x00A3 ATD1DR9L 0x00A4 ATD1DR10H 0x00A5 ATD1DR10L 0x00A6 ATD1DR11H 0x00A7 ATD1DR11L 0x00A8 ATD1DR12H 0x00A9 ATD1DR12L 0x00AA AT
PAGE 1317
Appendix G Detailed Register Map 0x0080–0x00AF Analog-to-Digital Converter 10-bit 16-Channels (ATD1) Map (Sheet 3 of 3) Address Name 0x00AC ATD1DR14H 0x00AD 0x00AE 0x00AF R W R ATD1DR14L W R ATD1DR15H W R ATD1DR15L W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit 0 0x00B0–0x00B7 Inter IC Bus (IIC1) Map Address Name 0x00B0 IBAD 0x00B1 IBFD 0x00B2 IBCR
PAGE 1318
Appendix G Detailed Register Map 0x00B8–0x00BF Asynchronous Serial Interface (SCI2) Map (continued) Address Name 0x00BB SCI2CR2 0x00BC SCI2SR1 0x00BD SCI2SR2 0x00BE SCI2DRH 0x00BF SCI2DRL 1 2 R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIE TCIE RIE ILIE TE RE RWU SBK TDRE TC RDRF IDLE OR NF FE PF 0 0 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 AMAP R8 R7 T7 T8 R6 T6 RAF Those registers are accessi
PAGE 1319
Appendix G Detailed Register Map 0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map Address Name 0x00C8 SCI0BDH1 0x00C9 SCI0BDL1 0x00CA SCI0CR11 0x00C8 SCI0ASR12 0x00C9 SCI0ACR12 0x00CA SCI0ACR22 0x00CB SCI0CR2 0x00CC SCI0SR1 0x00CD SCI0SR2 0x00CE SCI0DRH 0x00CF SCI0DRL 1 2 Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W R AMAP W R R8 W R R7 W T7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR6
PAGE 1320
Appendix G Detailed Register Map 0x00D0–0x00D7 Asynchronous Serial Interface (SCI1) Map (continued) Address 1 2 Name 0x00D5 SCI1SR2 0x00D6 SCI1DRH 0x00D7 SCI1DRL Bit 7 R W R W R W AMAP R8 R7 T7 Bit 6 Bit 5 0 0 T8 R6 T6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 RAF Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to zero Those registers are accessible if the AMAP bit in the SCI1SR2
PAGE 1321
Appendix G Detailed Register Map 0x00E0–0x00E7 Inter IC Bus (IIC0) Map (continued) Address Name 0x00E5 Reserved 0x00E6 Reserved 0x00E7 Reserved R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PAGE 1322
Appendix G Detailed Register Map 0x00F8–0x00FF Serial Peripheral Interface (SPI2) Map Address Name 0x00F8 SPI2CR1 0x00F9 SPI2CR2 0x00FA SPI2BR 0x00FB SPI2SR 0x00FC Reserved 0x00FD SPI2DR 0x00FE Reserved 0x00FF Reserved R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 MODFEN BIDIROE SPISWAI SPC0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 0 0 0 0 0 0
PAGE 1323
Appendix G Detailed Register Map 0x0100–0x010F Flash Control Register (FTX512K4) Map (continued) Address Name 0x010C Reserved 0x010D Reserved 0x010E Reserved 0x010F Reserved R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0110–0x011B EEPROM Control Register (EETX4K) Map Address Name 0x0110 ECLKDIV 0x0111 Reserved 0x0112 Reserved 0x0113 ECNFG 0x0114 EPROT 0x0115 E
PAGE 1324
Appendix G Detailed Register Map 0x011C–0x011F Memory Map Control (S12XMMC) Map 4 of 4 Address Name 0x011C RAMWPC 0x011D RAMXGU 0x011E RAMSHL 0x011F RAMSHU Bit 7 R W R W R W R W RPWE 1 1 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 AVIE AVIF XGU6 XGU5 XGU4 XGU3 XGU2 XGU1 XGU0 SHL6 SHL5 SHL4 SHL3 SHL2 SHL1 SHL0 SHU6 SHU5 SHU4 SHU3 SHU2 SHU1 SHU0 0x0120–0x012F Interrupt Module (S12XINT) Map Address Name 0x0120 Reserved 0x0121 IVBR 0x0122 Reserved
PAGE 1325
Appendix G Detailed Register Map 0x00130–0x0137 Asynchronous Serial Interface (SCI4) Map Address Name 0x0130 SCI4BDH1 0x0131 SCI4BDL1 0x0132 SCI4CR11 0x0130 SCI4ASR12 0x0131 SCI4ACR12 0x0132 SCI4ACR22 0x0133 SCI4CR2 0x0134 SCI4SR1 0x0135 SCI4SR2 0x0136 SCI4DRH 0x0137 SCI4DRL 1 2 Bit 7 R IREN W R SBR7 W R LOOPS W R RXEDGIF W R RXEDGIE W R 0 W R TIE W R TDRE W R AMAP W R R8 W R R7 W T7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR6
PAGE 1326
Appendix G Detailed Register Map 0x0138–0x013F Asynchronous Serial Interface (SCI5) Map (continued) Address 1 2 Name 0x013D SCI5SR2 0x013E SCI5DRH 0x013F SCI5DRL Bit 7 R W R W R W AMAP R8 R7 T7 Bit 6 Bit 5 0 0 T8 R6 T6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TXPOL RXPOL BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK RAF Those registers are accessible if the AMAP bit in the SCI5SR2 register is set
PAGE 1327
Appendix G Detailed Register Map 0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map (continued) Address Name 0x0150– CAN0IDAR0– 0x0153 CAN0IDAR3 0x0154– CAN0IDMR0– 0x0157 CAN0IDMR3 0x0158– CAN0IDAR4– 0x015B CAN0IDAR7 0x015C CAN0IDMR4– – CAN0IDMR7 0x015F R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 R 0x0160– 0x016
PAGE 1328
Appendix G Detailed Register Map Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued) Address Name 0xXX0x XX10 Extended ID CANxTIDR1 Standard ID 0xXX12 0xXX13 0xXX14 – 0xXX1B 0xXX1C 0xXX1D 0xXX1E 0xXX1F R W R W Extended ID R CANxTIDR2 W Standard ID R W Extended ID R CANxTIDR3 W Standard ID R W R CANxTDSR0– CANxTDSR7 W R W R CANxTTBPR W R CANxTTSRH W R CANxTTSRL W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15 ID2 ID1 I
PAGE 1329
Appendix G Detailed Register Map 0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 2 of 3) Address Name 0x0189 CAN1TAAK 0x018A CAN1TBSEL 0x018B CAN1IDAC 0x018C Reserved 0x018D CAN1MISC 0x018E CAN1RXERR 0x018F CAN1TXERR 0x0190 CAN1IDAR0 0x0191 CAN1IDAR1 0x0192 CAN1IDAR2 0x0193 CAN1IDAR3 0x0194 CAN1IDMR0 0x0195 CAN1IDMR1 0x0196 CAN1IDMR2 0x0197 CAN1IDMR3 0x0198 CAN1IDAR4 0x0199 CAN1IDAR5 0x019A CAN1IDAR6 0x019B CAN1IDAR7 0x019C CAN1IDMR4 0x019D CAN1IDMR
PAGE 1330
Appendix G Detailed Register Map 0x0180–0x01BF Freescale Scalable CAN — MSCAN (CAN1) Map (Sheet 3 of 3) Address Name R 0x019F CAN1IDMR7 W R 0x01A0– CAN1RXFG 0x01AF W R 0x01B0– CAN1TXFG 0x01BF W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 FOREGROUND RECEIVE BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) FOREGROUND TRANSMIT BUFFER (See Detailed MSCAN Foreground Receive and Transmit Buffer Layout) 0x01C0–0x01FF Freescale Scalab
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Appendix G Detailed Register Map 0x01C0–0x01FF Freescale Scalable CAN — MSCAN (CAN2) Map (continued) Address Name 0x01D1 CAN2IDAR1 0x01D2 CAN2IDAR2 0x01D3 CAN2IDAR3 0x01D4 CAN2IDMR0 0x01D5 CAN2IDMR1 0x01D6 CAN2IDMR2 0x01D7 CAN2IDMR3 0x01D8 CAN2IDAR4 0x01D9 CAN2IDAR5 0x01DA CAN2IDAR6 0x01DB CAN2IDAR7 0x01DC CAN2IDMR4 0x01DD CAN2IDMR5 0x01DE CAN2IDMR6 0x01DF CAN2IDMR7 0x01E0– 0x01EF CAN2RXFG 0x01F0– 0x01FF CAN2TXFG R W R W R W R W R W R W R W R W R W R W R W R W R W R W R
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Appendix G Detailed Register Map 0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3) Address Name 0x0200 CAN3CTL0 0x0201 CAN3CTL1 0x0202 CAN3BTR0 0x0203 CAN3BTR1 0x0204 CAN3RFLG 0x0205 CAN3RIER 0x0206 CAN3TFLG 0x0207 CAN3TIER 0x0208 CAN3TARQ 0x0209 CAN3TAAK 0x020A CAN3TBSEL 0x020B CAN3IDAC 0x020C Reserved 0x020D Reserved 0x020E CAN3RXERR 0x020F CAN3TXERR 0x0210 CAN3IDAR0 0x0211 CAN3IDAR1 0x0212 CAN3IDAR2 0x0213 CAN3IDAR3 0x0214 CAN3IDMR0 0x0215 CAN3IDMR1 Bit 7
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Appendix G Detailed Register Map 0x0200–0x023F Freescale Scalable CAN — MSCAN (CAN3) (continued) Address Name 0x0216 CAN3IDMR2 0x0217 CAN3IDMR3 0x0218 CAN3IDAR4 0x0219 CAN3IDAR5 0x021A CAN3IDAR6 0x021B CAN3IDAR7 0x021C CAN3IDMR4 0x021D CAN3IDMR5 0x021E CAN3IDMR6 0x021F CAN3IDMR7 0x0220– 0x022F CAN3RXFG 0x0230– 0x023F CAN3TXFG R W R W R W R W R W R W R W R W R W R W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AM7 AM6 AM5 AM4
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Appendix G Detailed Register Map 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 2 of 4) Address Name 0x0248 PTS 0x0249 PTIS 0x024A DDRS 0x024B RDRS 0x024C PERS 0x024D PPSS 0x024E WOMS 0x024F Reserved 0x0250 PTM 0x0251 PTIM 0x0252 DDRM 0x0253 RDRM 0x0254 PERM 0x0255 PPSM 0x0256 WOMM 0x0257 MODRR 0x0258 PTP 0x0259 PTIP 0x025A DDRP 0x025B RDRP 0x025C PERP 0x025D PPSP 0x025E PIEP 0x025F PIFP R W R W R W R W R W R W R W R W R W R W R W R W R W R
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Appendix G Detailed Register Map 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 3 of 4) Address Name 0x0260 PTH 0x0261 PTIH 0x0262 DDRH 0x0263 RDRH 0x0264 PERH 0x0265 PPSH 0x0266 PIEH 0x0267 PIFH 0x0268 PTJ 0x0269 PTIJ 0x026A DDRJ 0x026B RDRJ 0x026C PERJ 0x026D PPSJ 0x026E PIEJ 0x026F PIFJ 0x0270 Reserved 0x0271 PT1AD0 0x0272 Reserved 0x0273 DDR1AD0 0x0274 Reserved 0x0275 RDR1AD0 0x0276 Reserved 0x0277 PER1AD0 R W R W R W R W R W R W R W R W
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Appendix G Detailed Register Map 0x0240–0x027F Port Integration Module PIM_9DX (PIM) Map (Sheet 4 of 4) Address Name 0x0278 PT0AD1 0x0279 PT1AD1 0x027A DDR0AD1 0x027B DDR1AD1 0x027C RDR0AD1 0x027D RDR1AD1 0x027E PER0AD1 0x027F PER1AD1 R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PT0AD1 23 PT0AD1 22 PT0AD1 21 PT0AD1 20 PT0AD1 19 PT0AD1 18 PT0AD1 17 PT0AD1 16 PT1AD1 15 PT1AD1 14 PT1AD1 13 PT1AD1 12 PT1AD1 11 PT1AD1 10 PT1AD1 9 PT1AD
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Appendix G Detailed Register Map 0x0280–0x02BF Freescale Scalable CAN — MSCAN (CAN4) Map (continued) Address Name 0x028D CAN4MISC 0x028E CAN4RXERR 0x028F CAN4TXERR 0x0290 CAN4IDAR0 0x0291 CAN4IDAR1 0x0292 CAN4IDAR2 0x0293 CAN4IDAR3 0x0294 CAN4IDMR0 0x0295 CAN4IDMR1 0x0296 CAN4IDMR2 0x0297 CAN4IDMR3 0x0298 CAN4IDAR4 0x0299 CAN4IDAR5 0x029A CAN4IDAR6 0x029B CAN4IDAR7 0x029C CAN4IDMR4 0x029D CAN4IDMR5 0x029E CAN4IDMR6 0x029F CAN4IDMR7 0x02A0– 0x02AF CAN4RXFG 0x02B0– 0
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Appendix G Detailed Register Map 0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map Address Name 0x02C0 ATD0CTL0 0x02C1 ATD0CTL1 0x02C2 ATD0CTL2 0x02C3 ATD0CTL3 0x02C4 ATD0CTL4 0x02C5 ATD0CTL5 0x02C6 ATD0STAT0 0x02C7 Reserved 0x02C8 ATD0TEST0 0x02C9 ATD0TEST1 0x02CA Reserved 0x02CB ATD0STAT1 0x02CC Reserved 0x02CD ATD0DIEN 0x02CE Reserved 0x02CF ATD0PTAD0 0x02D0 ATD0DR0H 0x02D1 ATD0DR0L 0x02D2 ATD0DR1H 0x02D3 ATD0DR1L 0x02D4 ATD0DR2H 0x02D5 AT
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Appendix G Detailed Register Map 0x02C0–0x02DF Analog-to-Digital Converter 10-Bit 8-Channel (ATD0) Map (continued) Address Name 0x02D6 ATD0DR3H 0x02D7 ATD0DR3L 0x02D8 ATD0DR4H 0x02D9 ATD0DR4L 0x02DA ATD0DR5H 0x02DB ATD0DR5L 0x02DC ATD0DR6H 0x02DD ATD0DR6L 0x02DE ATD0DR7H 0x02DF ATD0DR7L R W R W R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bi
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Appendix G Detailed Register Map 0x02F8–0x02FF Reserved Address 0x02F8– 0x02FF Name Reserved R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address 0x0300 0x0301 0x0302 0x0303 0x0304 0x0305 0x0306 0x0307 0x0308 0x0309 0x030A 0x030B 0x030C 0x030D 0x030E 0x030F 0x0310 0x0311 0x0312 0x0313 Name Bit 7 R PWME7 W R PWMPOL PPOL7 W R PWMCLK PCLK7 W R 0 PWMPRCLK W R PWMCAE CAE7 W R PWMCTL CON67 W R 0 PWMTST Test
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Appendix G Detailed Register Map 0x0300–0x0327 Pulse Width Modulator 8-Bit 8-Channel (PWM) Map Address Name 0x0314 PWMPER0 0x0315 PWMPER1 0x0316 PWMPER2 0x0317 PWMPER3 0x0318 PWMPER4 0x0319 PWMPER5 0x031A PWMPER6 0x031B PWMPER7 0x031C PWMDTY0 0x031D PWMDTY1 0x031E PWMDTY2 0x031F PWMDTY3 0x0320 PWMDTY4 0x0321 PWMDTY5 0x0322 PWMDTY6 0x0323 PWMDTY7 0x0324 PWMSDN 0x0325 Reserved 0x0326 Reserved 0x0327 Reserved R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
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Appendix G Detailed Register Map 0x0328–0x033F Reserved Address 0x0328– 0x033F Name Reserved R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 PFLT3 0 PFLT2 0 PFLMT1 0 PFLT1 0 PFLMT0 0 PFLT0 PCE3 PCE2 PCE1 PCE0 PMUX3 PMUX2 PMUX1 PMUX0 PINTE3 PINTE2 PINTE1 PINTE0 PTF3 PTF2 PTF1 PTF0 0x0340–0x0367 Periodic Interrupt Timer (PIT) Map Address Name 0x0340 PITCFLMT 0x0341 PITFLT 0x0342 PITCE 0x0343 PITM
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Appendix G Detailed Register Map 0x0340–0x0367 Periodic Interrupt Timer (PIT) Map (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 R 0x0354 PITLD3 (hi) PLD15 W R 0x0355 PITLD3 (lo) PLD
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Appendix G Detailed Register Map 0x0380–0x03BF XGATE Map (Sheet 2 of 3) Address Name 0x038D XGIF 0x038E XGIF 0x038F XGIF 0x0390 XGIF 0x0391 XGIF 0x0392 XGIF 0x0393 XGIF 0x0394 XGIF 0x0395 XGIF 0x0396 XGIF 0x0397 XGIF 0x0398 XGSWT (hi) 0x0399 XGSWT (lo) 0x039A XGSEM (hi) 0x039B XGSEM (lo) 0x039C Reserved 0x039D XGCCR 0x039E XGPC (hi) 0x039F XGPC (lo) 0x03A0 Reserved 0x03A1 Reserved 0x03A2 XGR1 (hi) 0x03A3 XGR1 (lo) R W R W R W R W R W R W R W R W R W R W R W R
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Appendix G Detailed Register Map 0x0380–0x03BF XGATE Map (Sheet 3 of 3) Address Name 0x03A4 XGR2 (hi) 0x03A5 XGR2 (lo) 0x03A6 XGR3 (hi) 0x03A7 XGR3 (lo) 0x03A8 XGR4 (hi) 0x03A9 XGR4 (lo) 0x03AA XGR5 (hi) 0x03AB XGR5(lo) 0x03AC XGR6 (hi) 0x03AD XGR6 (lo) 0x03AE XGR7 (hi) 0x03AF XGR7 (lo) 0x03B0– 0x03BF Reserved Bit 7 R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XGR2[15:8] XGR2[7:0] XGR3[15:8] XGR3[7:0] XGR4[15:8] XGR4[7:0]
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Appendix G Detailed Register Map MC9S12XDP512 Data Sheet, Rev. 2.
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