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K10P144M100SF2

K10 Sub-Family Data Sheet

Supports the following:

MK10DX128ZVLQ10,

MK10DX128ZVMD10,

MK10DX256ZVLQ10,

MK10DX256ZVMD10,

MK10DN512ZVLQ10,

MK10DN512ZVMD10

Features

•

Operating Characteristics

–

Voltage range: 1.71 to 3.6 V

– Flash write voltage range: 1.71 to 3.6 V

– Temperature range (ambient): -40 to 105°C

•

Performance

– Up to 100 MHz ARM Cortex-M4 core with DSP

instructions delivering 1.25 Dhrystone MIPS per

MHz

•

Memories and memory interfaces

– Up to 512 KB program flash memory on non-

FlexMemory devices

– Up to 128 KB RAM

– Serial programming interface (EzPort)

– FlexBus external bus interface

•

Clocks

– 3 to 32 MHz crystal oscillator

– 32 kHz crystal oscillator

– Multi-purpose clock generator

•

System peripherals

– Multiple low-power modes to provide power

optimization based on application requirements

– Memory protection unit with multi-master

protection

– 16-channel DMA controller, supporting up to 63

request sources

– External watchdog monitor

– Software watchdog

– Low-leakage wakeup unit

•

Security and integrity modules

– Hardware CRC module to support fast cyclic

redundancy checks

– 128-bit unique identification (ID) number per chip

•

Human-machine interface

– Low-power hardware touch sensor interface (TSI)

– General-purpose input/output

•

Analog modules

– Two 16-bit SAR ADCs

– Programmable gain amplifier (PGA) (up to x64)

integrated into each ADC

– Two 12-bit DACs

– Three analog comparators (CMP) containing a 6-bit

DAC and programmable reference input

– Voltage reference

•

Timers

– Programmable delay block

– Eight-channel motor control/general purpose/PWM

timer

– Two 2-channel quadrature decoder/general purpose

timers

– Periodic interrupt timers

– 16-bit low-power timer

– Carrier modulator transmitter

– Real-time clock

•

Communication interfaces

– Two Controller Area Network (CAN) modules

– Three SPI modules

– Two I2C modules

– Six UART modules

– Secure Digital host controller (SDHC)

– I2S module

Freescale Semiconductor

Document Number: K10P144M100SF2

Data Sheet: Technical Data

Rev. 7, 02/2013

Freescale reserves the right to change the detail specifications as may be

required to permit improvements in the design of its products.

Summary of content (72 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data K10 Sub-Family Data Sheet Document Number: K10P144M100SF2 Rev. 7, 02/2013 K10P144M100SF2 Supports the following: MK10DX128ZVLQ10, MK10DX128ZVMD10, MK10DX256ZVLQ10, MK10DX256ZVMD10, MK10DN512ZVLQ10, MK10DN512ZVMD10 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C • Performance – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.
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Table of Contents 1 Ordering parts...........................................................................3 5.4.2 Thermal attributes.................................................21 1.1 Determining valid orderable parts......................................3 6 Peripheral operating requirements and behaviors....................22 2 Part identification......................................................................3 6.1 Core modules.............................................................
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Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK10 and MK10 . 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.
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Terminology and guidelines Field Description Values FFF Program flash memory size • • • • • • • 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB 2M0 = 2 MB R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK
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Terminology and guidelines 3.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min.
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Terminology and guidelines 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. –0.3 Max. Unit 1.2 V 3.
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Terminology and guidelines 3.6 Relationship between ratings and operating requirements e Op ing rat r ( ng ati in. t (m ) n. mi rat e Op ing ) t (m e ir qu re n me ing rat e Op ax .) e ir qu re n me ing rat e Op ng ati ax (m .
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Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.
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Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 Solder temperature, leaded — 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.
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General Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 185 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V Maximum current single pin limit (applies to all digital pins) –25 25 mA VDD – 0.3 VDD + 0.3 V –0.3 3.8 V ID VDDA Analog supply voltage VBAT RTC battery supply voltage 1.
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General 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V 1.71 3.6 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.
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General 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.
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General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Min. Typ.1 Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA VDD – 0.5 — — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA VDD – 0.5 — — V • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA VDD – 0.5 — — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA VDD – 0.
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General Table 4. Voltage and current operating behaviors (continued) Symbol IIND Description Min. Max. Unit Input leakage current, digital pins • VDD < VIN < 5.5 V ZIND Typ.1 Notes 4, 5 — 1 50 μA Input impedance examples, digital pins 4, 7 • VDD = 3.6 V — — 48 kΩ • VDD = 3.0 V — — 55 kΩ • VDD = 2.5 V — — 57 kΩ • VDD = 1.7 V — — 85 kΩ RPU Internal pullup resistors 20 35 50 kΩ 8 RPD Internal pulldown resistors 20 35 50 kΩ 9 1. 2. 3. 4. 5. 6. 7.
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General Table 5. Power mode transition operating behaviors Symbol tPOR Description Min. Max. After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VDD slew rate ≥ 5.7 kV/s • VDD slew rate < 5.7 kV/s • VLLS1 → RUN • VLLS2 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN Unit Notes μs 1 — 300 — 1.7 V / (VDD slew rate) — 134 μs — 96 μs — 96 μs — 6.2 μs — 5.9 μs — 5.
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General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. Typ. Max. Unit Notes IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — N/A — mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled — N/A — mA 8 IDD_STOP Stop mode current at 3.0 V • @ –40 to 25°C — 0.59 1.4 mA • @ 70°C — 2.26 7.9 mA • @ 105°C — 5.94 19.
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General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. IDD_VBAT Average current when CPU is not accessing RTC registers Typ. Max. Unit Notes 10 • @ 1.8V • @ –40 to 25°C • @ 70°C • @ 105°C — 0.71 0.81 μA — 1.01 1.3 μA — 2.82 4.3 μA — 0.84 0.94 μA — 1.17 1.5 μA — 3.16 4.6 μA • @ 3.0V • @ –40 to 25°C • @ 70°C • @ 105°C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
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General Figure 2. Run mode supply current vs. core frequency 5.2.6 EMC radiated emissions operating behaviors Table 7. EMC radiated emissions operating behaviors as measured on 144LQFP and 144MAPBGA packages Symbol Description Frequency band (MHz) 144LQFP 144MAPBGA Unit Notes 1,2 VRE1 Radiated emissions voltage, band 1 0.
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General 2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 5.2.7 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.8 Capacitance attributes Table 8.
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General Table 10. General switching specifications Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.
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General 5.4.1 Thermal operating requirements Table 11. Thermal operating requirements Symbol Description Min. Max. Unit TJ Die junction temperature –40 125 °C TA Ambient temperature –40 105 °C 5.4.
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Peripheral operating requirements and behaviors 2. 3. 4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate.
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Peripheral operating requirements and behaviors 6.1.2 JTAG electricals Table 13. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.
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Peripheral operating requirements and behaviors Table 14. JTAG full voltage range electricals (continued) Symbol J3 Description Min. Max. Unit • Boundary Scan 50 — ns • JTAG and CJTAG 25 — ns • Serial Wire Debug 12.
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Peripheral operating requirements and behaviors TCLK J5 Data inputs J6 Input data valid J7 Data outputs Output data valid J8 Data outputs J7 Data outputs Output data valid Figure 6. Boundary scan (JTAG) timing TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 7. Test Access Port timing K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors TCLK J14 J13 TRST Figure 8. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules 6.3.1 MCG specifications Table 15. MCG specifications Symbol Description Min. Typ. Max. Unit — 32.768 — kHz 31.25 — 38.2 kHz — ± 0.3 ± 0.6 %fdco 1 Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70°C — ± 1.5 ± 4.
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Peripheral operating requirements and behaviors Table 15. MCG specifications (continued) Symbol fdco Description DCO output frequency range Low range (DRS=00) Min. Typ. Max. Unit Notes 20 20.97 25 MHz 2, 3 40 41.94 50 MHz 60 62.91 75 MHz 80 83.89 100 MHz — 23.99 — MHz — 47.97 — MHz — 71.99 — MHz — 95.98 — MHz — 180 — — 150 — — — 1 ms 48.0 — 100 MHz — 1060 — µA — 600 — µA 2.0 — 4.
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Peripheral operating requirements and behaviors 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4.
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Peripheral operating requirements and behaviors Table 16. Oscillator DC electrical specifications (continued) Symbol RF RS Description Min. Typ. Max.
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Peripheral operating requirements and behaviors Table 17. Oscillator frequency specifications (continued) Symbol Description Min. Typ. Max.
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Peripheral operating requirements and behaviors 6.3.3.2 Symbol fosc_lo tstart fec_extal32 32 kHz oscillator frequency specifications Table 19. 32 kHz oscillator frequency specifications Description Min. Typ. Max. Unit Oscillator crystal — 32.768 — kHz Crystal start-up time — 1000 — ms 1 Externally provided input clock frequency — 32.768 — kHz 2 700 — VBAT mV 2, 3 vec_extal32 Externally provided input clock amplitude Notes 1.
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Peripheral operating requirements and behaviors Table 21. Flash command timing specifications (continued) Symbol Description Min. Typ. Max.
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Peripheral operating requirements and behaviors Table 23. NVM reliability specifications (continued) Min. Typ.1 Max. Unit tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles Symbol Description Notes 2 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile.
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Peripheral operating requirements and behaviors EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 9. EzPort Timing Diagram 6.4.3 Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency.
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Peripheral operating requirements and behaviors 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 26. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Frequency of operation Notes — FB_CLK MHz 1/FB_CLK — ns Address, data, and control output valid — 13.5 ns 1 FB3 Address, data, and control output hold 0 — ns 1 FB4 Data and FB_TA input setup 13.7 — ns 2 FB5 Data and FB_TA input hold 0.
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Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB5 FB_A[Y] Address FB4 FB2 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 10. FlexBus read timing diagram K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. 36 Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] Address FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA AA=0 FB_TSIZ[1:0] TSIZ Figure 11. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and ADCx_DM3. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 29 and Table 30.
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Peripheral operating requirements and behaviors Table 27. 16-bit ADC operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate 16-bit mode Min. Typ.1 Max. Unit Notes 5 No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2.
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Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol fADACK Description ADC asynchronous clock source Sample Time TUE DNL INL EFS Conditions1 Min. Typ.2 Max. Unit Notes • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.
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Peripheral operating requirements and behaviors Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description EIL Input leakage error Conditions1 Min. Typ.2 Max. IIn × RAS Unit Notes mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C Temp sensor voltage 25 °C 706 716 726 mV 1.
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Peripheral operating requirements and behaviors Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 29. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.
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Peripheral operating requirements and behaviors Table 29. 16-bit ADC with PGA operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate ≤ 13 bit modes Min. Typ.1 Max. Unit Notes 18.484 — 450 Ksps 7 37.037 — 250 Ksps 8 No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 16 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume VDDA = 3.
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Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA characteristics (continued) Symbol G BW Description Gain4 Input signal bandwidth PSRR Power supply rejection ratio CMRR Common mode rejection ratio Min. Typ.1 Max. • PGAG=0 0.95 1 1.05 • PGAG=1 1.9 2 2.1 • PGAG=2 3.8 4 4.2 • PGAG=3 7.6 8 8.4 • PGAG=4 15.2 16 16.6 • PGAG=5 30.0 31.6 33.2 • PGAG=6 58.8 63.3 67.
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Peripheral operating requirements and behaviors Table 30. 16-bit ADC with PGA characteristics (continued) Symbol Description ENOB Effective number of bits SINAD Min. Typ.1 Max. Unit Notes • Gain=1, Average=4 11.6 13.4 — bits • Gain=64, Average=4 7.2 9.6 — bits • Gain=1, Average=32 12.8 14.5 — bits 16-bit differential mode,fin=100Hz • Gain=2, Average=32 11.0 14.3 — bits • Gain=4, Average=32 7.9 13.8 — bits • Gain=8, Average=32 7.3 13.
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Peripheral operating requirements and behaviors Table 31. Comparator and 6-bit DAC electrical specifications (continued) Symbol tDLS IDAC6b Description Min. Typ. Max. Unit Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1.
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Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 Symbol 12-bit DAC operating requirements Table 32. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.
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Peripheral operating requirements and behaviors 6.6.3.2 Symbol 12-bit DAC operating behaviors Table 33. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.
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Peripheral operating requirements and behaviors Figure 17. Typical INL error vs. digital code K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013. Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors Figure 18. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 34. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device °C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference.
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Peripheral operating requirements and behaviors Table 35. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V Vout Voltage reference output — factory trim 1.1584 — 1.2376 V Vstep Voltage reference trim step — 0.
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Peripheral operating requirements and behaviors 6.8.1 CAN switching specifications See General switching specifications. 6.8.2 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes.
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Peripheral operating requirements and behaviors Table 39. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V 12.
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Peripheral operating requirements and behaviors Table 40. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 4 — ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 4 — ns 3 DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns DS7 DSPI_SIN to DSPI_SCK input setup 20.
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Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Last data Data DS14 First data Data Last data Figure 22. DSPI classic SPI timing — slave mode 6.8.4 Inter-Integrated Circuit Interface (I2C) timing Table 42. I 2C timing Characteristic Symbol Standard Mode Fast Mode Unit Minimum Maximum Minimum Maximum SCL Clock Frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition.
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Peripheral operating requirements and behaviors 6. Cb = total capacitance of the one bus line in pF. SDA tf tLOW tSU; DAT tr tf tHD; STA tr tSP tBUF SCL S tHD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 23. Timing definition for fast and standard mode devices on the I2C bus 6.8.5 UART switching specifications See General switching specifications. 6.8.
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Peripheral operating requirements and behaviors SD3 SD2 SD1 SDHC_CLK SD6 Output SDHC_CMD Output SDHC_DAT[3:0] SD7 SD8 Input SDHC_CMD Input SDHC_DAT[3:0] Figure 24. SDHC timing 6.8.7 I2S switching specifications This section provides the AC timings for the I2S in master (clocks driven) and slave modes (clocks input). All timings are given for non-inverted serial clock polarity (TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0, RCR[RFSI] = 0).
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Peripheral operating requirements and behaviors S1 S2 S2 I2S_MCLK (output) S3 I2S_BCLK (output) S4 S4 S6 S5 I2S_FS (output) S10 S9 I2S_FS (input) S7 S8 S7 S8 I2S_TXD S9 S10 I2S_RXD Figure 25. I2S timing — master mode Table 45. I2S slave mode timing (limited voltage range) Num Description Min. Max. Unit Operating voltage 2.7 3.
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Peripheral operating requirements and behaviors S11 S12 I2S_BCLK (input) S12 S15 S16 I2S_FS (output) S13 S14 I2S_FS (input) S15 S16 S15 S16 I2S_TXD S17 S18 I2S_RXD Figure 26. I2S timing — slave modes Table 46. I2S master mode timing (full voltage range) Num Description Min. Max. Unit Operating voltage 1.71 3.
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Peripheral operating requirements and behaviors 6.9 Human-machine interfaces (HMI) 6.9.1 TSI electrical specifications Table 48. TSI electrical specifications Symbol Description Min. Typ. Max. Unit VDDTSI Operating voltage 1.71 — 3.6 V CELE Notes Target electrode capacitance range 1 20 500 pF 1 fREFmax Reference oscillator frequency — 5.5 12.7 MHz 2 fELEmax Electrode oscillator frequency — 0.5 4.0 MHz 3 Internal reference capacitor 0.5 1 1.
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Dimensions 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 144-pin LQFP 98ASS23177W 144-pin MAPBGA 98ASA00222D 8 Pinout 8.
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Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 7 E3 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3 8 E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2 9 E1 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_ I2S0_MCLK b 10 F4 PTE7 DISABLED PTE7 UART3_RTS_ I2S0_RXD b 11 F3 PTE8 DISABLED PTE8 UART5_TX I2S0_RX_FS 12 F2 PTE9 DISABLED PTE9 UART5_RX I2S0_RX_ BCLK 13 F1 PTE10 DISABLED PTE10 UART5_CTS_ I2S0_TXD b 14 G
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Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 35 K3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 36 J3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 37 M3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 38 L3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23
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Pinout 144 144 LQFP MAP BGA Pin Name Default 60 K8 PTA8 ADC0_SE11 61 L8 PTA9 62 M9 63 ALT0 ADC0_SE11 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 PTA8 FTM1_CH0 FTM1_QD_ PHA TRACE_D2 DISABLED PTA9 FTM1_CH1 FTM1_QD_ PHB TRACE_D1 PTA10 DISABLED PTA10 FTM2_CH0 FTM2_QD_ PHA TRACE_D0 L9 PTA11 DISABLED PTA11 FTM2_CH1 FTM2_QD_ PHB 64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD FTM1_QD_ PHA 65 J9 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX
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Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 89 F10 PTB8 PTB8 90 F9 PTB9 PTB9 91 E12 PTB10 ADC1_SE14 ADC1_SE14 92 E11 PTB11 ADC1_SE15 ADC1_SE15 93 H7 VSS VSS VSS 94 F5 VDD VDD VDD 95 E10 PTB16 TSI0_CH9 96 E9 PTB17 97 D12 PTB18 98 D11 PTB19 99 D10 100 101 102 ALT2 ALT3 ALT4 ALT5 ALT6 UART3_RTS_ b FB_AD21 SPI1_PCS1 UART3_CTS_ b FB_AD20 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2 TSI0_CH9 PT
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Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 117 A7 PTC12 PTC12 UART4_RTS_ b FB_AD27 118 D6 PTC13 PTC13 UART4_CTS_ b FB_AD26 119 C6 PTC14 PTC14 UART4_RX FB_AD25 120 B6 PTC15 PTC15 UART4_TX FB_AD24 121 — VSS VSS VSS 122 — VDD VDD VDD 123 A6 PTC16 PTC16 CAN1_RX UART3_RX FB_CS5_b/ FB_TSIZ1/ FB_BE23_16_ b 124 D5 PTC17 PTC17 CAN1_TX UART3_TX FB_CS4_b/ FB_TSIZ0/ FB_BE31_24_ b 125 C5 PTC18 PTC18 UART3_RTS_ b FB_TBST_b
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Pinout 144 144 LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 ALT7 EzPort 8.2 K10 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K10 Sub-Family Data Sheet Data Sheet, Rev.
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PTD15 PTD14 PTD13 PTD12 PTD11 PTD10 PTD9 PTD8 PTD7 VDD VSS PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 PTC19 PTC18 PTC17 PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6 PTC5 PTC4 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Pinout PTE0 1 108 VDD PTE1 2 107 VSS PTE2 3 106 PTC3 PTE3 4 105 PTC2 VDD 5 104 PTC1
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Revision History 1 2 3 4 5 6 7 8 9 10 11 12 A PTD7 PTD6 PTD5 PTD4 PTD0 PTC16 PTC12 PTC8 PTC4 NC PTC3 PTC2 A B PTD12 PTD11 PTD10 PTD3 PTC19 PTC15 PTC11 PTC7 PTD9 NC PTC1 PTC0 B C PTD15 PTD14 PTD13 PTD2 PTC18 PTC14 PTC10 PTC6 PTD8 NC PTB23 PTB22 C D PTE2 PTE1 PTE0 PTD1 PTC17 PTC13 PTC9 PTC5 PTB21 PTB20 PTB19 PTB18 D E PTE6 PTE5 PTE4 PTE3 VDD VDD VDD VDD PTB17 PTB16 PTB11 PTB10 E F PTE10 PTE9 PTE8 PTE7 VDD VSS VSS VDD PT
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Revision History Table 49. Revision History (continued) Rev. No. Date Substantial Changes 2 3/2011 Many updates throughout 3 3/2011 Added sections that were inadvertently removed in previous revision 4 3/2011 Reworded IIC footnote in "Voltage and Current Operating Requirements" table. Added paragraph to "Peripheral operating requirements and behaviors" section. Added "JTAG full voltage range electricals" table to the "JTAG electricals" section.
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Revision History Table 49. Revision History (continued) Rev. No. Date 6 01/2012 Substantial Changes • • • • • • • • • 7 02/2013 Added AC electrical specifications. Replaced TBDs with silicon data throughout. In "Power mode transition operating behaviors" table, removed entry times. Updated "EMC radiated emissions operating behaviors" to remove SAE level and also added data for 144LQFP. Clarified "EP7" in "EzPort switching specifications" table and "EzPort Timing Diagram". Added "ENOB vs.
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