Freescale Semiconductor Product Brief Document Number:K10PB Rev. 11, 08/2012 K10 Family Product Brief Supports all K10 devices Contents 1 Kinetis Portfolio 1 Kinetis Portfolio........................................................1 Kinetis is the most scalable portfolio of low power, mixedsignal ARM®Cortex™-M4 MCUs in the industry. Phase 1 of the portfolio consists of five MCU families with over 200 pin-, peripheral- and software-compatible devices.
Kinetis Portfolio Family Program Flash Packages K70 Family 512KB-1MB 196-256pin K6x Family 256KB-1MB 100-256pin K5x Family 128-512KB 64-144pin K40 Family 64-512KB 64-144pin K30 Family 64-512KB 64-144pin K20 Family 32KB-1MB 32-144pin K10 Family 32KB-1MB 32-144pin Low power Mixed signal Encryption and Tamper Detect Key Features USB Segment LCD Operational & transimpedance amplifiers DDR Ethernet Graphic LCD Figure 1.
K10 Family Introduction • • • • • • • EEPROM erase/write times an order of magnitude faster than traditional EEPROM • Multi-function external bus interface capable of interfacing to external memories, gate-array logic Mixed-signal analog: • Fast, high precision 16-bit ADCs, 12-bit DACs, high speed comparators and an internal voltage reference.
K10 Block Diagram Kinetis K10 Family ARM ® Cortex™-M4 Core Debug interfaces DSP Interrupt controller System Memories and Memory Interfaces Clocks Internal and external watchdogs Program flash DMA FlexMemory Frequencylocked loop Low-leakage wakeup Serial programming interface Low/high frequency oscillators RAM Phaselocked loop Internal reference clocks Security Communication Interfaces Analog Timers 16-bit ADC Timers x3 (16ch) I C x2 Random number generator Analog comparator x2 Ca
Features 4 Features 4.1 Common features among the K10 family All devices within the K10 family features the following at a minimum: Table 1. Common features among all K10 devices Operating characteristics • • • • Voltage range 1.71V - 3.6V Flash memory programming down to 1.
Features Table 1.
Features Table 2. K10 family summary (continued) Flash (KB) FlexNVM (KB) EEPROM/ FlexRAM (KB) 32 QFN (5x5) 48 QFN (7x7) 48 LQFP (7x7) 64 BGA (5x5) 64 LQFP (10x10) 80 LQFP (12x12) 81 BGA (8x8) 100 LQFP (14x14) 120 WLCSP (5.3x5.
Features 4.2.1 Programmable Trade-Off FlexMemory lets you fully configure the way FlexNVM and FlexRAM blocks are used to provide the best balance of memory resources for their application. The user can configure several parameters, including EEPROM size, endurance, write size, and the size of additional program/data flash. In addition to this flexibility, FlexMemory provides superior EEPROM performance, endurance, and low-voltage operation when compared to traditional EEPROM solutions.
Features Field Description Values K## Kinetis family • K10 • K11 • K12 A Key attribute • D = Cortex-M4 w/ DSP • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only • X = Program flash and FlexMemory FFF Program flash memory size • • • • • • R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7
Features 4.4.1 K10 family features (50MHz Performance) 1 MK10DX64VFT5(R) MK10DN64VFT5(R) MK10DX32VFT5(R) MK10DN32VFT5(R) MK10DX128VLF5(R) MK10DN128VLF5(R) MK10DX64VLF5(R) MK10DN64VLF5(R) MK10DX32VLF5(R) MK10DN32VLF5(R) MK10DX128VFM5(R) MK10DN128VFM5(R) MK10DX64VFM5(R) MK10DN64VFM5(R) MK10DX32VFM5(R) MC Partnumber MK10DN32VFM5(R) Table 3.
Features NMI MK10DN64VFM5(R) MK10DX64VFM5(R) MK10DN128VFM5(R) MK10DX128VFM5(R) MK10DN32VLF5(R) MK10DX32VLF5(R) MK10DN64VLF5(R) MK10DX64VLF5(R) MK10DN128VLF5(R) MK10DX128VLF5(R) MK10DN32VFT5(R) MK10DX32VFT5(R) MK10DN64VFT5(R) MK10DX64VFT5(R) Trace MK10DX32VFM5(R) MC Partnumber MK10DN32VFM5(R) Table 3.
Features ADC SE MK10DX64VFT5(R) MK10DN64VFT5(R) MK10DX32VFT5(R) MK10DN32VFT5(R) MK10DX128VLF5(R) MK10DN128VLF5(R) MK10DX64VLF5(R) MK10DN64VLF5(R) MK10DX32VLF5(R) MK10DN32VLF5(R) MK10DX128VFM5(R) MK10DN128VFM5(R) MK10DX64VFM5(R) MK10DN64VFM5(R) MK10DX32VFM5(R) MC Partnumber MK10DN32VFM5(R) Table 3.
Features MC Partnumber MK10DN32VFM5(R) MK10DX32VFM5(R) MK10DN64VFM5(R) MK10DX64VFM5(R) MK10DN128VFM5(R) MK10DX128VFM5(R) MK10DN32VLF5(R) MK10DX32VLF5(R) MK10DN64VLF5(R) MK10DX64VLF5(R) MK10DN128VLF5(R) MK10DX128VLF5(R) MK10DN32VFT5(R) MK10DX32VFT5(R) MK10DN64VFT5(R) MK10DX64VFT5(R) Table 3.
Features 4.4.
Features Trace MK10DX128VMP5(R) MK10DN128VMP5(R) MK10DX64VMP5(R) MK10DN64VMP5(R) MK10DX32VMP5(R) MK10DN32VMP5(R) MK10DX128VLH5(R) MK10DN128VLH5(R) MK10DX64VLH5(R) MK10DN64VLH5(R) MK10DX32VLH5(R) MK10DN32VLH5(R) MK10DX128VFT5(R) MC Partnumber MK10DN128VFT5(R) Table 4.
Features MK10DN128VFT5(R) MK10DX128VFT5(R) MK10DN32VLH5(R) MK10DX32VLH5(R) MK10DN64VLH5(R) MK10DX64VLH5(R) MK10DN128VLH5(R) MK10DX128VLH5(R) MK10DN32VMP5(R) MK10DX32VMP5(R) MK10DN64VMP5(R) MK10DX64VMP5(R) MK10DN128VMP5(R) MK10DX128VMP5(R) Table 4.
Features MC Partnumber MK10DN128VFT5(R) MK10DX128VFT5(R) MK10DN32VLH5(R) MK10DX32VLH5(R) MK10DN64VLH5(R) MK10DX64VLH5(R) MK10DN128VLH5(R) MK10DX128VLH5(R) MK10DN32VMP5(R) MK10DX32VMP5(R) MK10DN64VMP5(R) MK10DX64VMP5(R) MK10DN128VMP5(R) MK10DX128VMP5(R) Table 4.
Features MK11DN512VMC5(R) LQFP MK11DX256VMC5(R) LQFP MK11DX128VMC5(R) MK11DX256VLK5(R) Package MK11DN512VLK5(R) MC Partnumber MK11DX128VLK5(R) Table 5.
Features MC Partnumber MK11DX128VLK5(R) MK11DX256VLK5(R) MK11DN512VLK5(R) MK11DX128VMC5(R) MK11DX256VMC5(R) MK11DN512VMC5(R) Table 5.
Features MC Partnumber MK11DX128VLK5(R) MK11DX256VLK5(R) MK11DN512VLK5(R) MK11DX128VMC5(R) MK11DX256VMC5(R) MK11DN512VMC5(R) Table 5.
Features 4.4.
Features MC Partnumber MK12DX128VLF5(R) MK12DX256VLF5(R) MK12DX128VLH5(R) MK12DX256VLH5(R) MK12DN512VLH5(R) MK12DX128VLK5(R) MK12DX256VLK5(R) MK12DN512VLK5(R) MK12DX128VMC5(R) MK12DX256VMC5(R) MK12DN512VMC5(R) Table 6.
Features MK12DX256VMC5(R) MK12DN512VMC5(R) YES MK12DX128VMC5(R) YES MK12DN512VLK5(R) MK12DX256VLH5(R) YES MK12DX256VLK5(R) MK12DX128VLH5(R) YES MK12DX128VLK5(R) MK12DX256VLF5(R) Vref MK12DN512VLH5(R) MC Partnumber MK12DX128VLF5(R) Table 6.
Features MC Partnumber MK12DX128VLF5(R) MK12DX256VLF5(R) MK12DX128VLH5(R) MK12DX256VLH5(R) MK12DN512VLH5(R) MK12DX128VLK5(R) MK12DX256VLK5(R) MK12DN512VLK5(R) MK12DX128VMC5(R) MK12DX256VMC5(R) MK12DN512VMC5(R) Table 6.
Features MC Partnumber MK10DX64VLH7(R) MK10DX128VLH7(R) MK10DX256VLH7(R) MK10DX64VLK7(R) MK10DX128VLK7(R) MK10DX256VLK7(R) MK10DX128VLL7(R) MK10DX256VLL7(R) MK10DX64VMC7(R) MK10DX128VMC7(R) MK10DX256VMC7(R) Table 7.
Features MC Partnumber MK10DX64VLH7(R) MK10DX128VLH7(R) MK10DX256VLH7(R) MK10DX64VLK7(R) MK10DX128VLK7(R) MK10DX256VLK7(R) MK10DX128VLL7(R) MK10DX256VLL7(R) MK10DX64VMC7(R) MK10DX128VMC7(R) MK10DX256VMC7(R) Table 7.
Features MC Partnumber MK10DX64VLH7(R) MK10DX128VLH7(R) MK10DX256VLH7(R) MK10DX64VLK7(R) MK10DX128VLK7(R) MK10DX256VLK7(R) MK10DX128VLL7(R) MK10DX256VLL7(R) MK10DX64VMC7(R) MK10DX128VMC7(R) MK10DX256VMC7(R) Table 7.
Features 4.4.6 K10 family features (100MHz Performance) MK10DN512VMD10(R) MK10DN512VLQ10(R) MK10DN512VMC10(R) MK10DN512VLL10(R) MK10DN512VLK10(R) MK10DX256VMD10(R) MK10DX256VLQ10(R) MK10DX128VMD10(R) MC Partnumber MK10DX128VLQ10(R) Table 8.
Features MK10DN512VLL10(R) MK10DN512VMC10(R) MK10DN512VLQ10(R) MK10DN512VMD10(R) YES YES YES YES YES YES YES YES YES Hardware Watchdog YES YES YES YES YES YES YES YES YES PMC YES YES YES YES YES YES YES YES YES MPU YES YES YES YES YES YES YES YES YES DMA 16ch 16ch 16ch 16ch 16ch 16ch 16ch 16ch 16ch MK10DX256VMD10(R) Software Watchdog MC Partnumber MK10DX128VMD10(R) MK10DN512VLK10(R) MK10DX256VLQ10(R) MK10DX128VLQ10(R) Table 8.
Features MC Partnumber MK10DX128VLQ10(R) MK10DX128VMD10(R) MK10DX256VLQ10(R) MK10DX256VMD10(R) MK10DN512VLK10(R) MK10DN512VLL10(R) MK10DN512VMC10(R) MK10DN512VLQ10(R) MK10DN512VMD10(R) Table 8.
Features MC Partnumber MK10DX128VLQ10(R) MK10DX128VMD10(R) MK10DX256VLQ10(R) MK10DX256VMD10(R) MK10DN512VLK10(R) MK10DN512VLL10(R) MK10DN512VMC10(R) MK10DN512VLQ10(R) MK10DN512VMD10(R) Table 8.
Features MK10FN1M0VMD12(R) MC Partnumber MK10FX512VMD12(R) MK10FX512VLQ12(R) MK10FN1M0VLQ12(R) Table 9.
Features MK10FX512VLQ12(R) MK10FN1M0VLQ12(R) MK10FX512VMD12(R) MK10FN1M0VMD12(R) Table 9.
Features MC Partnumber MK10FX512VLQ12(R) MK10FN1M0VLQ12(R) MK10FX512VMD12(R) MK10FN1M0VMD12(R) Table 9.
Core modules 4.5.1 Core modules 4.5.1.1 • • • • • • • • • • Supports up to 120 MHz frequency with 1.
System modules • CoreSight™ Embedded Trace Buffer (ETB) is a memory-mapped buffer to store trace data. Allows reconstruction of program flow with standard JTAG tools. • Test Port Interface Unit (TPIU) acts as a bridge between ITM or ETM and an off-chip Trace Port Analyzer • Flash Patch and Breakpoints (FPB) implements hardware breakpoints and patches code and data from code space to system space 4.5.2 System modules 4.5.2.
Memories and Memory Interfaces 4.5.2.5 External Watchdog Monitor (EWM) • Independent 1 kHz LPO clock source • Output signal to gate an external circuit which is controlled by CPU service or external input 4.5.2.6 System Clocks • Frequency-locked loop (FLL) • Digitally-controlled oscillator (DCO) • DCO frequency range is programmable • Option to program DCO frequency for a 32,768 Hz external reference clock source • Internal or external reference clock can be used to control the FLL • 0.
Security and Integrity • Flexmemory block contains up to 512KB FlexNVM and 16KB FlexRAM with up to 16KB EEPROM capability • Up to 128KB SRAM • 16KB cache • Security circuitry to prevent unauthorized access to RAM and flash contents 4.5.3.
Analog 4.5.4.3 Random Number Generator (RNG) • Supports the key generation algorithm defined in the Digital Signature Standard • http://www.itl.nist.gov/fipspubs/fip186.htm • Integrated entropy sources capable of providing the PRNG with entropy for its seed 4.5.4.
Timers 4.5.5.2 High-Speed Analog Comparator (CMP) • Updated to allow the Analog input mux to be used as a pass through mux http://designpdm.freescale.
Timers • One trigger output for ADC hardware trigger and up to eight pre-trigger outputs for ADC trigger select per PDB channel • Trigger outputs can be enabled or disabled independently.
Communication interfaces • Selectable clock for prescaler/glitch filter • 1 kHz internal LPO • External low power crystal oscillator • Internal reference clock (not available in low leakage power modes) • Secondary external reference clock (for example, 32 kHz crystal) • Configurable glitch filter or prescaler • Interrupt generated on timer compare • Hardware trigger generated on timer compare 4.5.6.
Communication interfaces 4.5.7.
Human-machine interface • Hardware parity generation and checking • 1/16 bit-time noise detection 4.5.7.5 Secure Digital Host Controller (SDHC) • Compatible with the following specifications: • SD Host Controller Standard Specification, Version 2.0 (http://www.sdcard.org ) with test event register and advanced DMA support • MultiMediaCard System Specification, Version 4.2 (http://www.mmca.org ) • SD Memory Card Specification, Version 2.0 (http://www.sdcard.
Power modes • Configurable slew rate and drive strength on all output pins • Independent pin value register to read logic level on digital pin • Optional devices with 5V tolerance 4.5.8.
Power modes Table 10. Chip power modes (continued) Chip mode Description Core mode Normal recovery method VLPS (Very Low Places chip in static state with LVD operation off. Lowest power mode Power Stop)-via with ADC and pin interrupts functional. Peripheral clocks are stopped, WFI but LPTimer, RTC, CMP, DAC can be used. NVIC is disabled (FCLK = OFF); AWIC is used to wake up from interrupt.
Developer Environment 6 Developer Environment Freescale's products are supported by a widespread, established network of tools and third party developers and software vendors. The Kinetis families take advantage of these and similar development resources. 6.1 Freescale's Tower System Support Freescale's Tower System is a modular development platform for 8-bit, 16-bit, and 32-bit microcontrollers that enables advanced development through rapid prototyping.
Developer Environment Table 11.
Developer Environment Table 12. CodeWarrior 10.x Differentiating Features Differentiating features MCU Change Wizard Customer benefits Ability to easily retarget project to a new processor Details Simply select a new device (from the same or a different architecture) and select the default connection, and the CodeWarrior tool suite automatically reconfigures the project for the new device with the correct build tools and support files.
Developer Environment Freescale Comprehensive Solution CodeWarrior™ Development Environment (MQX OS Aware) CodeWarrior Processor Expert™ MQX Design and Development Tools Demo Code Customized Applications Application Tasks and Industry-Specific Libraries MQX RTOS Optional Services Ethernet (RTCS) USB File System CAN Core Services MQX RTOS Third Party: IAR (MQX OS Aware) Open Source BDM and Third Party: Emulator/Probe Applications BSP/PSP BDM/JTAG Microcontroller Discrete Driver, Third Party
Developer Environment • Fast boot sequence: Ensures the application is running quickly after the hardware has been reset. • Simple Message Passing: Messages can be passed either from a system pool or a private pool, sent with either urgent status or a user-defined priority, and broadcast or task specific. For maximum flexibility, a receiving task can operate on either the same CPU as the sending task or on a different CPU within the same system. For more information see the MQX web site at http://www.
Revision History 7 Revision History The following table provides a revision history for this document. Table 13. Revision History Rev. No.
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