Freescale Semiconductor Product Brief Document Number:K20PB Rev. 11, 08/2012 K20 Family Product Brief Supports all K20 devices Contents 1 Kinetis Portfolio 1 Kinetis Portfolio........................................................1 Kinetis is the most scalable portfolio of low power, mixedsignal ARM®Cortex™-M4 MCUs in the industry. Phase 1 of the portfolio consists of five MCU families with over 200 pin-, peripheral- and software-compatible devices.
Kinetis Portfolio Family Program Flash Packages K70 Family 512KB-1MB 196-256pin K6x Family 256KB-1MB 100-256pin K5x Family 128-512KB 64-144pin K40 Family 64-512KB 64-144pin K30 Family 64-512KB 64-144pin K20 Family 32KB-1MB 32-144pin K10 Family 32KB-1MB 32-144pin Low power Mixed signal Encryption and Tamper Detect Key Features USB Segment LCD Operational & transimpedance amplifiers DDR Ethernet Graphic LCD Figure 1.
K20 Family Introduction • • • • • • • EEPROM erase/write times an order of magnitude faster than traditional EEPROM • Multi-function external bus interface capable of interfacing to external memories, gate-array logic Mixed-signal analog: • Fast, high precision 16-bit ADCs, 12-bit DACs, high speed comparators and an internal voltage reference.
K20 Block Diagram Kinetis K20 Family ARM ® Cortex™-M4 Core Debug interfaces DSP Interrupt controller System Memories and Memory Interfaces Clocks Internal and external watchdogs Program flash DMA FlexMemory Frequencylocked loop Low-leakage wakeup Serial programming interface Low/high frequency oscillators RAM Phaselocked loop Internal reference clocks Security Communication Interfaces Human-Machine Interface (HMI) Analog Timers 16-bit ADC Timers x3 (16ch) I C x2 I S x1 GPIO Rand
Features 4 Features 4.1 Common features among the K20 family All devices within the K20 family features the following at a minimum: Table 1. Common features among all K20 devices Operating characteristics • • • • Voltage range 1.71V - 3.6V Flash memory programming down to 1.
Features Table 1.
Features Table 2. K20 family summary (continued) Flash (KB) FlexNVM (KB) EEPROM/ FlexRAM (KB) 32 QFN (5x5) 48 QFN (7x7) 48 LQFP (7x7) 64 BGA (5x5) 64 LQFP (10x10) 80 LQFP (12x12) 81 BGA (8x8) 100 LQFP (14x14) 120 WLCSP (5.3x5.
Features 4.2.1 Programmable Trade-Off FlexMemory lets you fully configure the way FlexNVM and FlexRAM blocks are used to provide the best balance of memory resources for their application. The user can configure several parameters, including EEPROM size, endurance, write size, and the size of additional program/data flash. In addition to this flexibility, FlexMemory provides superior EEPROM performance, endurance, and low-voltage operation when compared to traditional EEPROM solutions.
Features Field Description Values K## Kinetis family • K20 • K21 • K22 A Key attribute • D = Cortex-M4 w/ DSP • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only • X = Program flash and FlexMemory FFF Program flash memory size • • • • • • R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7
Features 4.4.1 K20 family features (50MHz Performance) 1 MK20DX64VFT5(R) MK20DN64VFT5(R) MK20DX32VFT5(R) MK20DN32VFT5(R) MK20DX128VLF5(R) MK20DN128VLF5(R) MK20DX64VLF5(R) MK20DN64VLF5(R) MK20DX32VLF5(R) MK20DN32VLF5(R) MK20DX128VFM5(R) MK20DN128VFM5(R) MK20DX64VFM5(R) MK20DN64VFM5(R) MK20DX32VFM5(R) MC Partnumber MK20DN32VFM5(R) Table 3.
Features NMI MK20DN64VFM5(R) MK20DX64VFM5(R) MK20DN128VFM5(R) MK20DX128VFM5(R) MK20DN32VLF5(R) MK20DX32VLF5(R) MK20DN64VLF5(R) MK20DX64VLF5(R) MK20DN128VLF5(R) MK20DX128VLF5(R) MK20DN32VFT5(R) MK20DX32VFT5(R) MK20DN64VFT5(R) MK20DX64VFT5(R) Trace MK20DX32VFM5(R) MC Partnumber MK20DN32VFM5(R) Table 3.
Features - - - - - - - - - - - - - - - - 12-bit DAC - - - - - - - - - - - - - - - - Analog Comparator 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Analog Comparator Inputs MK20DX64VFT5(R) PGA MK20DN64VFT5(R) 6ch MK20DX32VFT5(R) 6ch MK20DN32VFT5(R) MK20DX128VFM5(R) 6ch MK20DN128VLF5(R) MK20DN128VFM5(R) 6ch MK20DX64VLF5(R) MK20DX64VFM5(R) 6ch MK20DN64VLF5(R) MK20DN64VFM5(R) 6ch MK20DX32VLF5(R) MK20DX32VFM5(R) ADC SE MK20DN32VLF5(R) MC Partnumber MK
Features MC Partnumber MK20DN32VFM5(R) MK20DX32VFM5(R) MK20DN64VFM5(R) MK20DX64VFM5(R) MK20DN128VFM5(R) MK20DX128VFM5(R) MK20DN32VLF5(R) MK20DX32VLF5(R) MK20DN64VLF5(R) MK20DX64VLF5(R) MK20DN128VLF5(R) MK20DX128VLF5(R) MK20DN32VFT5(R) MK20DX32VFT5(R) MK20DN64VFT5(R) MK20DX64VFT5(R) Table 3.
Features 4.4.
Features Trace MK20DX128VMP5(R) MK20DN128VMP5(R) MK20DX64VMP5(R) MK20DN64VMP5(R) MK20DX32VMP5(R) MK20DN32VMP5(R) MK20DX128VLH5(R) MK20DN128VLH5(R) MK20DX64VLH5(R) MK20DN64VLH5(R) MK20DX32VLH5(R) MK20DN32VLH5(R) MK20DX128VFT5(R) MC Partnumber MK20DN128VFT5(R) Table 4.
Features MK20DN128VFT5(R) MK20DX128VFT5(R) MK20DN32VLH5(R) MK20DX32VLH5(R) MK20DN64VLH5(R) MK20DX64VLH5(R) MK20DN128VLH5(R) MK20DX128VLH5(R) MK20DN32VMP5(R) MK20DX32VMP5(R) MK20DN64VMP5(R) MK20DX64VMP5(R) MK20DN128VMP5(R) MK20DX128VMP5(R) Table 4.
Features MC Partnumber MK20DN128VFT5(R) MK20DX128VFT5(R) MK20DN32VLH5(R) MK20DX32VLH5(R) MK20DN64VLH5(R) MK20DX64VLH5(R) MK20DN128VLH5(R) MK20DX128VLH5(R) MK20DN32VMP5(R) MK20DX32VMP5(R) MK20DN64VMP5(R) MK20DX64VMP5(R) MK20DN128VMP5(R) MK20DX128VMP5(R) Table 4.
Features MK21DN512VMC5(R) LQFP MK21DX256VMC5(R) LQFP MK21DX128VMC5(R) MK21DX256VLK5(R) Package MK21DN512VLK5(R) MC Partnumber MK21DX128VLK5(R) Table 5.
Features MC Partnumber MK21DX128VLK5(R) MK21DX256VLK5(R) MK21DN512VLK5(R) MK21DX128VMC5(R) MK21DX256VMC5(R) MK21DN512VMC5(R) Table 5.
Features MC Partnumber MK21DX128VLK5(R) MK21DX256VLK5(R) MK21DN512VLK5(R) MK21DX128VMC5(R) MK21DX256VMC5(R) MK21DN512VMC5(R) Table 5.
Features 4.4.
Features MC Partnumber MK22DX128VLF5(R) MK22DX256VLF5(R) MK22DX128VLH5(R) MK22DX256VLH5(R) MK22DN512VLH5(R) MK22DX128VLK5(R) MK22DX256VLK5(R) MK22DN512VLK5(R) MK22DX128VMC5(R) MK22DX256VMC5(R) MK22DN512VMC5(R) Table 6.
Features MK22DX256VMC5(R) MK22DN512VMC5(R) YES MK22DX128VMC5(R) YES MK22DN512VLK5(R) MK22DX256VLH5(R) YES MK22DX256VLK5(R) MK22DX128VLH5(R) YES MK22DX128VLK5(R) MK22DX256VLF5(R) Vref MK22DN512VLH5(R) MC Partnumber MK22DX128VLF5(R) Table 6.
Features MC Partnumber MK22DX128VLF5(R) MK22DX256VLF5(R) MK22DX128VLH5(R) MK22DX256VLH5(R) MK22DN512VLH5(R) MK22DX128VLK5(R) MK22DX256VLK5(R) MK22DN512VLK5(R) MK22DX128VMC5(R) MK22DX256VMC5(R) MK22DN512VMC5(R) Table 6.
Features MC Partnumber MK20DX64VLH7(R) MK20DX128VLH7(R) MK20DX256VLH7(R) MK20DX64VLK7(R) MK20DX128VLK7(R) MK20DX256VLK7(R) MK20DX128VLL7(R) MK20DX256VLL7(R) MK20DX64VMC7(R) MK20DX128VMC7(R) MK20DX256VMC7(R) Table 7.
Features MC Partnumber MK20DX64VLH7(R) MK20DX128VLH7(R) MK20DX256VLH7(R) MK20DX64VLK7(R) MK20DX128VLK7(R) MK20DX256VLK7(R) MK20DX128VLL7(R) MK20DX256VLL7(R) MK20DX64VMC7(R) MK20DX128VMC7(R) MK20DX256VMC7(R) Table 7.
Features MC Partnumber MK20DX64VLH7(R) MK20DX128VLH7(R) MK20DX256VLH7(R) MK20DX64VLK7(R) MK20DX128VLK7(R) MK20DX256VLK7(R) MK20DX128VLL7(R) MK20DX256VLL7(R) MK20DX64VMC7(R) MK20DX128VMC7(R) MK20DX256VMC7(R) Table 7.
Features 4.4.6 K20 family features (100MHz Performance) MK20DN512VLL10(R) MK20DX256VMC10(R) MK20DN512VMC10(R) MK20DN512VLQ10(R) MK20DN512VMD10(R) 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz Pin Count 144 144 144 144 80 100 121 121 144 144 Package LQFP MAPBG A LQFP MAPBG A LQFP LQFP LQFP MAPBG A MK20DX256VMD10(R) CPU Frequency MC Partnumber MK20DX128VMD10(R) MK20DN512VLK10(R) MK20DX256VLQ10(R) MK20DX128VLQ10(R) Table 8.
Features MK20DN512VLL10(R) MK20DX256VMC10(R) MK20DN512VMC10(R) MK20DN512VLQ10(R) MK20DN512VMD10(R) YES YES YES YES YES YES YES YES YES YES Hardware Watchdog YES YES YES YES YES YES YES YES YES YES PMC YES YES YES YES YES YES YES YES YES YES MPU YES YES YES YES YES YES YES YES YES YES DMA 16ch 16ch 16ch 16ch 16ch 16ch 16ch 16ch 16ch 16ch MK20DX256VMD10(R) Software Watchdog MC Partnumber MK20DX128VMD10(R) MK20DN512VLK10(R) MK20DX256VLQ10(R) MK2
Features MC Partnumber MK20DX128VLQ10(R) MK20DX128VMD10(R) MK20DX256VLQ10(R) MK20DX256VMD10(R) MK20DN512VLK10(R) MK20DN512VLL10(R) MK20DX256VMC10(R) MK20DN512VMC10(R) MK20DN512VLQ10(R) MK20DN512VMD10(R) Table 8.
Features MK20DN512VMD10(R) - MK20DN512VLQ10(R) - MK20DN512VMC10(R) MK20DX256VMD10(R) - MK20DX256VMC10(R) MK20DX256VLQ10(R) - MK20DN512VLL10(R) MK20DX128VMD10(R) IEEE1588 Timer MK20DN512VLK10(R) MC Partnumber MK20DX128VLQ10(R) Table 8.
Features MK20FX512VLQ12(R) MK20FN1M0VLQ12(R) MK20FX512VMD12(R) MK20FN1M0VMD12(R) Table 9.
Features MK20FX512VMD12(R) MK20FN1M0VMD12(R) Hardware Encryption - - - - Tamper Detect - - - - Number of External Tamper Pins - - - - CRC YES YES YES YES MK20FX512VLQ12(R) MK20FN1M0VLQ12(R) Table 9.
Features MC Partnumber MK20FX512VLQ12(R) MK20FN1M0VLQ12(R) MK20FX512VMD12(R) MK20FN1M0VMD12(R) Table 9.
Core modules 4.5.1 Core modules 4.5.1.1 • • • • • • • • • • Supports up to 120 MHz frequency with 1.
System modules • CoreSight™ Embedded Trace Buffer (ETB) is a memory-mapped buffer to store trace data. Allows reconstruction of program flow with standard JTAG tools. • Test Port Interface Unit (TPIU) acts as a bridge between ITM or ETM and an off-chip Trace Port Analyzer • Flash Patch and Breakpoints (FPB) implements hardware breakpoints and patches code and data from code space to system space 4.5.2 System modules 4.5.2.
Memories and Memory Interfaces 4.5.2.5 External Watchdog Monitor (EWM) • Independent 1 kHz LPO clock source • Output signal to gate an external circuit which is controlled by CPU service or external input 4.5.2.6 System Clocks • Frequency-locked loop (FLL) • Digitally-controlled oscillator (DCO) • DCO frequency range is programmable • Option to program DCO frequency for a 32,768 Hz external reference clock source • Internal or external reference clock can be used to control the FLL • 0.
Security and Integrity • Flexmemory block contains up to 512KB FlexNVM and 16KB FlexRAM with up to 16KB EEPROM capability • Up to 128KB SRAM • 16KB cache • Security circuitry to prevent unauthorized access to RAM and flash contents 4.5.3.
Analog 4.5.4.3 Random Number Generator (RNG) • Supports the key generation algorithm defined in the Digital Signature Standard • http://www.itl.nist.gov/fipspubs/fip186.htm • Integrated entropy sources capable of providing the PRNG with entropy for its seed 4.5.4.
Timers 4.5.5.2 High-Speed Analog Comparator (CMP) • Updated to allow the Analog input mux to be used as a pass through mux http://designpdm.freescale.
Timers • One trigger output for ADC hardware trigger and up to eight pre-trigger outputs for ADC trigger select per PDB channel • Trigger outputs can be enabled or disabled independently.
Communication interfaces • Selectable clock for prescaler/glitch filter • 1 kHz internal LPO • External low power crystal oscillator • Internal reference clock (not available in low leakage power modes) • Secondary external reference clock (for example, 32 kHz crystal) • Configurable glitch filter or prescaler • Interrupt generated on timer compare • Hardware trigger generated on timer compare 4.5.6.
Communication interfaces 4.5.7.2 USB Device Charger Detect (USBDCD) • Compatible with systems powered from: • Rechargable battery • Non-rechargable battery • External 3.3v LDO regulator powered from USB or • Directly from USB using internal regulator • Option to set nominal 3.
Communication interfaces • Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 bytes data length each, configurable as Rx or Tx, all supporting standard and extended messages • Listen-only mode capability • Individual mask registers for each message buffer • Programmable transmit-first scheme: lowest ID or lowest buffer number • Timestamp based on 16-bit free-running timer • Global network time, synchronized by a specific message 4.5.7.
Communication interfaces • • • • • • • • Idle line wakeup • Address mark wakeup Address match feature in receiver to reduce address mark wakeup ISR overhead Hardware flow control support for request to send (RTS) and clear to send (CTS) signals Support for CEA709.1-B protocol (LON) used in building automation and home networking systems Interrupt or DMA driven operation Receiver framing error detection Hardware parity generation and checking 1/16 bit-time noise detection 4.5.7.
Human-machine interface 4.5.8 Human-machine interface 4.5.8.1 General Purpose Input/Output (GPIO) 4.5.8.
Power modes Table 10. Chip power modes (continued) Chip mode Description Core mode Normal recovery method Run Interrupt Sleep Interrupt VLPS (Very Low Places chip in static state with LVD operation off. Lowest power mode Power Stop)-via with ADC and pin interrupts functional. Peripheral clocks are stopped, WFI but LPTimer, RTC, CMP, DAC can be used. NVIC is disabled (FCLK = OFF); AWIC is used to wake up from interrupt.
Developer Environment Table 10. Chip power modes (continued) Chip mode BAT (backup battery only) Description The chip is powered down except for the VBAT supply. The RTC and the 32-byte VBAT register file for customer-critical data remain powered. Core mode Normal recovery method Off Power-up Sequence 1. Resumes normal run mode operation by executing the LLWU interrupt service routine. 2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.
Developer Environment The Freescale Tower System Primary Elevator MCU/ MPU Module • Common serial and expansion bus signals • Tower controller board • Works stand-alone or in Tower System • Two 2x80 connectors on backside for easy signal access and side-mounting board (i.e.
Developer Environment Table 11.
Developer Environment Table 12. CodeWarrior 10.x Differentiating Features (continued) Differentiating features Customer benefits Details Freescale Problems in Combines easy-to-use component-based application creation with an expert knowledge Processor Expert hardware system.
Developer Environment Freescale Comprehensive Solution CodeWarrior™ Development Environment (MQX OS Aware) CodeWarrior Processor Expert™ MQX Design and Development Tools Demo Code Customized Applications Application Tasks and Industry-Specific Libraries MQX RTOS Optional Services Ethernet (RTCS) USB File System CAN Core Services MQX RTOS Third Party: IAR (MQX OS Aware) Open Source BDM and Third Party: Emulator/Probe Applications BSP/PSP BDM/JTAG Microcontroller Discrete Driver, Third Party
Developer Environment • Fast boot sequence: Ensures the application is running quickly after the hardware has been reset. • Simple Message Passing: Messages can be passed either from a system pool or a private pool, sent with either urgent status or a user-defined priority, and broadcast or task specific. For maximum flexibility, a receiving task can operate on either the same CPU as the sending task or on a different CPU within the same system. For more information see the MQX web site at http://www.
Revision History 7 Revision History The following table provides a revision history for this document. Table 13. Revision History Rev. No.
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