Datasheet

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Kinetis KL15 Sub-Family

48 MHz Cortex-M0+ Based Microcontroller

Designed with efficiency in mind. Compatible with all other

Kinetis L families as well as Kinetis K1x family. General purpose

MCU featuring market leading ultra low-power to provide

developers an appropriate entry-level 32-bit solution.

This product offers:

• Run power consumption down to 47 μA/MHz in very low

power run mode

• Static power consumption down to 2 μA with full state

retention and 4 μs wakeup

• Ultra-efficient Cortex-M0+ processor running up to 48MHz

with industry leading throughput

• Memory option is up to 128 KB flash and 16 KB RAM

• Energy-saving architecture is optimized for low power with

90 nm TFS technology, clock and power gating techniques,

and zero wait state flash memory controller

Performance

• 48 MHz ARM

Cortex

-M0+ core

Memories and memory interfaces

• Up to 128 KB program flash memory

• Up to 16 KB SRAM

System peripherals

• Nine low-power modes to provide power optimization

based on application requirements

• COP Software watchdog

• 4-channel DMA controller, supporting up to 63 request

sources

• Low-leakage wakeup unit

• SWD debug interface and Micro Trace Buffer

• Bit Manipulation Engine

Clocks

• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator

• Multi-purpose clock source

• 1 kHz LPO clock

Operating Characteristics

• Voltage range: 1.71 to 3.6 V

• Flash write voltage range: 1.71 to 3.6 V

• Temperature range (ambient): -40 to 105°C

Human-machine interface

• Low-power hardware touch sensor interface (TSI)

• Up to 70 general-purpose input/output (GPIO)

Communication interfaces

• Two 8-bit SPI modules

• One low power UART module

• Two UART modules

• Two I2C module

Analog Modules

• 16-bit SAR ADC

• 12-bit DAC

• Analog comparator (CMP) containing a 6-bit DAC

and programmable reference input

Timers

• Six channel Timer/PWM (TPM)

• Two 2-channel Timer/PWM modules

• Periodic interrupt timers

• 16-bit low-power timer (LPTMR)

• Real time clock

Security and integrity modules

• 80-bit unique identification number per chip

MKL15ZxxVFM4

MKL15ZxxVFT4

MKL15ZxxVLH4

MKL15ZxxVLK4

32-pin QFN (FM)

5 x 5 x 1 Pitch 0.5 mm

48-pin QFN (FT)

7 x 7 x 1 Pitch 0.5 mm

64-pin LQFP (LH)

10 x 10 x 1.4 Pitch 0.5

80-pin LQFP (LK)

12 x 12 x 1.4 Pitch 0.5

Freescale Semiconductor, Inc.

KL15P80M48SF0

Data Sheet: Technical Data Rev 4 03/2014

Freescale reserves the right to change the detail specifications as may be required to

Summary of content (57 pages)

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Freescale Semiconductor, Inc. Data Sheet: Technical Data KL15P80M48SF0 Rev 4 03/2014 Kinetis KL15 Sub-Family 48 MHz Cortex-M0+ Based Microcontroller Designed with efficiency in mind. Compatible with all other Kinetis L families as well as Kinetis K1x family. General purpose MCU featuring market leading ultra low-power to provide developers an appropriate entry-level 32-bit solution.
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Ordering Information Part Number Memory Maximum number of I\O's Flash (KB) SRAM (KB) MKL15Z32VFM4 32 4 28 MKL15Z64VFM4 64 8 28 MKL15Z128VFM4 128 16 28 MKL15Z32VFT4 32 4 40 MKL15Z64VFT4 64 8 40 MKL15Z128VFT4 128 16 40 MKL15Z32VLH4 32 4 54 MKL15Z64VLH4 64 8 54 MKL15Z128VLH4 128 16 54 MKL15Z32VLK4 32 4 70 MKL15Z64VLK4 64 8 70 MKL15Z128VLK4 128 16 70 Related Resources Type Description Selector Guide The Freescale Solution Advisor is a web-based tool that f
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Table of Contents 1 Ratings..................................................................................4 1.1 Thermal handling ratings...............................................4 1.2 Moisture handling ratings...............................................4 1.3 ESD handling ratings.....................................................4 1.4 Voltage and current operating ratings............................4 2 General.................................................................................5 2.
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Ratings 1 Ratings 1.1 Thermal handling ratings Table 1. Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Table 2.
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General 1.4 Voltage and current operating ratings Table 4. Voltage and current operating ratings Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 120 mA VIO IO pin input voltage –0.3 VDD + 0.3 V Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA VDD – 0.3 VDD + 0.3 V ID VDDA Analog supply voltage 2 General 2.
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General 2.2.1 Voltage and current operating requirements Table 5. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V — VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V — VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V — VIH VIL Input high voltage — • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V Input low voltage — • 2.7 V ≤ VDD ≤ 3.
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General Table 6. VDD supply LVD and POR operating requirements (continued) Symbol Min. Typ. Max. Unit VLVW3H Description • Level 3 falling (LVWV = 10) 2.82 2.90 2.98 V VLVW4H • Level 4 falling (LVWV = 11) 2.92 3.00 3.08 V — ±60 — mV — 1.54 1.60 1.66 V — VHYSH Low-voltage inhibit reset/recover hysteresis — high range VLVDL Falling low-voltage detect threshold — low range (LVDV=00) Notes Low-voltage warning thresholds — low range 1 VLVW1L • Level 1 falling (LVWV = 00) 1.
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General Table 7. Voltage and current operating behaviors (continued) Symbol Description Min. Max. Unit — 0.5 V Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.
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General Table 8. Power mode transition operating behaviors (continued) Symbol Description • VLLS1 → RUN Min. Typ. Max. Unit — 93 115 μs — 42 53 μs — 4 4.6 μs — 4 4.4 μs — 4 4.4 μs • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN 1. Normal boot (FTFA_FOPT[LPBOOT]=11). 2.2.5 Power consumption operating behaviors Table 9.
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General Table 9. Power consumption operating behaviors (continued) Symbol Description IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V IDD_WAIT Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled • at 3.0 V IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.
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General Table 9. Power consumption operating behaviors (continued) Symbol Description at 85 °C Min. Typ. Max. — 81 201 1.9 3.7 3.6 39 6.5 43 13 49 30 69 — 1.4 3.2 — 2.5 19 — 5.1 21 — 9.2 26 — 21 38 — 0.7 — 1.3 — 2.3 — 5.1 — 13 — 381 — 956 — 2370 — 4800 — 12410 — 176 — 760 — 2120 — 4500 — 12130 Unit Notes at 105 °C IDD_LLS Low-leakage stop mode current at 3.
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General 4. Incremental current consumption from peripheral activity is not included. 5. MCG configured for BLPI mode. 6. No brownout Table 10. Low power mode peripheral adders — typical value Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Measured by entering STOP or VLPS mode with 4 MHz IRC enabled. 56 56 56 56 56 56 µA IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder.
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General Table 10. Low power mode peripheral adders — typical value (continued) Symbol Description Temperature (°C) Unit -40 25 50 70 85 105 generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents. • MCGIRCLK (4 MHz internal reference clock) • OSCERCLK (4 MHz external crystal) 235 256 265 274 280 287 IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode.
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General Run Mode Current Vs Core Frequency Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE 8.00E-03 7.00E-03 Current Consumption on VDD(A) 6.00E-03 5.00E-03 All Peripheral CLK Gates 4.00E-03 All Off All On 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-1 '1-2 1 2 3 4 6 12 24 48 CLK Ratio Flash-Core Core Freq (MHz) Figure 2. Run mode supply current vs. core frequency 14 Freescale Semiconductor, Inc.
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General VLPR Mode Current Vs Core Frequency Temperature = 25, V DD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE 400.00E-06 Current Consumption on VDD (A) 350.00E-06 300.00E-06 250.00E-06 All Peripheral CLK Gates 200.00E-06 All Off All On 150.00E-06 100.00E-06 50.00E-06 000.00E+00 '1-1 '1-2 1 '1-2 '1-4 2 4 CLK Ratio Flash-Core Core Freq (MHz) Figure 3. VLPR mode current vs. core frequency 2.2.6 EMC radiated emissions operating behaviors Table 11.
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General application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VDD = 3.3 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 48 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 2.2.
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General Table 13. Device clock specifications (continued) Symbol Description Min. Max. Unit — 16 MHz Oscillator crystal or resonator frequency — high frequency mode (high range) (MCG_C2[RANGE]=1x) — 16 MHz TPM asynchronous clock — 8 MHz UART0 asynchronous clock — 8 MHz fLPTMR_ERCLK LPTMR external reference clock fosc_hi_2 fTPM fUART0 1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing specification for any other module.
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Peripheral operating requirements and behaviors 2.4.2 Thermal attributes Table 16. Thermal attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) Description 80 LQFP 64 LQFP 48 QFN 32 QFN Unit Notes Thermal resistance, junction to ambient (natural convection) 70 71 84 92 °C/W 1 RθJA Thermal resistance, junction to ambient (natural convection) 53 52 28 33 °C/W Single-layer (1S) RθJMA Thermal resistance, junction to ambient (200 ft./min.
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Peripheral operating requirements and behaviors 3.1.1 SWD electricals Table 17. SWD full voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 1.71 3.
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Peripheral operating requirements and behaviors SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 5. Serial wire data timing 3.2 System modules There are no specifications necessary for the device's system modules. 3.3 Clock modules 3.3.1 MCG specifications Table 18. MCG specifications Symbol Description Min. Typ. Max.
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Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes Δfdco_t Total deviation of trimmed average DCO output frequency over voltage and temperature — +0.5/-0.7 ±3 %fdco 1, 2 Δfdco_t Total deviation of trimmed average DCO output frequency over fixed voltage and temperature range of 0–70 °C — ± 0.4 ± 1.
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Peripheral operating requirements and behaviors Table 18. MCG specifications (continued) Symbol Description Min. Jacc_pll PLL accumulated jitter over 1µs (RMS) Typ. Max. Unit 10 • fvco = 48 MHz — 1350 — ps • fvco = 100 MHz — 600 — ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time Notes — — 10-6 150 × + 1075(1/ fpll_ref) s 11 1.
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Peripheral operating requirements and behaviors Table 19. Oscillator DC electrical specifications (continued) Symbol Description • 24 MHz Min. Typ. Max. Unit — 1.5 — mA Notes • 32 MHz IDDOSC Supply current — high gain mode (HGO=1) 1 • 32 kHz — 25 — μA • 4 MHz — 400 — μA • 8 MHz (RANGE=01) — 500 — μA • 16 MHz — 2.
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Peripheral operating requirements and behaviors 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 Symbol Oscillator frequency specifications Table 20.
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Peripheral operating requirements and behaviors 3.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 21. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 Notes Longword Program high-voltage time — 7.
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Peripheral operating requirements and behaviors 3.4.1.4 Symbol Reliability specifications Table 24. NVM reliability specifications Description Min. Typ.1 Max. Unit Notes Program Flash tnvmretp10k Data retention after up to 10 K cycles 5 50 — years tnvmretp1k Data retention after up to 1 K cycles 20 100 — years nnvmcycp Cycling endurance 10 K 50 K — cycles 2 1.
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Peripheral operating requirements and behaviors Table 25. 16-bit ADC operating conditions (continued) Symbol Description VADIN Input voltage CADIN RADIN RAS Input capacitance Min. Typ.1 Max.
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Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS ADC SAR ENGINE RADIN VADIN CAS VAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 6. ADC input impedance equivalency diagram 3.6.1.2 16-bit ADC electrical characteristics Table 26.
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Peripheral operating requirements and behaviors Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol INL Description Integral nonlinearity EFS Full-scale error EQ Quantization error ENOB Conditions1 Min. Typ.2 Max. Unit Notes –2.7 to +1.9 LSB4 5 LSB4 VADIN = VDDA5 • 12-bit modes — ±1.0 • <12-bit modes — ±0.5 • 12-bit modes — –4 –5.4 • <12-bit modes — –1.4 –1.8 • 16-bit modes — –1 to 0 — • ≤13-bit modes — — ±0.5 12.8 14.5 — bits 11.
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Peripheral operating requirements and behaviors 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power).
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Peripheral operating requirements and behaviors 3.6.2 CMP and 6-bit DAC electrical specifications Table 27. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.
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Peripheral operating requirements and behaviors CMP Hysteresis vs Vinn 90.00E-03 80.00E-03 70.00E-03 CMP Hysteresis (V) 60.00E-03 HYSTCTR Setting 50.00E-03 0 1 40.00E-03 2 3 30.00E-03 20.00E-03 10.00E-03 000.00E+00 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 Vinn (V) Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) CMP Hysteresis vs Vinn 180.00E-03 160.00E-03 140.00E-03 CMP Hysteresis (V) 120.00E-03 HYSTCTR Setting 100.00E-03 0 1 80.00E-03 2 3 60.
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Peripheral operating requirements and behaviors 3.6.3.2 Symbol 12-bit DAC operating behaviors Table 29. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 250 μA — — 900 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.
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Peripheral operating requirements and behaviors 8 6 4 DAC12 INL (LSB) 2 0 -2 -4 -6 -8 0 500 1000 1500 2000 2500 3000 3500 4000 Digital Code Figure 11. Typical INL error vs. digital code 34 Freescale Semiconductor, Inc. Kinetis KL15 Sub-Family, Rev4 03/2014.
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Peripheral operating requirements and behaviors 1.499 DAC12 Mid Level Code Voltage 1.4985 1.498 1.4975 1.497 1.4965 1.496 -40 55 25 85 105 125 Temperature °C Figure 12. Offset at half scale vs. temperature 3.7 Timers See General switching specifications. 3.8 Communication interfaces Kinetis KL15 Sub-Family, Rev4 03/2014. 35 Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors 3.8.1 SPI switching specifications The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic SPI timing modes. See the SPI chapter of the chip's Reference Manual for information about the modified transfer formats used for communicating with slower peripheral devices.
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Peripheral operating requirements and behaviors Table 31. SPI master mode timing on slew rate enabled pads (continued) Num. Symbol 8 tv 9 Description Min. Max. Unit Note Data valid (after SPSCK edge) — 52 ns — tHO Data hold time (outputs) 0 — ns — 10 tRI Rise time input — tperiph – 25 ns — tFI Fall time input 11 tRO Rise time output — 36 ns — tFO Fall time output 1. For SPI0, fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS). 2.
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Peripheral operating requirements and behaviors SS 1 (OUTPUT) 2 3 10 11 4 10 11 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 5 6 MISO (INPUT) 7 MSB IN BIT 6 . . . 1 2 9 8 MOSI (OUTPUT) LSB IN PORT DATA MASTER MSB OUT 2 BIT 6 . . . 1 PORT DATA MASTER LSB OUT 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 14. SPI master mode timing (CPHA = 1) Table 32. SPI slave mode timing on slew rate disabled pads Num.
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Peripheral operating requirements and behaviors Table 33. SPI slave mode timing on slew rate enabled pads Num. Symbol 1 fop 2 tSPSCK 3 tLead Enable lead time 4 tLag Enable lag time 5 tWSPSCK 6 tSU 7 Frequency of operation SPSCK period Min. Max.
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Peripheral operating requirements and behaviors SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 see note SLAVE 8 MSB OUT 6 MOSI (INPUT) 13 12 13 11 10 MISO (OUTPUT) 12 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . . 1 LSB IN 7 MSB IN NOTE: Not defined Figure 16. SPI slave mode timing (CPHA = 1) 3.8.2 Inter-Integrated Circuit Interface (I2C) timing Table 34.
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Peripheral operating requirements and behaviors 2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 4. Input signal Slew = 10 ns and Output Load = 50 pF 5.
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Dimensions 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00473D 48-pin QFN 98ASA00466D 64-pin LQFP 98ASS23234W 80-pin LQFP 98ASS23174W 5 Pinout 5.
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Pinout 80 64 LQFP LQFP 48 QFN 32 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT5 TPM_CLKIN1 ALT6 ALT7 10 6 4 4 PTE17 ADC0_DM1/ ADC0_SE5a ADC0_DM1/ ADC0_SE5a PTE17 SPI0_SCK 11 7 5 5 PTE18 ADC0_DP2/ ADC0_SE2 ADC0_DP2/ ADC0_SE2 PTE18 SPI0_MOSI I2C0_SDA SPI0_MISO 12 8 6 6 PTE19 ADC0_DM2/ ADC0_SE6a ADC0_DM2/ ADC0_SE6a PTE19 SPI0_MISO I2C0_SCL SPI0_MOSI 13 9 7 — PTE20 ADC0_DP0/ ADC0_SE0 ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0 UART0_TX 14 10 8 — PTE21 ADC0_DM0/ AD
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Pinout 80 64 LQFP LQFP 48 QFN 32 QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 42 34 26 19 PTA20 RESET_b 43 35 27 20 PTB0/ LLWU_P5 ADC0_SE8/ TSI0_CH0 ADC0_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 44 36 28 21 PTB1 ADC0_SE9/ TSI0_CH6 ADC0_SE9/ TSI0_CH6 PTB1 I2C0_SDA TPM1_CH1 45 37 29 — PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL TPM2_CH0 46 38 30 — PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA TPM2_CH1 47 — — —
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Pinout 80 64 LQFP LQFP 48 QFN 32 QFN Pin Name Default 73 57 41 — PTD0 DISABLED 74 58 42 — PTD1 ADC0_SE5b 75 59 43 — PTD2 DISABLED 76 60 44 — PTD3 77 61 45 29 78 62 46 79 63 80 64 ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 PTD0 SPI0_PCS0 PTD1 SPI0_SCK PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO DISABLED PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_PCS0 UART2_RX TPM0_CH4 30 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI1_SCK
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PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC17 PTC16 PTC13 PTC12 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Pinout PTB10 PTE20 13 48 PTB9 PTE21 14 47 PTB8 PTE22 15 46 PTB3 PTE23 16 45 PTB2 VDDA 17 44 PTB1 VREFH 18 43 PTB0/LLWU_P5 VREFL 19 42 PTA20 VSSA 20 41 PTA19 40 49 PTA18 12 39 PTE19 VSS PTB11 38 50 VDD 11 37 PTE18 PT
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PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC11 PTC10 PTC9 PTC8 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout PTB18 PTE20 9 40 PTB17 PTE21 10 39 PTB16 PTE22 11 38 PTB3 PTE23 12 37 PTB2 VDDA 13 36 PTB1 VREFH 14 35 PTB0/LLWU_P5 VREFL 15 34 PTA20 VSSA 16 33 PTA19 PTA18 32 41 31 8 VSS PTE19 30 PTB19 VDD 42 29 7 PTA13 PTE18 28 PTC0 PTA12 43 27 6 PTA5 PTE17
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PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTD3 PTD2 PTD1 PTD0 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 48 47 46 45 44 43 42 41 40 39 38 37 Pinout PTB16 PTE20 7 30 PTB3 PTE21 8 29 PTB2 VDDA 9 28 PTB1 VREFH 10 27 PTB0/LLWU_P5 VREFL 11 26 PTA20 VSSA 12 25 PTA19 PTA18 24 31 23 6 VSS PTE19 22 PTB17 VDD 32 21 5 PTA4 PTE18 20 PTC0 PTA3 33 19 4 PTA2 PTE17 18 PTC1/LLWU_P6/RTC_CLKIN PTA1 34 17 3 PTA0 PTE16 16 PTC2 PTE25 35 15 2 PTE
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PTD7 PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 32 31 30 29 28 27 26 25 Ordering parts 21 PTB1 PTE18 5 20 PTB0/LLWU_P5 PTE19 6 19 PTA20 VDDA 7 18 PTA19 VSSA 8 17 PTA18 PTA0 PTE30 16 4 VSS PTE17 15 PTC1/LLWU_P6/RTC_CLKIN VDD 22 14 3 PTA4 PTE16 13 PTC2 PTA3 23 12 2 PTA2 PTE1 11 PTC3/LLWU_P7 PTA1 24 10 1 9 PTE0 Figure 21. KL15 32-pin QFN pinout diagram 6 Ordering parts 6.
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Part identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q KL## A FFF R T PP CC N 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Table 36.
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Terminology and guidelines 7.4 Example This is an example part number: MKL15Z32VFT4 8 Terminology and guidelines 8.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 Example This is an example of an operating requirement: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.
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Terminology and guidelines 8.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins Min. — Max. 7 Unit pF 8.
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Terminology and guidelines 8.5 Result of exceeding a rating 40 Failures in time (ppm) 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 8.6 Relationship between ratings and operating requirements g Op g in rat tin era nt ) in. (m me ire era Op g tin .) ) in. (m nt me ire u req g tin era Op ax (m .
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Terminology and guidelines 8.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. 8.8.
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Revision history 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.05 1.00 1.10 VDD (V) 8.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): Table 37. Typical value conditions Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 9 Revision history The following table provides a revision history for this document.
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Revision history Table 38. Revision history Rev. No. Date Substantial Changes • • • • • • • • • • • • 56 Freescale Semiconductor, Inc.
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