Freescale Semiconductor Data Sheet: Technical Data Document Number: MMA8451Q Rev. 8.1, 10/2013 An Energy Efficient Solution by Freescale Xtrinsic MMA8451Q 3-Axis, MMA8451Q 14-bit/8-bit Digital Accelerometer The MMA8451Q is a smart, low-power, three-axis, capacitive, micromachined accelerometer with 14 bits of resolution. This accelerometer is packed with embedded functions with flexible user programmable options, configurable to two interrupt pins.
Contents 1 2 3 4 5 6 Block Diagram and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Mechanical and Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Block Diagram and Pin Description Internal OSC X-axis Transducer VDD VDDIO INT2 Embedded DSP Functions 14-bit ADC C to V Converter Y-axis Transducer VSS INT1 Clock GEN SDA SCL I2 C Z-axis Transducer 32 Data Point Configurable FIFO Buffer with Watermark Freefall and Motion Detection Transient Detection (i.e.
Figure 3 shows the device configuration in the 6 different orientation modes. These orientations are defined as the following: PU = Portrait Up, LR = Landscape Right, PD = Portrait Down, LL = Landscape Left, BACK and FRONT side views. There are several registers to configure the orientation detection and are described in detail in the register setting section.
Table 1. Pin Description Pin # Pin Name 1 VDDIO Description 2 BYP Bypass capacitor (0.1 μF) Input 3 NC Leave open. Do not connect Open 4 SCL I2C Serial Clock 5 GND Connect to Ground 6 SDA I2 7 SA0 I2C Least Significant Bit of the Device I2C Address Input 8 NC Internally not connected (can be GND or VDD) Input Internal Power Supply (1.62V - 3.
2 Mechanical and Electrical Specifications 2.1 Mechanical Characteristics Table 2. Mechanical Characteristics @ VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted. Parameter Test Conditions Symbol Min FS[1:0] set to 00 2g Mode Measurement Range(1) Sensitivity FS[1:0] set to 01 4g Mode Typ FS ±4 ±8 FS[1:0] set to 00 2g Mode 4096 So g 2048 FS[1:0] set to 10 8g Mode Sensitivity Accuracy(2) Unit ±2 FS[1:0] set to 10 8g Mode FS[1:0] set to 01 4g Mode Max counts/g 1024 Soa ±2.
2.2 Electrical Characteristics Table 3. Electrical Characteristics @ VDD = 2.5V, VDDIO = 1.8V, T = 25°C unless otherwise noted. Parameter Test Conditions Supply Voltage Symbol VDD (1) VDDIO(1) Interface Supply Voltage Min Typ Max Unit 1.95 2.5 3.6 V 1.62 1.8 3.6 V ODR = 1.56 Hz 6 ODR = 6.25 Hz 6 ODR = 12.5 Hz 6 ODR = 50 Hz 14 Low Power Mode ODR = 100 Hz IddLP ODR = 200 Hz 44 ODR = 400 Hz 85 ODR = 800 Hz 165 ODR = 1.56 Hz 24 ODR = 6.25 Hz 24 ODR = 12.
2.3 I2C interface characteristics Table 4. I2C slave timing values(1) Parameter Symbol I2C Fast Mode Min Max 400 Unit SCL clock frequency fSCL 0 Bus-free time between STOP and START condition tBUF 1.3 μs (Repeated) START hold time tHD;STA 0.6 μs Repeated START setup time tSU;STA 0.6 μs STOP condition setup time tSU;STO 0.6 kHz μs μs SDA data hold time tHD;DAT 0.05 SDA setup time tSU;DAT 100 ns SCL clock low time tLOW 1.3 μs SCL clock high time tHIGH 0.
2.4 Absolute Maximum Ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5. Maximum Ratings Rating Symbol Value Unit Maximum Acceleration (all axes, 100 μs) gmax 5,000 g Supply Voltage VDD -0.3 to + 3.6 V Vin -0.3 to VDDIO + 0.3 V Drop Test Ddrop 1.
3 Terminology 3.1 Sensitivity The sensitivity is represented in counts/g. In 2g mode the sensitivity is 4096 counts/g. In 4g mode the sensitivity is 2048 counts/ g and in 8g mode the sensitivity is 1024 counts/g. 3.2 Zero-g Offset Zero-g Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A sensor stationary on a horizontal surface will measure 0g in X-axis and 0g in Y-axis whereas the Z-axis will measure 1g.
4 Modes of Operation SLEEP ACTIVE OFF STANDBY WAKE Figure 6. MMA8451Q Mode Transition Diagram Table 7. Mode of Operation Description Mode OFF I2C Bus State Powered Down VDD VDDIO <1.8V VDDIO Can be > VDD Function Description The device is powered off. All analog and digital blocks are shutdown. I2C bus inhibited. STANDBY I2C communication with MMA8451Q is possible ON VDDIO = High VDD = High ACTIVE bit is cleared Only digital blocks are enabled. Analog subsystem is disabled.
5 Functionality The MMA8451Q is a low-power, digital output 3-axis linear accelerometer with a I2C interface and embedded logic used to detect events and notify an external microprocessor over interrupt lines.
5.2 8-bit or 14-bit Data The measured acceleration data is stored in the OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB registers as 2’s complement 14-bit numbers. The most significant 8-bits of each axis are stored in OUT_X (Y, Z)_MSB, so applications needing only 8-bit results can use these 3 registers and ignore OUT_X,Y, Z_LSB. To do this, the F_READ bit in CTRL_REG1 must be set. When the F_READ bit is cleared, the fast read mode is disabled.
5.6 Freefall and Motion Detection MMA8451Q has flexible interrupt architecture for detecting either a Freefall or a Motion. Freefall can be enabled where the set threshold must be less than the configured threshold, or motion can be enabled where the set threshold must be greater than the threshold. The motion configuration has the option of enabling or disabling a high-pass filter to eliminate tilt data (static offset). The freefall does not use the high-pass filter.
5.9 Orientation Detection The MMA8451Q incorporates an advanced algorithm for orientation detection (ability to detect all 6 orientations) with configurable trip points. The embedded algorithm allows the selection of the mid point with the desired hysteresis value. The MMA8451Q Orientation Detection algorithm confirms the reliability of the function with a configurable Z-lockout angle.
Figure 9 illustrates the Z-angle lockout region. When lifting the device upright from the flat position it will be active for orientation detection as low as14° from flat. This is user configurable. The default angle is 29° but it can be set as low as 14°. . UPRIGHT 90° NORMAL DETECTION REGION Z-LOCK = 29° LOCKOUT REGION 0° FLAT Figure 9. Illustration of Z-Tilt Angle Lockout Transition 5.
MMA8451Q is in off mode and communications on the I2C interface are ignored. The I2C interface may be used for communications between other I2C devices and the MMA8451Q does not affect the I2C bus. Table 9. Serial Interface Pin Description Pin Name Pin Description SCL I2C Serial Clock SDA I2C Serial Data SA0 I2C least significant bit of the device address There are two signals associated with the I2C bus; the Serial Clock Line (SCL) and the Serial Data line (SDA).
complete, the Master transmits a stop condition (SP) to the data transfer. The data sent to the MMA8451Q is now stored in the appropriate register. Multiple Byte Write The MMA8451Q automatically increments the received register address commands after a write command is received. Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each MMA8451Q acknowledgment (ACK) is received. Table 11.
6 Register Descriptions Table 12. Register Address Map Name Auto-Increment Address Register Type Address FMODE = 0 FMODE > 0 FMODE = 0 FMODE > 0 Default Hex Value Comment 00000000 0x00 FMODE = 0, real time status FMODE > 0, FIFO status Output — [7:0] are 8 MSBs Root pointer to of 14-bit sample. XYZ FIFO data.
Table 12.
Table 13. STATUS Description ZYXOW X, Y, Z-axis Data Overwrite. Default value: 0 0: No data overwrite has occurred 1: Previous X, Y, or Z data was overwritten by new X, Y, or Z data before it was read ZOW Z-axis Data Overwrite. Default value: 0 0: No data overwrite has occurred 1: Previous Z-axis data was overwritten by new Z-axis data before it was read YOW Y-axis Data Overwrite.
Data Registers: 0x01 OUT_X_MSB, 0x02 OUT_X_LSB, 0x03 OUT_Y_MSB, 0x04 OUT_Y_LSB, 0x05 OUT_Z_MSB, 0x06 OUT_Z_LSB These registers contain the X-axis, Y-axis, and Z-axis14-bit output sample data expressed as 2's complement numbers.
Table 14. FIFO Flag Event Description F_OVF F_WMRK_FLAG Event Description 0 — No FIFO overflow events detected. 1 — FIFO event detected; FIFO has overflowed. — 0 No FIFO watermark events detected. — 1 FIFO Watermark event detected. FIFO sample count is greater than watermark value. If F_MODE = 11, Trigger Event detected.
0x0A: TRIG_CFG In the trigger configuration register the bits that are set (logic ‘1’) control which function may trigger the FIFO to its interrupt and conversely bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt. The bits set are rising edge sensitive, and are set by a low to high state change and reset by reading the appropriate source register.
0x0C: INT_SOURCE System Interrupt Status Register In the interrupt source register the status of the various embedded features can be determined. The bits that are set (logic ‘1’) indicate which function has asserted an interrupt and conversely the bits that are cleared (logic ‘0’) indicate which function has not asserted or has deasserted an interrupt. The bits are set by a low to high transition and are cleared by reading the appropriate interrupt source register.
0x0D: WHO_AM_I Device ID Register The device identification register identifies the part. The default value is 0x1A. This value is factory programmed. Consult the factory for custom alternate values. 0x0D: WHO_AM_I Device ID Register (Read Only) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 1 1 0 1 0 0x0E: XYZ_DATA_CFG Register The XYZ_DATA_CFG register sets the dynamic range and sets the high-pass filter for the output data.
Table 23. High-Pass Filter Cutoff Options Oversampling Mode = Normal SEL1 SEL0 800 Hz 400 Hz 200 Hz 100 Hz 50 Hz 12.5 Hz 6.25 Hz 1.56 Hz 0 0 16 Hz 16 Hz 8 Hz 4 Hz 2 Hz 2 Hz 2 Hz 2 Hz 0 1 8 Hz 8 Hz 4 Hz 2 Hz 1 Hz 1 Hz 1 Hz 1 Hz 1 0 4 Hz 4 Hz 2 Hz 1 Hz 0.5 Hz 0.5 Hz 0.5 Hz 0.5 Hz 1 1 2 Hz 2 Hz 1 Hz 0.5 Hz 0.25 Hz 0.25 Hz 0.25 Hz 0.25 Hz Oversampling Mode = Low Noise Low Power 0 0 16 Hz 16 Hz 8 Hz 4 Hz 2 Hz 0.5 Hz 0.5 Hz 0.
0x11: Portrait/Landscape Configuration Register This register enables the Portrait/Landscape function and sets the behavior of the debounce counter. 0x11: PL_CFG Register (Read/Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBCNTM PL_EN — — — — — — Table 25. PL_CFG Description DBCNTM PL_EN Debounce counter mode selection. Default value: 1 0: Decrements debounce whenever condition of interest is no longer valid. 1: Clears counter whenever condition of interest is no longer valid.
Table 29. Z-Lock Threshold Angles Z-Lock Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Threshold Angle 14° 18° 21° 25° 29° 33° 37° 42° Table 30.
Table 33. Trip Angles with Hysteresis for 45° Angle 5 6 7 6.4 ±17 ±21 ±24 62° 66° 69° 28° 24° 21° Motion and Freefall Embedded Function Registers The freefall/motion function can be configured in either Freefall or Motion Detection mode via the OAE configuration bit (0x15 bit 6). The freefall/motion detection block can be disabled by setting all three bits ZEFE, YEFE, and XEFE to zero.
0x15: FF_MT_CFG Freefall/Motion Configuration Register This is the Freefall/Motion configuration register for setting up the conditions of the freefall or motion function. 0x15: FF_MT_CFG Register (Read/Write) Bit 7 ELE Bit 6 OAE Bit 5 ZEFE Bit 4 YEFE Bit 3 XEFE Bit 2 — Bit 1 — Bit 0 — Table 34. FF_MT_CFG Description ELE Event Latch Enable: Event flags are latched into FF_MT_SRC register. Reading of the FF_MT_SRC register clears the event flag EA and all FF_MT_SRC bits. Default value: 0.
Table 35. Freefall/Motion Source Description EA ZHE ZHP YHE YHP XHE XHP Event Active Flag. Default value: 0. 0: No event flag has been asserted; 1: one or more event flag has been asserted. See the description of the OAE bit to determine the effect of the 3-axis event flags on the EA bit. Z Motion Flag. Default value: 0. 0: No Z Motion event detected, 1: Z Motion has been detected This bit reads always zero if the ZEFE control bit is set to zero Z Motion Polarity Flag. Default value: 0.
0x18: FF_MT_COUNT Debounce Register This register sets the number of debounce sample counts for the event trigger. 0x18: FF_MT_COUNT_Register (Read/Write) Bit 7 D7 Bit 6 D6 Bit 5 D5 Bit 4 D4 Bit 3 D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 Table 37. FF_MT_COUNT Description D[7:0] Count value. Default value: 0000_0000 This register sets the minimum number of debounce sample counts of continuously matching the detection condition user selected for the freefall, motion event.
High g Event on all 3-axis (Motion Detect) Count Threshold (a) FF Counter Value FFEA High g Event on all 3-axis (Motion Detect) DBCNTM = 1 Count Threshold Debounce Counter Value (b) EA High g Event on all 3-axis (Motion Detect) DBCNTM = 0 Count Threshold Debounce Counter Value (c) EA Figure 13. DBCNTM Bit Function MMA8451Q 34 Sensors Freescale Semiconductor, Inc.
6.5 Transient (HPF) Acceleration Detection For more information on the uses of the transient function please review Freescale application note, AN4071. This function is similar to the motion detection except that high-pass filtered data is compared. There is an option to disable the high-pass filter through the function. In this case the behavior is the same as the motion detection. This allows for the device to have 2 motion detection functions.
0x1F: TRANSIENT_THS Register The Transient Threshold register sets the threshold limit for the detection of the transient acceleration. The value in the TRANSIENT_THS register corresponds to a g value which is compared against the values of High-Pass Filtered Data. If the HighPass Filtered acceleration value exceeds the threshold limit, an event flag is raised and the interrupt is generated if enabled.
6.6 Single, Double and Directional Tap Detection Registers For more details of how to configure the tap detection and sample code, please refer to Freescale application note, AN4072. The tap detection registers are referred to as “Pulse”. 0x21: PULSE_CFG Pulse Configuration Register This register configures the event flag for the tap detection for enabling/disabling the detection of a single and double pulse on each of the axes.
0x23 - 0x25: PULSE_THSX, Y, Z Pulse Threshold for X, Y & Z Registers The pulse threshold can be set separately for the X, Y and Z axes. The PULSE_THSX, PULSE_THSY and PULSE_THSZ registers define the threshold which is used by the system to start the pulse detection procedure. 0x23: PULSE_THSX Register (Read/Write) Bit 7 0 Bit 6 THSX6 Bit 5 THSX5 Bit 4 THSX4 Bit 3 THSX3 Bit 2 THSX2 Bit 1 THSX1 Bit 0 THSX0 Bit 2 THSY2 Bit 1 THSY1 Bit 0 THSY0 Table 46.
Table 51. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 0 ODR (Hz) Max Time Range (s) Time Step (ms) Normal LPLN HighRes LP Normal LPLN HighRes LP 800 0.159 0.159 0.159 0.159 0.625 0.625 0.625 0.625 400 0.159 0.159 0.159 0.319 0.625 0.625 0.625 1.25 200 0.319 0.319 0.159 0.638 1.25 1.25 0.625 2.5 100 0.638 0.638 0.159 1.28 2.5 2.5 0.625 5 50 1.28 1.28 0.159 2.55 5 5 0.625 10 12.5 1.28 5.1 0.159 10.2 5 20 0.625 40 6.25 1.28 5.1 0.
0x28: PULSE_WIND Register (Read/Write) 0x28: PULSE_WIND Second Pulse Time Window Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WIND7 WIND6 WIND5 WIND4 WIND3 WIND2 WIND1 WIND0 Table 55. PULSE_WIND Description WIND[7:0] Second Pulse Time Window. Default value: 0000_0000.
6.7 Auto-WAKE/SLEEP Detection The ASLP_COUNT register sets the minimum time period of inactivity required to change current ODR value from the value specified in the DR[2:0] register to ASLP_RATE register value, provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2 register. See Table 59 for functional blocks that may be monitored for inactivity in order to trigger the “return to SLEEP” event.
6.8 Control Registers Note: Except for STANDBY mode selection, the device must be in STANDBY mode to change any of the fields within CTRL_REG1 (0x2A). 0x2A: CTRL_REG1 System Control 1 Register 0x2A: CTRL_REG1 Register (Read/Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ASLP_RATE1 ASLP_RATE0 DR2 DR1 DR0 LNOISE F_READ ACTIVE Table 61. CTRL_REG1 Description ASLP_RATE[1:0] Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode. Default value: 00.
0x2B: CTRL_REG2 System Control 2 Register 0x2B: CTRL_REG2 Register (Read/Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ST RST 0 SMODS1 SMODS0 SLPE MODS1 MODS0 Table 65. CTRL_REG2 Description Self-Test Enable. Default value: 0. 0: Self-Test disabled; 1: Self-Test enabled ST Software Reset. Default value: 0. 0: Device reset disabled; 1: Device reset enabled. RST SMODS[1:0] SLEEP mode power scheme selection. Default value: 00. See Table 66 and Table 67 Auto-SLEEP enable.
0x2C: CTRL_REG3 Interrupt Control Register 0x2C: CTRL_REG3 Register (Read/Write) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFO_GATE WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT — IPOL PP_OD Table 68. CTRL_REG3 Description FIFO_GATE WAKE_TRANS WAKE_LNDPRT WAKE_PULSE WAKE_FF_MT IPOL PP_OD 0: FIFO gate is bypassed. FIFO is flushed upon the system mode transitioning from WAKE to SLEEP mode or from SLEEP to WAKE mode. Default value: 0.
0x2E: CTRL_REG5 Register (Read/Write) 0x2E: CTRL_REG5 Interrupt Configuration Register Bit 7 Bit 6 INT_CFG_ASLP INT_CFG_FIFO Bit 5 Bit 4 Bit 3 Bit 2 INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE INT_CFG_FF_MT Bit 1 Bit 0 — INT_CFG_DRDY Table 70. Interrupt Configuration Register Description Interrupt Configuration Description INT1/INT2 Configuration. Default value: 0. 0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin INT1/INT2 Configuration.
Table 74.
Table 75. Accelerometer Output Data 14-bit Data Range ±2g (0.25 mg) Range ±4g (0.5 mg) Range ±8g (1.0 mg) 01 1111 1111 1111 1.99975g +3.9995g +7.999g 01 1111 1111 1110 1.99950g +3.9990g +7.998g … … … … 00 0000 0000 0001 0.00025g +0.0005g +0.001g 00 0000 0000 0000 0.00000g 0.00000g 0.000g 11 1111 1111 1111 -0.00025g -0.0005g -0.001g … … … … 10 0000 0000 0001 -1.99975g -3.9995g -7.999g 10 0000 0000 0000 -2.00000g -4.0000g -8.000g 8-bit Data Range ±2g (15.
PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN MMA8451Q 48 Sensors Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN MMA8451Q Sensors Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS CASE 2077-02 ISSUE A 16-LEAD QFN MMA8451Q 50 Sensors Freescale Semiconductor, Inc.
Table 76. Revision History Revision number Revision date Description of changes 7 03/2012 • Table 2. Updated Typ values for Sensitivity Accuracy from 2.5% to 2.64%; Zero-g Level Offset Accuracy from ±20 mg to ±17 mg and Zero-g Level Offset Accuracy Post Board Mount from ±30 mg to ±20 mg. • Table 4. Updated Min value from 50 μs to 0.05 μs and added Max value of 0.9 μs • Added Table 8. Features of the MMA845xQ devices. • Removed FIFO paragraph at the end of Section 6.1.
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