Freescale Semiconductor Data Sheet MPC5200 Rev. 4, 01/2005 MPC5200 Data Sheet NOTE The information in this document is subject to change. For the latest data on the MPC5200, visit www.freescale.com and proceed to the MPC5200 Product Summary Page. 1 Overview The MPC5200 integrates a high performance MPC603e series G2_LE core with a rich set of peripheral functions focused on communications and systems integration. The G2_LE core design is based on the PowerPCTM core architecture.
Features 2 Features Key features are shown below.
Features • • • • • • • — CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97 — Full duplex SPI mode — IrDA mode from 2400 bps to 4 Mbps Fast Ethernet Controller (FEC) — Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface Universal Serial Bus Controller (USB) — USB Revision 1.1 Host — Open Host Controller Interface (OHCI) — Integrated USB Hub, with two ports. Two Inter-Integrated Circuit Interfaces (I2C) Serial Peripheral Interface (SPI) Dual CAN 2.
Features • • Test/Debug features — JTAG (IEEE 1149.1 test access port) — Common On-chip Processor (COP) debug port On-board PLL and clock generation Figure 1 shows a simplified MPC5200 block diagram. MPC5200 Data Sheet, Rev.
Freescale Semiconductor Reset / Clock Generation JTAG / COP Interface CommBus G2_LE Core 603 SDRAM / DDR Memory Controller SDRAM / DDR ATA Host Controller PCI Bus Controller Local Plus Controller GPIO/Timers Interrupt Controller System Functions Real-Time Clock Systems Interface Unit (SIU) Local Bus Features MSCAN 2x J1850 USB 2x SPI I2C 2x BestComm DMA Ethernet SRAM 16K PSC 6x Figure 1. Simplified Block Diagram—MPC5200 MPC5200 Data Sheet, Rev.
Electrical and Thermal Characteristics 3 Electrical and Thermal Characteristics 3.1 DC Electrical Characteristics 3.1.1 Absolute Maximum Ratings The tables in this section describe the MPC5200 DC Electrical characteristics. Table 1 gives the absolute maximum ratings. Table 1. Absolute Maximum Ratings1 Characteristic Symbol Min Max Unit SpecID Supply voltage - G2_LE core and peripheral logic VDD_CORE –0.3 1.8 V D1.1 VDD_IO, VDD_MEM_IO –0.3 3.6 V D1.
Electrical and Thermal Characteristics Table 2. Recommended Operating Conditions (continued) Characteristic Input voltage - memory I/O buffers (DDR) Ambient operating temperature range Symbol Min1 Max(1) VinDDR 0 2 TA Unit SpecID VDD_MEM_IODDR V D2.9 +85 oC D2.10 -40 Extended ambient operating temperature range3 TAext -40 +105 o C D2.11 Die junction operating temperature range Tj -40 +115 oC D2.12 Tjext -40 +125 oC D2.
Electrical and Thermal Characteristics Table 3. DC Electrical Specifications (continued) Characteristic Condition Symbol Min Max Unit SpecID Vin = 0 or VDD_IO/VDD_IO_MEMSDR IIN — +10 µA D3.13 Input leakage current SYS_XTAL_IN Vin = 0 or VDD_IO IIN — +10 µA D3.14 Input leakage current RTC_XTAL_IN Vin = 0 or VDD_IO IIN — +10 µA D3.15 PULLUP VDD_IO Vin = 0 IINpu 40 109 µA D3.16 PULLUP_MEM VDD_IO_MEMSDR Vin = 0 IINpu 41 111 µA D3.
Electrical and Thermal Characteristics Table 4. Drive Capability of MPC5200 Output Pins (continued) Driver Type Supply Voltage IOH IOL Unit SpecID VDD_IO = 3.3V - 8 mA D3.27 DRV16_MEM VDD_IO_MEM = 3.3V 16 16 mA D3.28 DRV16_MEM VDD_IO_MEM = 2.5V 16 16 mA D3.29 VDD_IO = 3.3V 16 16 mA D3.30 DRV8_OD PCI 3.1.4 Electrostatic Discharge CAUTION This device contains circuitry that protects against damage due to high-static voltage or electrical fields.
Electrical and Thermal Characteristics where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5200 processor must not exceed the value, which would cause the maximum junction temperature to be exceeded. P total = P core + P analog + P IO Table 6.
Electrical and Thermal Characteristics 3.1.6 Thermal Characteristics Table 7. Thermal Resistance Data Rating Value Unit Notes SpecID RθJA 30 °C/W 1,2 D6.1 Junction to Ambient Natural Convection Single layer board (1s) Junction to Ambient Natural Convection Four layer board (2s2p) RθJMA 22 °C/W 1,3 D6.2 Junction to Ambient (@200 ft/min) Single layer board (1s) RθJMA 24 °C/W 1,3 D6.3 Junction to Ambient (@200 ft/min) Four layer board (2s2p) RθJMA 19 °C/W 1,3 D6.
Electrical and Thermal Characteristics Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: R θJA = R θJC +R θCA Eqn. 2 where: R θJA = junction to ambient thermal resistance (°C/W) R θJC = junction to case thermal resistance (°C/W) R θCA = case to ambient thermal resistance (°C/W) R θJC is device related and cannot be influenced by the user.
Electrical and Thermal Characteristics There is a separate oscillator for the independent Real-Time Clock (RTC) system. The MPC5200 clock generation uses two phase locked loop (PLL) blocks. • The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration. • The G2_LE core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry.
Electrical and Thermal Characteristics 3.2.4 G2_LE Core PLL Electrical Characteristics The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL. Table 11. G2_LE PLL Specifications Characteristic Symbol Notes Min Typical Max Unit SpecID G2_LE frequency fcore 1 50 — 550 MHz O4.1 G2_LE cycle time tcore (1) 2.85 — 40.0 ns O4.2 G2_LE VCO frequency fVCOcore (1) 400 — 1200 MHz O4.
Electrical and Thermal Characteristics • • • • • TA = -40 to 85 oC Tj = -40 to 115 oC VDD_CORE = 1.42 to 1.58 V VDD_IO = 3.0 to 3.6 V Input conditions: All Inputs: tr, tf <= 1 ns Output Loading: All Outputs: 50 pF 3.3.1 AC Operating Frequency Data Table 12 provides the operating frequency information for the MPC5200. Table 12. Clock Frequencies 3.3.2 Min Max Units SpecID 1 G2_LE Processor Core — 400 MHz A1.1 2 SDRAM Clock — 133 MHz A1.2 3 XL Bus Clock — 133 MHz A1.
Electrical and Thermal Characteristics Table 13. SYS_XTAL_IN Timing Sym Description t CYCLE SYS_XTAL_IN cycle time.1 t RISE SYS_XTAL_IN rise time. t FALL SYS_XTAL_IN fall time. ).2 Min Max Units SpecID 28.6 64.1 ns A2.1 — 5.0 ns A2.2 — 5.0 ns A2.3 40.0 60.0 % A2.4 t DUTY SYS_XTAL_IN duty cycle (measured at V M CV IH SYS_XTAL_IN input voltage high 2.0 — V A2.5 CV IL SYS_XTAL_IN input voltage low — 0.8 V A2.
Electrical and Thermal Characteristics Table 15. Reset Rise / Fall Timing Description Min Max Unit SpecID PORRESET fall time — 1 ms A3.4 PORRESET rise time — 1 ms A3.5 HRESET fall time — 1 ms A3.6 HRESET rise time — 1 ms A3.7 SRESET fall time — 1 ms A3.8 SRESET rise time — 1 ms A3.9 For additional information, see the MPC5200 User Manual [1]. NOTE Make sure that the PORRESET does not carry any glitches. The MPC5200 has no filter to prevent them from getting into the chip.
Electrical and Thermal Characteristics NOTE Beware of changing the values on the pins of the reset configuration word after the deassertion of PORRESET. This may cause problems because it may change the internal clock ratios and so extend the PLL locking process. 3.3.
Electrical and Thermal Characteristics Table 16. External interrupt latencies (continued) Interrupt Type Standard GPIO Interrupts GPIO WakeUp Interrupts Pin Name Clock Cycles Reference Clock Core Interrupt SpecID GPIO_PSC3_4 12 IP_CLK normal (int) A4.7 GPIO_PSC3_5 12 IP_CLK normal (int) A4.8 GPIO_PSC3_8 12 IP_CLK normal (int) A4.9 GPIO_USB_9 12 IP_CLK normal (int) A4.10 GPIO_ETHI_4 12 IP_CLK normal (int) A4.11 GPIO_ETHI_5 12 IP_CLK normal (int) A4.
Electrical and Thermal Characteristics 3.3.5 SDRAM 3.3.5.1 Memory Interface Timing-Standard SDRAM Read Command Table 18. Standard SDRAM Memory Read Timing Sym Description Min Max Units SpecID MEM_CLK period 7.5 — ns A5.1 tvalid Control Signals, Address and MBA Valid after rising edge of MEM_CLK — tmem_clk*0.5+0.4 ns A5.2 thold Control Signals, Address and MBA Hold after rising edge of MEM_CLK tmem_clk*0.5 — ns A5.
Electrical and Thermal Characteristics Table 19. Standard SDRAM Write Timing Sym Description Min Max Units SpecID MEM_CLK period 7.5 — ns A5.8 tvalid Control Signals, Address and MBA Valid after rising edge of MEM_CLK — tmem_clk*0.5+0.4 ns A5.9 thold Control Signals, Address and MBA Hold after rising edge of MEM_CLK tmem_clk*0.5 — ns A5.10 — tmem_clk*0.25+0.4 ns A5.11 tmem_clk*0.25-0.7 — ns A5.
Electrical and Thermal Characteristics Table 20. DDR SDRAM Memory Read Timing Sym Min Max Units SpecID MEM_CLK period 7.5 — ns A5.15 tvalid Control Signals, Address and MBA valid after rising edge of MEM_CLK — tmem_clk*0.5+0.4 ns A5.16 thold Control Signals, Address and MBA hold after rising edge of MEM_CLK tmem_clk*0.5 — ns A5.17 tdata_sample_max Read Data sample window — 4.591 ns A5.18 tdata_sample_min Read Data sample window 1.552 — ns A5.
Electrical and Thermal Characteristics MEM_CLK MEM_CLK tvalid thold Active Control Signals NOP READ NOP NOP NOP NOP NOP MDQS (Data Strobe) tdata_valid_min tdata_valid_max MDQ (Data) Sample position A tdata_sample_min tdata_sample_max Read Data Sample Window MDQS (Data Strobe) tdata_valid_min tdata_valid_max MDQ (Data) 0.
Electrical and Thermal Characteristics 8.34 delay [ns] tdata_valid_max 4.59 Memory Data valid window Possible sample time over PVT for one selected Tap delay tdata_sample_min tdata_sample_min tdata_valid_min 1.55 Working Tap Delay range for sample position B 0 Working Tap Delay range for sample position A selected Tap delay 31 Tap delay number Figure 8.
Electrical and Thermal Characteristics 3.3.5.4 Memory Interface Timing-DDR SDRAM Write Command Table 21. DDR SDRAM Memory Write Timing Sym Description tmem_clk tDQSS Min Max Units SpecID MEM_CLK period 7.5 — ns A5.20 Delay from write command to first rising edge of MDQS — tmem_clk+0.4 ns A5.
Electrical and Thermal Characteristics Tcyc 0.5Vcc 0.4Vcc PCI CLK 0.3Vcc T high 0.6Vcc T low 0.4Vcc, p-to-p (minimum) 0.2Vcc Figure 10. PCI CLK Waveform Table 22. PCI CLK Specifications 66 MHz Sym 33 MHz Description Units Notes SpecID 30 ns 1,3 A6.1 11 ns Min Max Min 30 Tcyc PCI CLK Cycle Time 15 Thigh PCI CLK High Time 6 t low PCI CLK Low Time 6 - PCI CLK Slew Rate 1.5 Max A6.2 A6.3 4 1 4 V/ns 2 A6.4 NOTES: 1.
Electrical and Thermal Characteristics Table 23. PCI Timing Parameters 66 MHz Sym 33 MHz Description Units Notes SpecID 11 ns 1,2,3 A6.5 12 ns 1,2,3 A6.6 ns 1 A6.7 ns 1 A6.
Electrical and Thermal Characteristics 3.3.7 Local Plus Bus The Local Plus Bus is the external bus interface of the MPC5200. Maximum eight configurable Chip-selects are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz.
Electrical and Thermal Characteristics Table 24. Non-MUXed Mode Timing (continued) Sym Description Min Max Units Notes SpecID - 0.8 ns 4 A7.16 t14 TS assertion before CS assertion t15 TS pulse width tPCIck tPCIck ns 4 A7.17 t16 TSIZ valid before CS assertion tIPBIck - ns 5 A7.18 t17 TSIZ hold after CS negation tIPBIck - ns 5 A7.19 NOTES: 1. ACK can shorten the CS pulse width. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX.
Electrical and Thermal Characteristics 3.3.7.2 Burst Mode Table 25. Burst Mode Timing Sym Description t CSA PCI CLK to CS assertion t CSN PCI CLK to CS negation t1 CS pulse width Min Max Units Notes SpecID - 1.8 ns A7.20 A7.21 - 1.8 ns (1+WS+4LB*2*(32/DS))* (1+WS+4LB*2*(32/DS)) ns tPCIck *tPCIck tIPBIck tPCIck ns A7.23 1,2 A7.22 t2 ADDR valid before CS assertion t3 ADDR hold after CS negation - -0.7 ns A7.24 t4 OE assertion before CS assertion - 0.4 ns A7.
Electrical and Thermal Characteristics PCI CLK CS[x] t1 t3 t2 ADDR t5 t4 OE t6 t7 R/W t8 t10 DATA (rd) t9 t11 t12 ACK t14 t15 t13 TS Figure 13. Timing Diagram—Burst Mode MPC5200 Data Sheet, Rev.
Electrical and Thermal Characteristics 3.3.7.3 MUXed Mode Table 26. MUXed Mode Timing Sym Description Min Max Units t CSA PCI CLK to CS assertion - 1.8 ns A7.15 t CSN PCI CLK to CS negation - 1.8 ns A7.16 tALEA PCI CLK to ALE assertion - 1 ns A7.16 t1 ALE assertion before Address, Bank, TSIZ assertion - 0.8 ns A7.17 t2 CS assertion before Address, Bank, TSIZ negation - 0.7 ns A7.18 t3 CS assertion before Data wr valid - 0.7 ns A7.
Electrical and Thermal Characteristics PCI CLK t1 t2 t4 AD[31,27] (wr) Data AD[30:28] (wr) TSIZ[0:2] bits Data AD[26:25] (wr) Bank[0:1] bits Data AD[24:0] (wr) Address[7:31] Data t3 t5 AD[31:0] (rd) t6 Data t7 ALE Address latch t8 TS t9 CSx OE t10 t11 RW t12 ACK t13 Address tenure Data tenure Figure 14. Timing Diagram—MUXed Mode 3.3.8 ATA The MPC5200 ATA Controller is completely software programmable.
Electrical and Thermal Characteristics The MPC5200 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes. • Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that required by the ATA-4 specification. • Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that required by the ATA-4 specification.
Electrical and Thermal Characteristics CS[0]/CS[3]/DA[2:0] t2 t9 t1 DIOR/DIOW t8 t0 t3 t4 WDATA t5 t6 RDATA tA tB IORDY Figure 15. PIO Mode Timing Table 28. Multiword DMA Timing Specifications Multiword DMA Timing Parameters Min/Max Mode 0(ns) Mode 1(ns) Mode 2(ns) SpecID t0 Cycle Time min 480 150 120 A8.12 tC DMACK to DMARQ delay max — — — A8.13 tD DIOR/DIOW pulse width (16-bit) min 215 80 70 A8.14 tE DIOR data access max 150 60 50 A8.
Electrical and Thermal Characteristics t0 DMARQ (Drive) tL tC DMACK (Host) tI tD tJ tK DIOR DIOW (Host) tE RDATA (Drive) tS tF WDATA (Host) tH tG NOTE: The directionof signalassertionis towardsthe top of the page, and the direction of negation is towards the bottom of the page, irrespective of the electrical properties of the signal. Figure 16. Multiword DMA Timing Table 29.
Electrical and Thermal Characteristics Table 29. Ultra DMA Timing Specification (continued) Name (t) LI (t) MLI MODE 0 (ns) MODE 1 (ns) MODE 2 (ns) Min Max Min Max Min Max 0 150 0 150 0 150 20 — 20 — 20 — Comment Limited Interlock time.1,2 Interlock time with SpecID A8.34 minimum.1,2 A8.35 1,2 A8.36 (t) UI 0 — 0 — 0 — Unlimited interlock time. (t) AZ — 10 — 10 — 10 Maximum time allowed for output drivers to release from being asserted or negated A8.
Electrical and Thermal Characteristics DMARQ (device) t UI DMACK (device) t ACK t ENV t FS t ZAD STOP (host) t ACK t ENV HDMARDY (host) t FS t ZAD t ZIORDY DSTROBE (device) t DVS t AZ t DVH DD(0:15) t ACK DA0, DA1, DA2, CS[0:1]1 Figure 17. Timing Diagram—Initiating an Ultra DMA Data In Burst t 2CYC t CYC t CYC t 2CYC DSTROBE at device tDVH tDVS tDVH tDVS tDVH DD(0:15) at device DSTROBE at host tDH tDS tDH tDS tDH DD(0:15) at host Figure 18.
Electrical and Thermal Characteristics DMARQ (device) DMARQ (host) t RP STOP (host) t SR HDMARDY (host) t RFS DSTROBE (device) DD[0:15] (device) Figure 19. Timing Diagram—Host Pausing an Ultra DMA Data In Burst DMARQ (device) DMACK (host) t LI t MLI t LI t ACK STOP (host) tLI HDMARDY (host) DSTROBE (device) t ACK t SS t IORDYZ t ZAH t AZ t DVS t DVH CRC DD[0:15] t ACK DA0,DA1,DA2, CS[0:1] Figure 20. Timing Diagram—Drive Terminating Ultra DMA Data In Burst MPC5200 Data Sheet, Rev.
Electrical and Thermal Characteristics DMARQ (device) t LI DMACK (host) t RP t MLI t ZAH t ACK STOP (host) tACK t AZ HDMARDY (host) t RFS t LI t MLI DSTROBE (device) t IORDYZ t DVS t DVH DD[0:15] CRC t ACK DA0,DA1,DA2, CS[0:1] Figure 21. Timing Diagram—Host Terminating Ultra DMA Data In Burst MPC5200 Data Sheet, Rev.
Electrical and Thermal Characteristics DMARQ (device) tUI DMACK (host) tACK tENV STOP (host) tLI tZIORDY tUI DDMARDY (host) tACK HSTROBE (device) tDVS tDVH DD[0:15] (host) tACK DA0,DA1,DA2, CS[0:1] Figure 22. Timing Diagram—Initiating an Ultra DMA Data Out Burst t 2CYC t CYC t CYC t 2CYC HSTROBE (host) t DVS t DVH t DVS t DVH t DVH DD[0:15] (host) HSTROBE (device) t DH t DS t DS t DH t DH DD[0:15] (device) Figure 23.
Electrical and Thermal Characteristics t RP DMARQ (device) DMACK (host) STOP (host) t SR DDMARDY (device) t RFS HSTROBE DD[0:15] (host) Figure 24. Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst DMARQ (device) t LI t MLI DMACK (host) t SS t ACK t LI STOP (host) t LI t IORDYZ DDMARDY (device) tACK HSTROBE (host) t DVS DD[0:15] (host) t DVH CRC t ACK DA0,DA1,DA2, CS[0:1] Figure 25. Timing Diagram—Host Terminating Ultra DMA Data Out Burst MPC5200 Data Sheet, Rev.
Electrical and Thermal Characteristics DMARQ (device) DMACK (host) t LI t MLI t ACK STOP (host) t RP t IORDYZ DDMARDY (device) t RFS t LI t MLI t ACK HSTROBE (host) t DVS DD[0:15] (host) t DVH CRC t ACK DA0,DA1,DA2, CS[0:1] Figure 26. Timing Diagram—Drive Terminating Ultra DMA Data Out Burst Table 30. Timing Specification ata_isolation Sym Description Min Max Units SpecID 1 ata_isolation setup time 7 - IP Bus cycles A8.48 2 ata_isolation hold time - 19 IP Bus cycles A8.
Electrical and Thermal Characteristics 3.3.9 Ethernet AC Test Timing Conditions: • Output Loading All Outputs: 25 pF Table 31. MII Rx Signal Timing Sym Description Min Max Unit SpecID M1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup 10 — ns A9.1 M2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold 10 — ns A9.2 M3 RX_CLK pulse width high 35% 65% RX_CLK Period1 A9.3 M4 RX_CLK pulse width low 35% 65% RX_CLK Period1 A9.
Electrical and Thermal Characteristics Table 32. MII Tx Signal Timing Sym Description Min Max Unit SpecID 0 25 ns A9.5 M5 TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER Delay M6 TX_CLK pulse width high 35% 65% TX_CLK Period1 A9.6 M7 TX_CLK pulse width low 35% 65% TX_CLK Period(1) A9.7 NOTES: 1 the TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g.
Electrical and Thermal Characteristics Table 34. MII Serial Management Channel Signal Timing Sym Description Min Max Unit SpecID M9 MDC falling edge to MDIO output delay 0 25 ns A9.9 M10 MDIO (input) to MDC rising edge setup 10 — ns A9.10 M11 MDIO (input) to MDC rising edge hold 10 — ns A9.11 M12 MDC pulse width high1 160 — ns A9.12 M13 MDC pulse width low(1) 160 — ns A9.13 M14 MDC period2 400 — ns A9.
Electrical and Thermal Characteristics NOTE Output timing was specified at a nominal 50 pF load. 2 USB_OE 3 4 USB_TXN 1 1 4 3 USB_TXP Figure 32. Timing Diagram—USB Output Line 3.3.11 SPI Table 36. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) Sym 1 Description Cycle time 2 Clock high or low time 3 Slave select clock delay 4 Min Max Units SpecID 4 1024 IP-Bus Cycle1 A11.1 1 2 512 IP-Bus Cycle A11.2 15.0 — ns A11.
Electrical and Thermal Characteristics 1 10 SCK (CLKPOL=0) Output 2 2 11 SCK (CLKPOL=1) Output 11 10 9 8 3 SS Output 5 4 MOSI Output 6 6 MISO Input 7 7 Figure 33. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) Sym 1 Description Cycle time Min Max Units SpecID 4 1024 IP-Bus Cycle1 A11.12 1 2 512 IP-Bus Cycle A11.13 15.0 — ns A11.14 Output Data valid after Slave Select (SS) — 50.0 ns A11.
Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 3 9 SS Input 6 7 MOSI Input 4 5 MISO Output Figure 34. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) Sym 1 Description Cycle time Min Max Units SpecID 4 1024 IP-Bus Cycle1 A11.21 2 512 Cycle1 A11.22 15.0 — ns A11.23 — 20.0 ns A11.
Electrical and Thermal Characteristics 1 9 SCK (CLKPOL=0) Output 2 2 10 SCK (CLKPOL=1) Output 10 9 7 3 8 SS Output 4 MOSI Output 5 MISO Input 6 Figure 35. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 Cycle time 4 1024 IP-Bus Cycle1 A11.31 2 Clock high or low time 2 512 IP-Bus Cycle1 A11.32 3 Slave select clock delay 15.0 — ns A11.
Electrical and Thermal Characteristics 1 SCK (CLKPOL=0) Input 2 2 SCK (CLKPOL=1) Input 8 7 3 SS Input 5 6 MOSI Input 4 MISO Output Figure 36. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 3.3.12 MSCAN The CAN functions are available as RX and TX pins at normal IO pads (I2C1+GPTimer or PSC2). There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured. 3.3.13 I2C Table 40.
Electrical and Thermal Characteristics Table 41. I2C Output Timing Specifications—SCL and SDA Sym 1 1 21 3 2 4 1 Description Min Max Units SpecID Cycle3 A13.8 Start condition hold time 6 — IP-Bus Clock low period 10 — IP-Bus Cycle3 A13.9 SCL/SDA rise time — 7.9 ns A13.10 Data hold time 7 — 51 SCL/SDA fall time — 7.9 ns A13.12 61 Clock high time 10 — IP-Bus Cycle3 A13.13 — IP-Bus Cycle3 A13.14 Cycle3 A13.15 A13.
Electrical and Thermal Characteristics 3.3.15 PSC 3.3.15.1 Codec Mode (8,16,24 and 32-bit) / I2S Mode Table 42. Timing Specifications—8,16, 24 and 32-bit CODEC / I2S Master Mode Sym Description Min Typ Max Units SpecID 40.0 — — ns A15.1 1 Bit Clock cycle time, programmed in CCS register 2 Clock pulse width — 50 — %1 A15.2 3 Bit Clock fall time — — 7.9 ns A15.3 4 Bit Clock rise time — — 7.9 ns A15.4 5 FrameSync valid after clock edge — — 8.4 ns A15.
Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Output 2 3 2 4 BitClk (CLKPOL=1) Output 4 5 Frame (SyncPol = 1) Output Frame (SyncPol = 0) Output 3 6 7 TxD Output 8 RxD Input Figure 38. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Master Mode Table 43. Timing Specifications — 8,16, 24, and 32-bit CODEC / I2S Slave Mode Sym 1 Description Bit Clock cycle time Min Typ Max Units SpecID 40.0 — — ns A15.9 A15.10 2 Clock pulse width — 50 — %1 3 FrameSync setup time 1.
Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input 2 2 BitClk (CLKPOL=1) Input 3 Frame (SyncPol = 1) Input Frame (SyncPol = 0) Input 4 TxD Output 5 RxD Input 6 Figure 39. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Slave Mode 3.3.15.2 AC97 Mode Table 44. Timing Specifications — AC97 Mode Sym Description Min Typ Max Units SpecID 1 Bit Clock cycle time — 81.4 — ns A15.15 2 Clock pulse high time — 40.7 — ns A15.16 3 Clock pulse low time — 40.7 — ns A15.
Electrical and Thermal Characteristics 1 BitClk (CLKPOL=0) Input 4 Sync (SyncPol = 1) Output 5 3 2 Sdata_out Output 6 7 Sdata_in Input Figure 40. Timing Diagram — AC97 Mode 3.3.15.3 IrDA Mode Table 45. Timing Specifications — IrDA Transmit Line Sym Description Min Max Units SpecID 1 Pulse high time, defined in the IrDA protocol definition 0.125 10000 µs A15.22 2 Pulse low time, defined in the IrDA protocol definition 0.125 10000 µs A15.23 3 Transmitter rising time — 7.
Electrical and Thermal Characteristics 3.3.15.4 SPI Mode Table 46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.26 2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.27 3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A15.28 4 Output Data valid after Slave Select (SS) — 8.9 ns A15.29 5 Output Data valid after SCK — 8.9 ns A15.
Electrical and Thermal Characteristics Table 47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.37 2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.38 3 Slave select clock delay 1.0 — ns A15.39 4 Input Data setup time 1.0 — ns A15.40 5 Input Data hold time 1.0 — ns A15.41 6 Output data valid after SS — 14.0 ns A15.
Electrical and Thermal Characteristics Table 48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.46 2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.47 3 Slave select clock delay, programable in the PSC CCS register 30.0 — ns A15.48 4 Output data valid — 8.9 ns A15.49 5 Input Data setup time 6.0 — ns A15.50 6 Input Data hold time 1.0 — ns A15.
Electrical and Thermal Characteristics Table 49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1) Sym Description Min Max Units SpecID 1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.56 2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.57 3 Slave select clock delay 0.0 — ns A15.58 4 Output data valid — 14.0 ns A15.59 5 Input Data setup time 2.0 — ns A15.60 6 Input Data hold time 1.0 — ns A15.61 7 Slave disable lag time 0.
Electrical and Thermal Characteristics 3.3.16 GPIOs and Timers 3.3.16.1 General and Asynchronous Signals The MPC5200 contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are asynchronous to the system clock. The following numbers are provided for test and validation purposes only, and they assume a 133 MHz internal bus frequency. Figure 46 shows the GPIO Timing Diagram. Table 50 gives the timing specifications. Table 50.
Electrical and Thermal Characteristics 3.3.17 IEEE 1149.1 (JTAG) AC Specifications Table 51. JTAG Timing Specification Sym Characteristic Min Max Unit SpecID — TCK frequency of operation. 0 25 MHz A17.1 1 TCK cycle time. 40 — ns A17.2 2 TCK clock pulse width measured at 1.5V. 1.08 — ns A17.3 3 TCK rise and fall times. 0 3 ns A17.4 10 — ns A17.5 5 — ns A17.6 5 — ns A17.7 15 — ns A17.8 0 30 ns A17.9 0 30 ns A17.
Electrical and Thermal Characteristics TCK 4 TRST 5 Numbers shown reference Table 51. Figure 48. Timing Diagram—JTAG TRST TCK 6 DATA INPUTS 7 INPUT DATA VALID 8 DATA OUTPUTS OUTPUT DATA VALID 9 DATA OUTPUTS Numbers shown reference Table 51. Figure 49. Timing Diagram—JTAG Boundary Scan TCK 10 TDI, TMS 11 INPUT DATA VALID 12 TDO OUTPUT DATA VALID 13 TDO Numbers shown reference Table 51. Figure 50. Timing Diagram—Test Access Port MPC5200 Data Sheet, Rev.
Package Description 4 Package Description 4.1 Package Parameters The MPC5200 uses a 27 mm x 27 mm TE-PBGA package. The package parameters are as provided in the following list: • Package outline 27 mm x 27 mm • Interconnects 272 • Pitch 1.27 mm 4.2 Mechanical Dimensions Figure 51 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200, 272 TE-PBGA package. MPC5200 Data Sheet, Rev.
Package Description PIN A1 INDEX D C 0.2 4X A 272X 0.2 A E 0.35 A E2 D2 0.2 M NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM A. 4. PRIMARY DATUM A AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
Package Description 4.3 Pinout Listings See details in the MPC5200 User Manual [1]. Table 52.
Package Description Table 52.
Package Description Table 52.
Package Description Table 52.
Package Description Table 52.
System Design Information Table 52. MPC5200 Pinout Listing (continued) Name Alias Type Power Supply Output Driver Type Input Type Pull-up/ down Power and Ground VDD_IO - VDD_MEM_IO - VDD_CORE - VSS_IO/CORE - SYS_PLL_AVDD - CORE_PLL_AVDD - NOTES: All “open drain” outputs of the MPC5200 are actually regular three-state output drivers with the output data tied low and the output enable controlled.
DC Power Supply Voltage System Design Information 3.3V VDD_IO, VDD_IO_MEM (SDR) 2.5V VDD_IO_MEM (DDR) 1.5V 1 VDD_CORE, PLL_AVDD 2 0 Time Note: 1. VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V at any time, including power-up. 2. It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM up to 0.9 V then separate for completion of ramps. 3.
System Design Information VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator. 5.1.2 Power Down Sequence If VDD_CORE/PLL_AVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state.
System Design Information 5.3.2 Pull-up Requirements for the PCI Control Lines If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local Bus specification [4]. This is also required for MOST/Graphics and Large Flash Mode. PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus.
System Design Information PORRESET required assertion of JTAG_TRST optional assertion of JTAG_TRST JTAG_TRST Figure 54. PORRESET vs. JTAG_TRST 5.4.1.2 Connecting JTAG_TRST The wiring of the JTAG_TRST depends on the existence of a board-related debug interface (see Table 53 below). Normally this interface is implemented, using a COP (common on-chip processor) connector.
System Design Information Table 53. COP/BDM Interface Signals (continued) BDM Pin # MPC5200 I/O Pin BDM Connector Internal PullUp/Down External PullUp/Down I/O 1 8 — N/C — — — 7 JTAG_TCK tck 100k Pull-Up 10k Pull-Up O 6 — VDD 2 — — — 5 See Note 3. halted 3 — — I 4 JTAG_TRST trst 100k Pull-Up 10k Pull-Up O 3 JTAG_TDI tdi 100k Pull-Up 10k Pull-Up O qack 4 — — O tdo — — I 2 1 See Note 4.
System Design Information PORRESET PORRESET COP Header 13 11 10Kohm HRESET SRESET 1 2 3 4 5 6 7 8 9 10 11 12 13 K 15 16 4 62 Key 3 SRESET VDD JTAG_TRST 10Kohm TMS VDD JTAG_TMS 12 7 VDD TRST Key 14 9 MPC5200 VDD 10Kohm 10Kohm 16 COP Connector Physical Pinout HRESET 10Kohm TCK VDD VDD JTAG_TCK 10Kohm TDI VDD JTAG_TDI 15 1 CKSTP_OUT TEST_SEL_0 TDO JTAG_TDO halted 53 NC qack 4 2 NC 10 NC 8 NC Figure 55. COP Connector Diagram MPC5200 Data Sheet, Rev.
System Design Information 5.4.2.2 Boards without COP connector If the JTAG interface is not used, JTAG_TRST should be tied to PORRESET, so that it is asserted when the system reset signal (PORRESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 56 shows the connection of the JTAG interface without COP connector.
Ordering Information 6 Ordering Information Table 54. Ordering Information Part Number 7 Speed Ambient Temp Qualification MPC5200BV400 400 0C to 70C Commercial MPC5200CBV266 266 -40C to 85C Industrial MPC5200CBV400 400 -40C to 85C Industrial SPC5200CBV400 400 -40C to 85C Automotive - AEC Document Revision History Table 55 provides a revision history for this hardware specification. Table 55. Document Revision History Rev. No. Substantive Change(s) 0.
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