Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsOL2381AHN/C0B,515

1. General description

A highly integrated single-chip transceiver solution, the OL2381 is ideally suited to

telemetry applications operating in the ISM/SRD bands. The small form factor, low power

consumption and wide supply voltage range make this device suitable for use in battery

powered, handheld devices and their counter parts.

The device utilizes a fully integrated, programmable fractional-N PLL (including loop filter)

to control the Local Oscillator (LO), thus supporting multi-channel operation and

frequency hopping schemes. This feature also allows programmable frequency steps for

crystal (XTAL) drift compensation.

The device can employ ASK, FSK or GFSK type modulation. The ASK modulation

characteristics are fully programmable by varying the power amplifier output power in

accordance with the TX data. The FSK modulation utilizes the fractional-N PLL capability

to precisely modulate the LO frequency with the TX data (in loop modulation). Relaxed

narrow band applications can utilize an on-chip GFSK type modulation to improve the

spectral occupancy.

The device is based on a low IF direct conversion receiver architecture, with on-chip IF

filtering and programmable channel bandwidth. After filtering and amplification the

quadrature signals are digitized, demodulated and processed in the digital domain.

Baseband processing of the received signal comprises a demodulator, a data-slicer and

clock recovery followed by a Manchester decoder. Automated signal signature recognition

units are available to allow simple, fast and reliable data reception.

The device is controlled via a three-wire serial interface (SPI) with data input and output,

data clock and interface enable. The interface can be configured to a full SPI interface

with separate data and clock pins. Additional pins are available to access internal signals

in real-time.

2. Features and benefits

 Highly integrated solution for the 315/434/868/915 MHz band

 Very few external components required

 Complies with ETSI EN300-220/FCC part 15 standards

 Near zero-IF RX architecture

 On-chip channel filtering with automatic calibration supported to provide stable cut-off

frequencies and filter roll-off

 Multi-channel TX and RX operation by fully integrated fractional-N PLL with on-chip

loop filter

OL2381

Highly integrated single-chip sub 1 GHz RF transceiver

Rev. 1 — 30 November 2011 Product data sheet

Summary of content (152 pages)

PAGE 1
OL2381 Highly integrated single-chip sub 1 GHz RF transceiver Rev. 1 — 30 November 2011 Product data sheet 1. General description A highly integrated single-chip transceiver solution, the OL2381 is ideally suited to telemetry applications operating in the ISM/SRD bands. The small form factor, low power consumption and wide supply voltage range make this device suitable for use in battery powered, handheld devices and their counter parts.
PAGE 2
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver  Automatic VCO sub-band selection and calibration to reduce PLL loop bandwidth variation  Programmable ASK/FSK modulation with Manchester codec  Programmable transmitter output power (20 dBm to +10 dBm), stabilized with onboard PA regulator  Digital RSSI with a configurable threshold  Onboard Signal Signature Recognition Unit (SSRU) with Preamble Pattern Recognition (PPR)  Configurable RX polling timer with 2 % absolu
PAGE 3
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x CHANNEL FILTER AUTO CALIBRATION RECEIVE STATE MACINE RSSI LEVEL CLASSIFICATION TIMING CLASSIFICATION
PAGE 4
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 6. Pinning information 25 XTAL1 26 VCC_XO 27 RSTDIS 28 TEN 29 TEST3 30 VREG_PLL terminal 1 index area 31 VCC_REG 32 GND 6.
PAGE 5
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 2.
PAGE 6
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.1.1 Power management The device contains a configurable power-on reset block. The device control registers are reset as the external voltage rises to ensure that the device state is in Standby mode. This is implemented by ensuring that all blocks are off except the SPI and the digital regulator. Note that the digital regulator is operating in clamp mode at this time. 7.1.
PAGE 7
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver analog part VCO CALIBRATION reference oscillator to RX mixer charge pump PA PFD PA 1 diff to SE buffer 3rd-order loop filter UP 1 PA 2 TX/RX SWITCH ÷2 ÷2 0 VCO 1.20 GHz 1.856 GHz DOWN RF_LO_DIV POWER CONTROL main divider /N /N+1 N integer ∑∆ MODULATOR N Fract /R1 FSK FILTER K Fdev /R2 1 data in LATCH 0 FSK/ASK Fig 3. DIGITAL PART 001aan587 TX block diagram 7.1.
PAGE 8
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.1.7 RX block The OL2381’s RX path consists of a broadband resistive-feedback LNA, a mixer (mixing down the input signal to an IF of 300 kHz), a channel-filter, a limiter, an RSSI stage (AM demodulation) and a base-band signal processing block used for FM and AM data and clock recovery. The LNA, limiter and channel-filter gain settings can be configured via control bits. The channel filter bandwidth can also be adapted.
PAGE 9
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.1.10 Receive command The predefined set of RX parameters (center frequency, modulation, etc.) enables Receive mode (receiver and LO buffers switched on) to be entered quickly after receiving the RX command. Several methods of signal signature recognition are implemented. These modes of semi-automatic signal processing can be pre-selected by the RX command. 7.1.
PAGE 10
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver MOSI SDIO MISO P13/SDO SCLK SCLK HOST Port1 CONTROLLER Port2 P10/DATA Port3 P12/CLOCK Port4 P11/INT SEN OL2381 001aan589 Fig 5. Minimum port connections for TX and RX mode The device also supports full four-line SPI mode, the line SDIO serving as data input and P13/SDO as data output. Alternatively, the device can be configured for separate data inputs and outputs.
PAGE 11
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver All general purpose ports, except P11/INT and P12/CLOCK, are in 3-state after power-on reset. Port P11/INT is initialized as an output driving the active-LOW POR interrupt. Note that this interrupt is non-maskable. Port P12/CLOCK is initialized to provide a 1 MHz reference clock as the default output. 7.5.
PAGE 12
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Data can be exchanged with multiple 8-bit frames (auto-incrementing) or in portions of 8 bits (1 byte), which provides an advantage when using a hardware SPI-interface. Data in the shift register is loaded into the addressed register on the last edge of SCLK within the last bit of the transferred byte. 7.6.2 SEN A logic LOW applied to pin SEN disables the SPI interface.
PAGE 13
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.7 Write and read access to SFR 7.7.1 Write access to SFR SEN SCLK SDIO external driver 0 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDIO internal driver SDIO polarity of SCLK evaluated here command and address evaluated here data D7 to D0 moved to address A5 to A0 here 001aan591 Fig 7. Write serial interface timing diagram 7.7.
PAGE 14
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.7.4 Read access to SFR with separate SDO line SEN SCLK SDIO external driver 0 1 A5 A4 A3 A2 A1 A0 0 1 A5 A4 A3 A2 A1 A0 SDIO internal driver SDIO P13/ SDIO D7 D6 D5 D4 D3 data D7 to D0 at address A5 to A0 is read here Fig 9. D2 D1 D0 001aan593 Read serial interface timing diagram (SEP_SDO = 1) 7.7.
PAGE 15
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors OL2381 Product data sheet 7.7.
PAGE 16
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver SEN must be forced LOW after registers are read to indicate end of read. Figure 11 is an example showing 5 successive bytes read. 7.8 Device mode description 7.8.
PAGE 17
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver • PLLEN is set whenever the DEV_MODE is not logic 00 • RXEN is set only if DEV_MODE is logic 10 • TXEN is set only if DEV_MODE is logic 11 power-down conditions RECEIVE STATE RX command power-on reset polling timer event prepare receiver = 1 RX command SPI command prepare receiver = 0 SEN = 1 POWER-DOWN STATE IDLE STATE power-down conditions prepare transmitter = 1 SPI command prepare transmitter = 0 TX command po
PAGE 18
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.8.4.2 XTAL oscillator start-up The crystal oscillator or the buffer for the external clock is turned on depending on the states of CLOCKCON register bits XODIS and EXT_CLK_BUF_EN. Bit XO_RDY is logic 1 once the crystal oscillator has settled. The device waits for several clock periods until the clock output’s frequency and duty cycle have fully settled to within the required specification.
PAGE 19
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver commands may be more useful if the only operation required is the entering of TX or RX mode. The corresponding sequences start automatically and operation enabled after all internal settling times are met. 7.8.6 Interrupts TheOL2381 can generate various interrupts which can be enabled by the IEN register and read from the IFLAG register; see Section 8.2.1.11 “Interrupt enable register IEN” on page 101.
PAGE 20
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Remark: this bit only starts the PLL regulator, all PLL functional blocks are enabled individually by separate control-bits. 7.9.4 VCO regulator For stability and immunity reasons the VCO is supplied via an independent voltage regulator. This regulator can be manually controlled via bit REG_VCO_ON in the TEST2 register. Remark: this bit only starts the VCO regulator.
PAGE 21
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver xo_en ext_clk_buf_en signals to analog blocks OSCILLATOR CORE VCC_XO AMPLITUDE CONTROL Ibias XO_RDY xoready OSCILLATOR BUFFERING driver OSCILLATOR CONTROL LOGIC DC-coupled buffer KICK quartz Xtal1 Xtal2 Cx1 Xtal2 refclk rawrefclk valid clock signal Cx2 signals from digital control test signals power down XODIS EXT_CLK_BUF_EN FORCE_XO_RDY XOSTARTUPDELAY[1:0] EXT_CLK_BUF_EN XO_EN EXT_CLK_BUF_EN XO_
PAGE 22
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The oscillator buffer consists of two amplifiers connected in parallel: one low-noise AC-coupled amplifier for crystal operation and one high-input voltage DC-coupled amplifier for testing purposes only. The buffer plays the role of level-shifter for the signals in PLL and digital supply domains. The buffer circuitry is supplied by the PLL and digital regulators accordingly.
PAGE 23
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx raw xo_enable TRANSITION xo_enable CONTROL en OSCILLATOR CORE AND BUFFERING xtal1 rdy XO_RDY(1) osc ou
PAGE 24
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver If the crystal oscillator is turned on (XO_ENABLE becomes true) and a crystal is connected to the oscillator, the raw clock becomes available after the oscillation reaches a significant amplitude, which is then signaled with the internal XO_RDY status signal. This internal status signal can be routed to pin P12/CLOCK for observation.
PAGE 25
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver If the external clock buffer is used, it is assumed that the clock source, which is connected to pin XTAL2, provides a stable clock with a duty cycle close to 50 % at the time when bit EXT_CLK_BUF_EN is set. Therefore the delay counter is not needed in this case.
PAGE 26
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.12 Polling and wakeup timer The device features a low power oscillator, which can be used to generate wakeup events. A polling timer overflow always generates an interrupt request. Moreover, if selected, the device can be automatically released from the Power-down state and it can enter the RX state.
PAGE 27
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The polling timer wakeup time can be set with the 8-bit control register POLLWUPTIME. The wakeup time calculates to: T WUP =  POLLWUPTIME + 1   T WUPTICK (2) The achievable resolution and wakeup times can be selected in two different ranges, a normal and an extended polling timer range according to the setting of bit EXTPOLLTIMRNG in the CLOCKCON register.
PAGE 28
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The MAINSCH and the PRESC bits can be found in register TIMING1; see Section 8.2.1.5 “Timing register TIMING1” on page 95. The divide-by-128 divider is used as a ‘clock’ for several other blocks to measure the sub-timing within one chip interval. This baud-rate generator is used as the time reference for a synchronized TX operation and as a time reference for the clock-recovery in RX mode.
PAGE 29
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.13.1 Clock recovery for RX mode The clock-recovery for RX mode is dependent on the baud rate accuracy. If the absolute correct baud rate cannot be selected, choose the next available integer value. The clock recovery is able to cope with a 1 % tolerance to be able to operate correctly with standard XTAL cutting and temperature inaccuracies.
PAGE 30
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.14.3 General PLL operation The following blocks are enabled after switching on the regulators so that the entire PLL is operational: VCO (VCO_ON), phase-detector (PFD_ON), prescaler (PRESC_ON) and reference clock buffer (CLK_PLL_ON), depending on the selected mode of operation (RX or TX mode, selected via device mode or command); eventually RX_ON must be also set.
PAGE 31
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 15 16 last A, B flags K(t) MASH 1 to 1 ΣΔ MODULATOR S(t) 0 S2 -1 to 2 0 1 FC0 20 FC1 S1 LSBs 20
PAGE 32
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver When the fractional part approaches 0 or 1 the low frequency noise components in the pseudo-random sequence become more dominant and can no longer be sufficiently suppressed by the PLL’s transfer function. The visible effect is an increase of the phase noise in the RF output near the carrier. To counteract this effect, the OL2381 uses bit DOUBLE_SD_RESULT (Double Sigma Delta Result).
PAGE 33
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver If bit DOUBLE_SD_RESULT is set, the integer part and the fractional part of the center frequency setting must be considered separately. In this case the expression for the output frequency is shown in Equation 9.
PAGE 34
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The integer part which we have just found can be entered in Equation 10 and then we can solve for the fractional part. We get the result for the settings after rounding it to the nearest integer number shown in Equation 17.    f RF  FCx  14:0  = round   -------   1 + RF_LO_DIV  – 32 – FCx  19:15    16384 – 0.5     f ref  (17) When using the floor function this becomes as shown in Equation 18.
PAGE 35
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.14.9 PLL lock detection A lock detection circuit is implemented to support the shortest PLL power-on time. The lock-detection circuit monitors the phase and frequency differences of the PLL and the reference clock. If the phase-difference of the two clock signals is settled within a defined window, an internal LOCK_DETECT signal is triggered.
PAGE 36
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 5. TX command packet D0 D1 D2 D3 D4 D5 D6 D7 1 1 TA TB TC TD TE TF Table 6.
PAGE 37
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 10.
PAGE 38
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver SEN SCLK external driver reset baud-rate generator and turn on power amplifier SCLK internal driver SCLK SDIO external driver 1 1 TA TB TC TD TE TF 1 1 TA TB TC TD TE TF SDIO internal driver SDIO P10/DATA external driver TX DATA TX DATA P12/CLOCK internal driver TX DATA 001aan604 TA to TF contain configuration information for TX operation. Fig 20. TX data timing diagram (SEP_TX_LINES = 1) 7.16.
PAGE 39
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors OL2381 Product data sheet Manchester coded data TXDATA ''0'' ''1'' ''0'' ''1'' ''0''
PAGE 40
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver • SEP_TX_LINES = 1: the line P12/CLOCK drives a constant HIGH level; see Section 8.2.1.9 “Port control register PORTCON2” on page 99 7.17 Power amplifier The power amplifier is driven from the PLL synthesizer and operates in single-ended mode.
PAGE 41
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver amout acon AMH AML 001aan607 Fig 23. ASK modulation timing 7.18 Soft ASK, ramp control To achieve a more narrow spectral occupation of the ASK signal, Gaussian ASK-like modulation is implemented. The time-constant defined in the ARMP register defines the ASK signal’s up and down ramping time-constant; see Section 8.2.1.22 “Register ARMP” on page 106.
PAGE 42
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.20 PLL frequency deviation (FSK) 7.20.1 Frequency modulation FSK and GFSK-type modulation is accomplished by adding a time-varying sequence to the center frequency control value. This variation in the total frequency control value is slow enough to pass the PLL’s transfer function and the resulting RF is modulated in frequency; see Section 7.14.3 “General PLL operation” on page 30 for a detailed description of operation.
PAGE 43
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The modulation signal controls the RF output such that a logic 0 produces +D (the high frequency, fRF = fcenter + fdev) and logic 1 selects D (the low frequency, fRF = fcenter  fdev). If FRMP_MANT is logic 0, the resulting squarewave shaped sequence is the modulating sequence M(t). 7.20.2 Soft FSK A GFSK-type modulation scheme is implemented to achieve a narrower signal bandwidth of the FSK spectrum.
PAGE 44
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Ramp Time +fdev Steps fdev 001aao143 Fig 24. Soft FSK parameters Given: fref = reference frequency (crystal frequency: 16 MHz). fdev = frequency deviation. RampTime = wanted time for ramping, to reduce occupied bandwidth. Search: FRMP_EXP and FRMP_MANT, in order to program register FRMP. Calculation: f ref 1 + DOUBLE_SD_RESULT 1.
PAGE 45
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.22 Modulation data generation Depending on the setting of bit SEP_TX_LINES in register PORTCON2, either pin SDIO or pin P10/DATA act as the data input; see Section 8.2.1.9 “Port control register PORTCON2” on page 99. Input data is synchronized to the reference clock CLKREF. This flip-flop serves also as storage for the input data. Input data is sampled under the following conditions.
PAGE 46
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.23.3.1 PLL active TX mode The TX mode is entered on reception of a valid TX command, providing the PLL is settled. Depending on the TX command’s content, TX mode exits either directly when SEN is set LOW, or when synchronized with the last data bit’s edge when SEN is set LOW or directly on the SPI register setting. The power amplifier is turned on at the ninth bit’s first active edge of the TX command.
PAGE 47
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver TEST1, TEST2 via bits ANA_TEST_SEL[2:0] in register TEST1. The digital IQ signals of the limiter output, and other digital baseband signals can be accessed via the alternative port functions of P11C and P12C with the appropriate setting of bits DIG_TEST_SEL[2:0] in register TEST0; see Table 121 “Register TEST0 - (address 35h) bit description” on page 126 for more details. 7.24.
PAGE 48
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.27.1 Channel filter auto-calibration The channel filter auto-calibration is implemented to achieve a well-centered filter roll-off characteristic in the filter pass-band. This feature can compensate for process and temperature dependent parameter mismatches. Filter auto-calibration is performed automatically before every RX operation.
PAGE 49
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver CF_IQ_CALVAL[6:0]. This information must be stored by the external microcontroller. Initialize this register with the stored values each time. Set CF_IQ_CALVAL[6:0] to logic 0 if no IQ calibration is required. Figure 26 shows the effect of a simulated I/Q calibration. With this calibration an image rejection of 50 dB is achievable. IMAGE CHANNEL IMAGE 21.
PAGE 50
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 14. RX gain control …continued LNA gain 1 LNA gain 0 Gain (dB) LNA input stage typical current (mA) 0 1 17 0.55 1 0 23 1.1 1 1 25.5 1.65 [1] LNA low gain stage.
PAGE 51
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver RSSI 1.65 +65 % switch 1 −120 −100 −70 −40 −20 Pin (dBm) 001aan611 Fig 28. 40 dB difference between Hi-gain and Lo-gain setting 7.29 Limiter The function of the limiter is to amplify or limit the input signal so that the output voltage of the last stage of the limiter is always constant. This applies to both very small signals at the sensitivity limit and very large input signals.
PAGE 52
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver gain control RSSI reference -60 dBm LNA channel filter mixer buffer I Q DIGITAL FM DEMODULATOR limiter conversion gain = 30 dB, 35 dB, 25 dB or 5 dB sensitivity = -116 dBm gain = 25 dB, 0 dB, 10dB or 35 dB IF = 300 kHz gain = -12 + 81 = 69 dBmin 14 dB per stage (nominal) IF = 300 kHz pin = -71 dBm to 5 dBm IF = 300 kHz signal level = -12 dBVp(diff) (= 250 mVpdiff, 10 Vt) 001aan612 Fig 29.
PAGE 53
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver start clk limiter IRSSI STATE MACHINE lo 2lo 4lo 8lo 16lo 32lo 001aan613 Fig 30. Block diagram of RSSI 7.31.2.1 RSSI low-pass filtering The filter integration time-constant of the analog RSSI signal can be adapted to achieve a more stable digital RSSI reading (RSSI raw value) as an input to the digital filtering and interpolation.
PAGE 54
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 108. If the gain switching is enabled during wakeup-search, the gain is reduced to the RX_LO_GAIN[3:0] setting provided the RSSI threshold set by HI_GAIN_LIMIT[7:0] is exceeded. The RSSI reading is performed automatically during the wakeup-search detection. Remark: If the input signal level is above the switching threshold and the gain-switching is initiated, two bits are lost due to the switching event.
PAGE 55
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver ENTER RECEIVE MODE RX_GAP_ON = 1 CLK_RXA_ON = 1 SKIP_CF_RC_CAL 1 WAIT 1 μs CF_RC_CAL_OK 0 1 0 PLL_LOCKED FALLING EDGE OF REF CLK TURNS CALIBRATION CLK OFF 1 RX_ON = 1 VCO CLOCK DIVIDER FOR RECEIVER PART ON 001aan614 Fig 31. Preparation for RX mode 1.
PAGE 56
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 16. Frequency selection (bits RA, RB) Bit RA Bit RB Selected frequency band 0 0 FC0L, FC0M, FC0H 0 1 FC1L, FC1M, FC1H 1 0 FC2L, FC2M, FC2H 1 1 FC3L, FC3M, FC3H Remark: In RX mode a frequency offset of +300 kHz is automatically added to the resulting center frequency to account for the necessary LO frequency offset.
PAGE 57
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver detection operation itself) can be interrupted with Read and Write commands and can be continued with a CONT RX command. When the correct preamble is detected, the receiver switches automatically into data reception mode. This switch does not influence the signal processing section of the receiver, which means that there is a seamless transition from the preamble detection mode to the data reception mode.
PAGE 58
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver SEN SCLK external driver SCLK internal driver SCLK SDIO external driver 1 0 RA RB RC RD RE RF SDIO internal driver SDIO 1 0 RA RB RC command and flags TA and TB evaluated here RD RE RF flags TC to TF evaluated here RX DATA RX DATA RX DATA RX DATA RX DATA RX DATA 1st bit to be fetched by host controller 2nd bit to be 3rd bit to be fetched by fetched by host controller host controller 001aan615 Fi
PAGE 59
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver SEN SCLK external driver SCLK internal driver SCLK SDIO external driver 1 0 RA RB RC RD RE RF 1 0 RA RB RC RD RE RF SDIO internal driver SDIO P12/CLOCK internal driver P10/DATA internal driver RX DATA 1st bit to be fetched by host controller RX DATA RX DATA 2nd bit to be 3rd bit to be fetched by fetched by host controller host controller 001aan616 Fig 33.
PAGE 60
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The command is initiated on the next rising edge of the SPI clock. In the case of a WUPS, a PRDA or a DATA RX command, this brings the receiver state machine to the respective starting point of the sub-command. If a CONT RX command is issued, the receiver state machine is not influenced.
PAGE 61
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The relevant register is automatically selected depending on whether the receiver is in wakeup search mode, preamble detection mode or in data reception mode. The settings of SLICERINITSEL[1:0] and INIT_ACQ_BITS[1:0] make two individual alternative configuration sets available because only one slicer initialization is necessary for the combined preamble detection and data reception operation.
PAGE 62
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 21.
PAGE 63
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.33.1.1 Functional block diagram UPPERRSSITH r 8 x below or equal upper threshol xr 001aan617 Fig 34.
PAGE 64
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.33.2.1 Method to determine the modulation amplitude The modulation amplitude classification block measures the magnitude of the signal transitions within one chip interval. The baseband signal is delayed by one chip interval using an oversampling ratio of 4 samples per chip interval. A raw amplitude measurement is computed for each sample by subtracting the delayed sample and taking the absolute value of the difference.
PAGE 65
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Due to the ripple in the output signal (lower trace) and the discrete sampling time, the sampled signal can be lower than the theoretical maximum value. Worst case input signals for this algorithm produce a maximum amplitude error of 8 % of the maximum theoretical value. 001aan621 2500 modulation (Hz) 2400 2300 2200 2100 2000 0.0343 0.0347 0.0351 0.0355 t (s) 4  oversampling. Fig 38.
PAGE 66
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver UPPER_MODAMP_TH_MANT[3:0] = 15d = 1111b UPPER_MODAMP_TH_EXP[7:4] = 4d = 0100b. The LOWER_MODAMP_TH should be set to 92 % of the maximum expected value: 242  0.92 = 222. The closest programmable value not exceeding this is 13  24 = 208.
PAGE 67
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver LEVEL SLICER READ/WRITE ACCESS FROM SPI SLICERINITTHR SLICERTHR INITIAL ACQUISITION LOW-PASS FILTER r x x³r baseband signal slicer output EDGE SENSITIVE SLICER 001aan622 Fig 39. Slicer block diagram The edge-sensitive slicer will not make use of these two registers. The EDGE_MODAMP_TH contains the expected peak modulation amplitude with which the edge slicer is initialized.
PAGE 68
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The slicer operating mode slicer is selected by the slicer selection bits SLICERSEL_W[1:0]; see Table 84 “SLICERSEL_W bit functions” on page 112. The edge slicer takes five adjacent samples at intervals equivalent to ¼ of the chip width. The four outermost samples (red and blue dots in Figure 40) are used to make up a dynamic threshold and the middle sample (green dot) is compared against this.
PAGE 69
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The FSK signal must be mapped to the output range of the FSK demodulator. The output signal range is from 0 to 32256. This range equates to a frequency deviation of 200 kHz to 600 kHz depending on bit LARGE_FM_DEM_RANGE in register EXPERT2. The expected peak modulation amplitude is 1.5 / 200  32256 = 242. The EDGE_MODAMP_TH is set as close as possible to the expected value: 15  24 = 240.
PAGE 70
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The various level slicer initialization mechanisms are controlled by bits SLICERINITSEL_x[1:0]. If the slicer is initialized, its output becomes invalid for at least one cycle, which restarts the deglitcher and the edge detector. The output remains valid even when the slicer threshold is updated after the initial acquisition refines its threshold value (after 4 and 8 bits). 7.34.3.
PAGE 71
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.34.4 Deglitcher and edge detector The purpose of the deglitcher is to suppress multiple signal transitions when a noisy baseband signal crosses the slicer threshold.
PAGE 72
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver edge detect TIME OF PREVIOUS EDGE chip rate counter chip width = 128 counts REDUCED_ CHIP_TIMEOUT − ≥ = 320 1 ≥ = 448 0 interval too large, chip timeout LATCH ≥ = 192 − long interval 0 128 1 256 single interval timing error value (will be averaged in the baud-rate checker) ABS() 0 1 ≥= 2 3 single chip timing error detected 8 16 24 32 SGLBITTMGERRTH 001aan624 Fig 41.
PAGE 73
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver reset IDLE off edge FIRST_SYNC off not valid unknown off timeout timeout timeout timeout TIMEOUT edge off timeout edge timeout valid error RESYNC off off edge edge CHECK valid ok/error 001aan625 Fig 42. State diagram of chip timing verification block After the first synchronization (reception of two edges) the chip timing verification block becomes VALID and the chip timing CHECK begins.
PAGE 74
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver reset IDLE off off off on egde START FIRST_SYNC timeout not valid unknown off off timeout timeout off CodeOK or ManchesterLong CodeViolation TIMEOUT ManchesterShort edge timeout timeout CodeOK or ManchesterLong off ManchesterShort CodeViolation ManchesterShort MANCHESTER START CodeOK or ManchesterLong off CodeViolation RESYNC off off valid error CodeViolation or ManchesterLong timeout ManchesterLo
PAGE 75
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The OK/ERROR information is directly derived from the state machine. The RESYNC state is initiated after a code violation is recognized by any of the other states, unlike the chip timing verification block which only enters the RESYNC state after the occurrence of a timeout.
PAGE 76
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver On the occurrence of a timeout or a single bit timing error, the baud-rate checker resets immediately, NOT VALID is signaled instantaneously and the baud-rate checker restarts. 7.35.4 Timeout timer for the wakeup search The control logic includes a timeout timer for the wakeup search operation.
PAGE 77
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 22.
PAGE 78
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver valid fail error pass WUPS_EN[i] 001aan628 Fig 45. Creation of PASS/FAIL information from one signal monitor Two different mechanisms are provided for the wakeup search: • ‘pessimistic wakeup search’ or mode 1 • ‘optimistic wakeup search’ or mode 2 In the pessimistic wakeup search (mode 1) the wakeup search timer has no meaning and therefore will not influence the result.
PAGE 79
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver SIGMON STATUS SIGMONERROR WUPS_EN WUPSFAIL WUP TIMEOUT WUPSMODE CHIP TIMEOUT CHIP TIMING CODING valid indicators BAUD RATE RSSI LEVEL MODULATION AMPLITUDE TOO HIGH MODULATION AMPLITUDE TOO LOW RFU status register address k + 1 control register status register at address k 001aan630 Fig 47. Wakeup search registers 7.36.
PAGE 80
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver The status of SIGMONSTATUS, SIGMONERROR and RSSILEVEL is only sampled in line 2. Single byte read commands (lines 4 and 5) only transfer the previously sampled status once bit STATAUTOSAMPLE is set back to logic 0. Lines 4 to 8 do not change the contents of the registers because status sampling is already disabled. Table 24.
PAGE 81
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.38 RX data decoding After a wakeup search, if configured, a preamble detection and data reception follows seamlessly. After successful completion of the wakeup search and the preamble detection, the RX data is switched to the corresponding port pins, dependent on the device configuration. The data pin is kept LOW during wakeup search and HIGH during preamble detection. Data reception can be interleaved with SPI commands.
PAGE 82
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.40 RX digital signal processing 7.40.1 AM demodulator AM demodulation requires bit DEMOD_ASK in register RXBW to be set; see Section 8.2.1.25 “Channel filter bandwidth and RSSI filter settings register RXBW” on page 108. In this case, the data from ASK demodulator output will be connected to the digital baseband filter input. 7.40.2 FM demodulator The FM demodulator consists of a discrete delay line and an XOR gate.
PAGE 83
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 25. FM demodulator configurations See register EXPERT2 bit descriptions in Table 117 on page 125. D7 D6 Center frequency (kHz) Input frequency range Maximum frequency (kHz) deviation (kHz) Number of delay elements 0 0 300 200 to 400 100 40 0 1 300 0 to 600 300 13 1 0 600 200 to 400 100 20 1 1 600 0 to 600 300 7 7.40.
PAGE 84
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Figure 50 and Figure 51 show the step response and the frequency response of the baseband filter, respectively. Figure 50 shows that the step response has an undershoot (negative overshoot) of approximately 3 % and an almost unnoticeable overshoot. This demonstrates a characteristic close to that of an analog Bessel filter.
PAGE 85
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 26. BASEBAND_FILTER_FC definition D3 D2 D1 D0 Cut-off frequency (fc) Down-sampling factor Output sampling rate 0 0 0 0 115.45 kHz 2 8 MHz 0 0 0 1 57.174 kHz 4 4 MHz 0 0 1 0 28.405 kHz 8 2 MHz 0 0 1 1 14.204 kHz 16 1 MHz 0 1 0 0 7.0795 kHz 32 500 kHz 0 1 0 1 3.5400 kHz 64 250 kHz 0 1 1 0 1.7701 kHz 128 125 kHz 0 1 1 1 885.12 Hz 256 62.
PAGE 86
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 27.
PAGE 87
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 27.
PAGE 88
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8. Special function registers 8.1 Overview A map of the Special Function Registers (SFR) is shown in Table 28. The SFRs are arranged into two banks: bank 0 and bank 1. Bank 0 or bank 1 can be selected by setting bit BANK_SEL in register BANKSEL, visible in both banks, accordingly. Bytes 0 to 2Dh and 3Fh can always be accessed, independent of the setting of bit BANK_SEL in register BANKSEL (3Fh).
PAGE 89
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Register map table Register Addr Bank Bit 7 (MSB) 6 5 4 FC0L[1] 3 2 1 0 (LSB) 0 0 0 0 Defaul
PAGE 90
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Register map table …continued Register Addr Bank DEVSTATUS 19h 01 FDEV 1Ah 01 Bit 7 (MSB) 6 5 4
PAGE 91
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Register map table …continued Register Addr Bank SIGMON2 30h 0 WUPSTO 31h 0 Bit 7 (MSB) 6 5 4 3
PAGE 92
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Register map table …continued Register Addr Bank EXPERT3 34h Bit 7 (MSB) 6 5 4 3 0 0 0 0 RFU[1
PAGE 93
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2 Register descriptions The SFRs are arranged into two banks: bank 0 and bank 1. Bank 0 or bank 1 can be selected by setting bit BANK_SEL in register BANKSEL, visible in both banks, accordingly. 8.2.1 Registers visible in both bank 0 and bank 1 8.2.1.1 Frequency control registers The frequency control registers contain the PLL frequency control information.
PAGE 94
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 31. Frequency control register FC0H - (address 02h) bit description …continued Reset value = B1h. Bit Symbol Value Description 2 FCxH 1 high 3 bits of 15-bit fractional part of operating frequency value FCx 1 1 0 0 Frequency control register FC1L (address 03h); same bit description as FC0L, but reset value = XXh.
PAGE 95
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.1.3 Local oscillator control register LOCON Table 33. Local oscillator control register LOCON - (address ODh) bit description Bit Symbol Value Description 7 CLK2SCLK_DELAY 0 delay from the 9th SCLK edge in a TX/RX command until the device starts driving the SCLK line. Only applicable if bit SEP_TX_LINES is logic 0 when sending a TX command, or bit SEP_RX_OUT is logic 0 when sending an RX command.
PAGE 96
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 34. 8.2.1.6 Timing register TIMING1 - (address 0Fh) bit description …continued Bit Symbol Value Description 2 MAINSCH 0 3 highest bits of baud-rate generator’s main scaler 1 0 0 0 Port control registers PORTCON0 to PORTCON2 Registers PORTCON0 to PORTCON2 define the function of Port pins P10, P11, P12, P13 and P14. Test functions can be enabled in combination with register TEST0.
PAGE 97
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 37.
PAGE 98
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 40. Port control register PORTCON1 - (address 11h) bit description …continued Bit Symbol Value Description 3 P12C 0 configures P12/CLOCK; see Table 41 2 1 1 1 0 P12INV Table 41.
PAGE 99
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 43. D6 D5 D4 Function 1 0 1 PLL lock detector signal (digitally filtered) 1 1 0 continuous 1 MHz clock 1 1 1 constant LOW (reserved) Table 44. 8.2.1.9 Test signal IIII …continued P13C port control data functions D3 D2 D1 Function 0 0 0 3-state 0 0 1 always zero 0 1 0 TX modulation signal, including Manchester encoding if applicable; bistable signal.
PAGE 100
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 47. SEP_TX_LINES TX data input TX clock output 0 SDIO SCLK 1 P10/DATA P12/CLOCK (optional, only if P12C = 010b) Table 48. 8.2.1.10 SEP_TX_LINES data functions P14C port control data functions D2 D1 Function 0 0 3-state 0 1 constant LOW 1 0 0 = RX_MODE, 1 = TX_MODE, or 3-state 1 1 0 = RX_MODE, 1 = TX_MODE, or 3-state General power mode register PWRMODE Table 49.
PAGE 101
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 51. Polling timer status after master reset Pin RSTDIS Status after master reset LOW POLLTIM_EN = 1: polling timer is activated with the settings of register POLLWUPTIME = 255 and EXTPOLLTIMRNG = 0. HIGH POLLTIM_EN = 0: polling timer off Table 52.
PAGE 102
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 54. 8.2.1.
PAGE 103
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 57. 8.2.1.15 POLL_MODE[1:0] device mode control functions D7 D6 Function 0 0 after signaling the polling timer interrupt, which is unmaskable, the device remains in Power-down mode 0 1 after signaling the polling timer interrupt, which is unmaskable, the device leaves Power-down mode, which turns the crystal oscillator or the external clock buffer on 1 0 device is fully powered up to RX mode.
PAGE 104
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 60. CLKSOURCESEL bit functions …continued D4 D3 D2 Port pin 1 0 1 2  chip clock 1 1 0 chip clock 1 1 1 bit clock Table 61. 8.2.1.16 EXT_CLK_BUF_EN / XODIS bit functions D1 D0 Function 0 0 crystal oscillator enabled. Digital reference clock disabled during oscillator start-up. 0 1 crystal oscillator and external clock buffer disabled 1 0 crystal oscillator enabled.
PAGE 105
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 63. 8.2.1.18 FSK frequency deviation register FDEV - (address 1Ah) bit description …continued Bit Symbol Value Description 4 FDEV_MANT X FSK frequency deviation 5-bit mantissa. 0 = no modulation. 3 X 2 X 1 X 0 X FSK ramp adjustment register FRMP Register FRMP bits adjust the FSK ramp (GFSK-type modulation); see Section 7.20.2 “Soft FSK” on page 43. Table 64.
PAGE 106
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.1.21 8.2.1.22 Table 66. Register ACON1 - (address 1Dh) bit description …continued Bit Symbol Value Description 4 AMH1 X if this power control set is selected for transmission (TX command flag F = 1), this becomes the output power control in FSK mode or the power setting when the modulation signal is 0 in ASK mode 3 X 2 X 1 X 0 X Register ACON2 Table 67.
PAGE 107
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.1.23 Transmitter control register TXCON Table 69. Transmitter control register TXCON - (address 20h) bit description Bit Symbol Value Description 7 DOUBLE_SD_ RESULT 0 configures the Sigma delta fractional-N modulation; see Section 7.14.
PAGE 108
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver [1] 8.2.1.24 The values were obtained using a fixed matching network, with an output load of 150  at 900 MHz. In specific cases where power values below 10 dBm are required, adapt the optimum matching network. Power steps of 1 dB (maximum) are valid only when the output power is above 0 dBm. Receiver gain control register RXGAIN Table 73.
PAGE 109
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.1.26 Register GAINSTEP Table 76. Register GAINSTEP - (address 23h) bit description Bit Symbol Value Description 7 0 0 - 6 RSSI_GAIN_ STEP_ADJ X the receiver automatically adds this value to the filtered and properly scaled RSSI reading whenever it is in low gain mode to compensate for the difference (high gain minus low gain). This seamlessly extends the RSSI’s dynamic range by switching the RX chain gain.
PAGE 110
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 78. Bit Symbol Value Description 5 BASEBAND_ SETTL_TIME X adjusts the baseband settling delay. Delay is the time between the declared valid IF signal and the declared valid baseband signal. The delay is 2  (1 + BASEBAND_SETTL_TIME)  chip duration.
PAGE 111
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver T 1 + --------100 In ASK mode: UMODAMPTH = ASK MOD  ------------------  512 where ASKMOD = ASK 1.5 modulation amplitude ratio (dB), T = tolerance (%). Remark: The specified amplitude is peak-to-peak. 8.2.1.31 Register LMODAMPTH Register LMODAMPTH (address 29h) contains the lower modulation amplitude measurement threshold level (modulation amplitude classification unit).
PAGE 112
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.1.33 Register RXDCON0 Table 82. Register RXDCON0- (address 2Bh) Register Table 83.
PAGE 113
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 85. D3 D2 Function 0 1 slicer threshold is initialized with the content of register SLICERINITH at the start of a RX event. 1 0 initial acquisition is achieved at the start of a RX event. Slicer threshold is updated each time a new result is available from the initial acquisition. 1 1 same as setting 10 but the initial acquisition is automatically restarted when a chip duration timeout occurs Table 86. 8.
PAGE 114
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 88. Dynamic RX mode control register RXDCON2 - (address 2Dh) bit description Bit Symbol Value Description 3 CODINGRESTR_W X wakeup search, coding verification unit. Selection of the permitted signal encoding, see Table 89 2 X 1 CODINGRESTR_P X coding restriction for preamble detection. If logic 0, no restriction, both time intervals (1  chip and 2  chip width) are accepted in an arbitrary order.
PAGE 115
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 92. D7 Function 0 ‘pessimistic’ wakeup search (also called mode 1): wakeup search ends when either one of the enabled signal monitors signals a FAIL or all enabled signal monitors signal PASS.
PAGE 116
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.2.3 Signal monitoring control register SIGMON2 Table 95. Bit Symbol 7 0 0 - 6 SIGMON_EN_D X selection of signal monitor (signal signature recognition unit) to be active during data reception, see Table 93. If an enabled signal monitor detects an abnormal condition, it is indicated by the IF_EOF (End-of-Frame flag). Value 5 X 4 X 3 X 2 X 1 X 0 8.2.2.
PAGE 117
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.2.7 Register TIMINGCHK Register TIMINGCHK (address 34h) configures the timing-check units. Table 98.
PAGE 118
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.2.8 Register RXCON Table 102. Receive mode control register RXCON - (address 35h) bit description Bit Symbol Value Description 7 STATAUTOSAMPLE X allows the software to control whether the status is sampled when certain Read commands are issued.
PAGE 119
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 103. CLOCK_RECOV_TC bit functions …continued 8.2.2.9 D4 D3 Maximum settling time (chips) Maximum bit edge phase error (deg) Tolerance (%) 0 1 7 15 4 1 0 15 30 2 1 1 31 60 1 Register RXFOLLOWUP Table 104.
PAGE 120
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 104. Receive mode follow-up control register RXFOLLOWUP - (address 36h) bit description …continued Bit Symbol Value Description 3 WUPS_FU_TF 1 this bit is only effective: when wakeup search (WUPS), was initiated by the polling timer event, and WUPS detection failed. if this bit is logic 1: device enters power-down. if this bit is logic 0: device stops, but stays on, a non-maskable interrupt occurs.
PAGE 121
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.2.10 Register SIGMONSTATUS Table 105. Status register SIGMONSTATUS - (address 37h) bit description See Section 7.36 “Wakeup search logic” on page 76 for further details. Bit Symbol Value Description 7 SIGMONSTATUS S if logic 1, the previous wakeup search or preamble detection has failed. If logic 0, the command completed successfully. Other status registers can be read to ascertain more information if required.
PAGE 122
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.2.12 Register RSSILEVEL Table 108. Register RSSI - (address 39h) bit description Bit Symbol 7 RSSI_LEVEL Value Description 0 result of RSSI conversion 6 0 5 0 4 0 3 X 2 X 1 X 0 X Register RSSI contains the measured RSSI level at the completion of a wakeup search or preamble detection, or at the moment the microcontroller recently triggered sampling the RX signal status. 8.2.2.
PAGE 123
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.2.17 Register PREA3 Register PREA3 (address 3Eh) contains bits [31:24] of the preamble pattern. 8.2.3 Registers only visible in bank 1 8.2.3.1 Register EXTRXSTATUS Table 111.
PAGE 124
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.4 Expert registers The expert registers enable the use of built-in functions for special application cases. It is recommended that these settings are not changed. 8.2.4.1 Register EXPERT0 Table 114. Register EXPERT0 - (address 31h) bit description 8.2.4.2 Bit Symbol Value Description 7 RED_VCO_SWING 0 automatically set at lower band, if logic 1, VCO output swing and LO power consumption are reduced.
PAGE 125
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 116. XOSTARTUPDELAY bit functions …continued 8.2.4.3 D7 D6 Delay time 0 1 512 s (default Power-on reset value) 1 0 768 s 1 1 1024 s Register EXPERT2 Table 117.
PAGE 126
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 119. CAPRSSI bit functions …continued 8.2.4.4 D1 D0 Typical capacitor value (pF) Time-constant (R = 300 k typical) 0 1 2 0.6 s 1 0 5 1.5 s 1 1 12 4.8 s Register EXPERT3 Table 120. Register EXPERT3 - (address 34h) bit description Bit Symbol Value Description 7 0 0 - 6 0 0 - 5 0 0 - 4 0 0 - 3 TESTBUFFERCAL 0 logic 1 turns the calibration path on.
PAGE 127
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.5.2 Register TEST1 Table 122. Register TEST1 - (address 36h) bit description Bit Symbol Value Description 7 IQ_TEST_LV 0 must be set if IF output signals test buffer is used at supply voltages below 2.0 V 6 ANA_TEST_SEL 0 selects analog test signal 5 0 4 0 3 REG_DIG_DIS 0 disables voltage regulator digital section 2 PLL_CTRL 0 test and configures PLL 1 0 8.2.5.
PAGE 128
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.5.5 Register TEST4 Table 125.
PAGE 129
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 9. Limiting values Table 128. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Tstg storage temperature Tj junction temperature VIO input/output voltage C C +3.6 V all other pins to GND 0.3 +2.8 V RF_OUT pin to GND; RF peak voltage 0.3 +4.2 V - 4 mA - 12.9 dBm 100 - mA 1.
PAGE 130
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 129. Static characteristics …continued Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and GND_PLL, VREG_VCO and GND_VCO . Capacitor of 47 nF // 270 pF connected between VREG_PA and GND_PA and VREG_DIG and GND_DIG quartz crystal NDK NX5032SA with CL = 12 pF, unless otherwise specified. The Edge Slicer was used for all relevant measurements.
PAGE 131
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 11. Dynamic characteristics Table 130. Dynamic characteristics Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_PA and GND_PA and VREG_DIG and GND_DIG; quartz crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified.
PAGE 132
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 130. Dynamic characteristics …continued Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_PA and GND_PA and VREG_DIG and GND_DIG; quartz crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevant measurements.
PAGE 133
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 130. Dynamic characteristics …continued Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_PA and GND_PA and VREG_DIG and GND_DIG; quartz crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevant measurements.
PAGE 134
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 130. Dynamic characteristics …continued Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_PA and GND_PA and VREG_DIG and GND_DIG; quartz crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevant measurements.
PAGE 135
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 130. Dynamic characteristics …continued Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_PA and GND_PA and VREG_DIG and GND_DIG; quartz crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevant measurements.
PAGE 136
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 130. Dynamic characteristics …continued Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_PA and GND_PA and VREG_DIG and GND_DIG; quartz crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevant measurements.
PAGE 137
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 130. Dynamic characteristics …continued Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_PA and GND_PA and VREG_DIG and GND_DIG; quartz crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevant measurements.
PAGE 138
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 130. Dynamic characteristics …continued Tamb = 25 C to +85 C, VCC_xxx = 2.7 V, GND_xxx = 0 V; capacitors of 22 nF // 270 pF connected between VREG_PLL and GND_PLL, VREG_VCO and GND_VCO; capacitor of 47 nF // 270 pF connected between VREG_PA and GND_PA and VREG_DIG and GND_DIG; quartz crystal NDK NX5032SA with CL = 12 pF; unless otherwise specified. The Edge Slicer was used for all relevant measurements.
PAGE 139
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x 100 nF 100 nF 100 nF 100 nF 1 μF VCC_PA P14/PIND XTAL2 TEN TEST1 RSTDIS TEST2 RF SWITCH 47 nF
PAGE 140
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 13. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm D B SOT617-3 A terminal 1 index area A A1 E detail X C e1 e 9 y1 C C A B C v w 1/2 e b y 16 L 17 8 e e2 Eh 1/2 e 24 1 terminal 1 index area 32 25 X Dh 0 2.5 scale Dimensions Unit(1) mm 5 mm A(1) A1 b max 0.05 0.30 nom 0.85 min 0.00 0.18 c D(1) Dh E(1) Eh 5.1 3.
PAGE 141
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 14. Abbreviations Table 131.
PAGE 142
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Table 131. Abbreviations …continued OL2381 Product data sheet Acronym Description SPI Serial Peripheral Interface SRD Short-Range Device TX Transmitter VCO Voltage-Controlled Oscillator WUP Wake UP WUPS Wake UP Search XO Crystal Oscillator All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 November 2011 © NXP B.V. 2011. All rights reserved.
PAGE 143
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 15. Revision history Table 132. Revision history Document ID Release date Data sheet status Change notice Supersedes OL2381 v.1 20111130 Product data sheet - - OL2381 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 November 2011 © NXP B.V. 2011. All rights reserved.
PAGE 144
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
PAGE 145
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 146
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 18. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Ordering information . . . . . . . . . . . . . . . . . . . . .
PAGE 147
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver bit description . . . . . . . . . . . . . . . . . . . . . . . .105 Table 67. Register ACON2 - (address 1Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Table 68. Register ARMP - (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Table 69. Transmitter control register TXCON (address 20h) bit description . . . . . . . . . . . . .107 Table 70.
PAGE 148
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver auto-calibration . . . . . . . . . . . . . . . . . . . . . . .128 Table 127. Register TEST5 - (address 3Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . .128 Table 128. Limiting values . . . . . . . . . . . . . . . . . . . . . . .129 Table 129. Static characteristics . . . . . . . . . . . . . . . . . . .129 Table 130. Dynamic characteristics . . . . . . . . . . . . . . . .131 Table 131. Abbreviations . . . .
PAGE 149
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 19. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Fig 42. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 150
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.
PAGE 151
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 7.14.8 7.14.9 7.15 7.16 7.16.1 7.16.1.1 7.16.2 7.16.3 7.16.4 7.17 7.18 7.19 7.20 7.20.1 7.20.2 7.21 7.22 7.23 7.23.1 7.23.2 7.23.3 7.23.3.1 7.23.4 7.23.5 7.24 7.24.1 7.25 7.26 7.27 7.27.1 7.27.2 7.28 7.29 7.30 7.31 7.31.1 7.31.2 7.31.2.1 7.31.2.2 7.31.2.3 7.31.3 7.32 7.32.1 7.32.2 7.32.2.1 7.33 7.33.1 7.33.1.1 7.33.2 7.33.2.1 RX frequency offset . . . . . . . . . . . . . . . . . . . . PLL lock detection . . . . . . . . . .
PAGE 152
OL2381 NXP Semiconductors Highly integrated single-chip sub 1 GHz RF transceiver 8.2.1.18 8.2.1.19 8.2.1.20 8.2.1.21 8.2.1.22 8.2.1.23 8.2.1.24 8.2.1.25 8.2.1.26 8.2.1.27 8.2.1.28 8.2.1.29 8.2.1.30 8.2.1.31 8.2.1.32 8.2.1.33 8.2.1.34 8.2.1.35 8.2.2 8.2.2.1 8.2.2.2 8.2.2.3 8.2.2.4 8.2.2.5 8.2.2.6 8.2.2.7 8.2.2.8 8.2.2.9 8.2.2.10 8.2.2.11 8.2.2.12 8.2.2.13 8.2.2.14 8.2.2.15 8.2.2.16 8.2.2.17 8.2.3 8.2.3.1 8.2.3.2 8.2.3.3 8.2.4 8.2.4.1 8.2.4.2 8.2.4.3 8.2.4.4 8.2.5 8.2.5.1 8.2.5.2 8.2.5.