PCA9575 16-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt Rev. 4 — 20 May 2014 Product data sheet 1. General description The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery powered mobile applications and was developed to enhance the NXP family of I2C-bus I/O expanders. The improvements include lower supply current, lower operating voltage of 1.1 V to 3.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the two banks of 8 I/Os as inputs, sets the registers to their default values and initializes the device state machine. The I/O banks are held in its default state when the logic supply (VDD) is off.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 3. Applications Cell phones Media players Multi-voltage environments Battery operated mobile gadgets Motherboards Servers RAID systems Industrial control Medical equipment PLCs Gaming machines Instrumentation and test measurement 4. Ordering information Table 1.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 5.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO data from shift register data from shift register output port register data configuration register D VDD(IO) Q1 Q FF write configuration pulse write pulse CK Q D Q FF Q2 CK output port register input port register D ESD protection diode VSS Q input port register data FF read pulse CK INTERRUPT MASK VDD(IO) BUS-HOLD AND PULL-UP/PULL-DOWN CONTROL P0_0 to P0_7 P1_0 to P1_7 to INT 100 kΩ polarity
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 6. Pinning information 6.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 6.2 Pin description Table 3.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7. Functional description 7.1 I/O ports The 16 I/O ports are organized as two banks of 8 ports each. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.3 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master sends a byte to the PCA9575, which is stored in the Command register. AI 0 0 Auto-Increment flag 0 D3 D2 D1 D0 register address 002aad568 Reset state = 00h Remark: The Command register does not apply to Software Reset I2C-bus address. Fig 8.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO Table 4. Register summary …continued Register number D3 D2 D1 D0 Name Type Function 0Dh 1 1 0 1 MSK1 read/write Interrupt mask port 1 register 0Eh 1 1 1 0 INTS0 read only Interrupt status port 0 register 0Fh 1 1 1 1 INTS1 read only Interrupt status port 1 register 7.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.6.2 Register 1 - Input port 1 register This register is read-only. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register are acknowledged but have no effect. The default ‘X’ is determined by the externally applied logic level. Table 6.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.6.4 Register 3 - Polarity inversion port 1 register This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained. Table 8.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.6.6 Register 5 - Bus-hold/pull-up/pull-down enable 1 register Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 1. In this mode, the pull-up/pull-downs are disabled for I/O bank 1. Setting the bit 0 to logic 0 disables bus-hold feature.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.6.7 Register 6 - Pull-up/pull-down select port 0 register When bus-hold feature is not selected and bit 1 of Register 4 is set to logic 1, the I/O port 0 can be configured to have pull-up or pull-down by programming the pull-up/pull-down register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.6.9 Register 8 - Configuration port 0 register This register configures the direction of the I/O pins. If a bit in this register is set (written with logic 1), the corresponding port 0 pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with logic 0), the corresponding port 0 pin is enabled as an output. At reset, the device ports are inputs. Table 13.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.6.11 Register 10 - Output port 0 register This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register 8. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 15.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.6.13 Register 12 - Interrupt mask port 0 register All the bits of Interrupt mask port 0 register are set to logic 1 upon power-on or software reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to logic 0. Table 17. Register 12 - Interrupt mask port 0 register (address 0Ch) bit description Legend: * default value. Bit Symbol Access Value Description 7 M0.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.6.15 Register 14 - Interrupt status port 0 register This register is read-only. It is used to identify the source of interrupt. Remark: If the interrupts are masked, this register returns all zeros. Table 19. Register 14 - Interrupt status port 0 register (address 0Eh) bit description Legend: * default value. Bit Symbol Access Value Description 7 S0.7 read only 0* identifies source of interrupt 6 S0.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 7.9 Software reset The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The Software Reset sequence is defined as following: 1. A START command is sent by the I2C-bus master. 2.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 8. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 6'$ 6&/ 0$67(5 75$160,77(5 5(&(,9(5 6/$9( 5(&(,9(5 6/$9( 75$160,77(5 5(&(,9(5 0$67(5 75$160,77(5 0$67(5 75$160,77(5 5(&(,9(5 , & %86 08/7,3/(;(5 6/$9( DDD Fig 11. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge bit.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 9. Bus transactions Data is transmitted to the PCA9575 registers using ‘Write Byte’ transfers (see Figure 13 and Figure 14). Data is read from the PCA9575 registers using ‘Read Byte’ transfers (see Figure 15 and Figure 16).
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO slave address(1) SDA S 0 1 0 0 0 0 0 START condition 0 A R/W acknowledge from slave acknowledge from slave slave address(1) (cont.) S 0 1 0 0 0 data from register 0 (repeated) START condition (cont.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 10. Application design-in information VDD(IO)1 = 3.6 V VDD(IO)0 = 3.6 V VDD = 1.1 V to 3.6 V 1.6 kΩ 1.6 kΩ VDD 1.1 kΩ SUBSYSTEM 4 (e.g., RF module) 2 kΩ CTRL VDD VDD(IO)1 VDD(IO)0 MASTER CONTROLLER SCL SDA PCA9575 INT RESET SCL SDA P0_0 SUBSYSTEM 1 (e.g., temp. sensor) P0_1 INT INT RESET P0_2 RESET P0_3 SUBSYSTEM 2 (e.g., counter) P0_4 VSS P0_5 P0_6 A P0_7 controlled switch (e.g.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 12. Static characteristics Table 22. Static characteristics VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 1.1 - 3.6 V VDD(IO)0 input/output supply voltage 0 1.1 - VDD + 0.5 V VDD(IO)1 input/output supply voltage 1 1.1 - VDD + 0.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO Table 22. Static characteristics …continued VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VOL = 0.4 V; VDD = 1.1 V 3 - - mA Interrupt INT IOL LOW-level output current Select inputs (reset and address) VIL LOW-level input voltage - - +0.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 002aaf071 24 002aaf072 40 IOL (mA) IOH (mA) 30 16 Tamb = −40 °C +25 °C +85 °C Tamb = −40 °C +25 °C +85 °C 20 8 10 0 0 0 0.2 0.4 0.6 0.8 VDD − VOH (V) a. VDD(IO)0 or VDD(IO)1 = 1.8 V 0 0.2 0.4 0.6 0.8 VDD − VOH (V) b. VDD(IO)0 or VDD(IO)1 = 2.6 V Fig 21. IOH versus VOH 13. Dynamic characteristics Table 23. Dynamic characteristics VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO Table 23. Dynamic characteristics …continued VDD = 1.1 V to 3.6 V; VDD(IO)0 = 1.1 V to 3.6 V; VDD(IO)1 = 1.1 V to 3.6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Standard-mode I2C-bus Fast-mode I2C-bus Unit Min Max Min Max VDD(IO)0, VDD(IO)1 = VDD = 1.1 V - 350 - 350 ns VDD(IO)0, VDD(IO)1 = VDD = 2.3 V to 3.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO START ACK or read cycle 30 % 30 % SCL SDA trst(SDA) RESET 50 % 50 % trec(rst) tw(rst) 50 % trst(GPIO) P0_0 to P0_7 P1_0 to P1_7 50 % output off 002aad574 Fig 23. Reset timing 14. Test information VDD PULSE GENERATOR VI VO RL 500 Ω 2VDD open VSS DUT RT CL 50 pF 500 Ω(1) 002aad582 RL = load resistance. CL = load capacitance includes jig and probe capacitance.
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PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.
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PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 19. Abbreviations Table 26.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PCA9575 NXP Semiconductors 16-bit I2C-bus and SMBus, level translating, low voltage GPIO 23. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . .