Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsInterface ICsInterface IC - buffer amplifiers, repeaters I²C 400 kHz SO 8

1. General description

The PCA9600 is designed to isolate I

C-bus capacitance, allowing long buses to be

driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a

higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic interface

between a normal I

C-bus and a range of other higher capacitance or different voltage

bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side

is compatible with the Fast-mode Plus (Fm+) specifications.

The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface

making it suitable for interfacing with buses that have non I

C-bus-compliant logic levels

such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.

The separation of the bidirectional I

C-bus signals into unidirectional TX and RX signals

enables the SDA and SCL signals to be transmitted via balanced transmission lines

(twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX

signals may be connected together to provide a normal bidirectional signal.

2. Features and benefits

 Bidirectional data transfer of I

C-bus signals

 Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side

 TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive

buses

 1 MHz operation on up to 20 meters of wire (see AN10658)

 Supply voltage range of 2.5 V to 15 V with I

C-bus logic levels on SX/SY side

independent of supply voltage

 Splits I

C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface

with opto-electrical isolators and similar devices that need unidirectional input and

output signal paths

 Low power supply current

 ESD protection exceeds 4500 V HBM per JESD22-A114 and 1400 V CDM per

JESD22-C101

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

 Packages offered: SO8 and TSSOP8 (MSOP8)

PCA9600

Dual bidirectional bus buffer

Rev. 5 — 5 May 2011 Product data sheet

Summary of content (31 pages)

PAGE 1
PCA9600 Dual bidirectional bus buffer Rev. 5 — 5 May 2011 Product data sheet 1. General description The PCA9600 is designed to isolate I2C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic interface between a normal I2C-bus and a range of other higher capacitance or different voltage bus configurations.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 3.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 6. Pinning information 6.1 Pinning SX 1 8 VCC RX 2 7 SY TX 3 6 RY TX 3 GND 4 5 TY GND 4 PCA9600D Pin configuration for SO8 1 8 VCC 2 7 SY 6 RY 5 TY PCA9600DP 002aac837 002aac836 Fig 2. SX RX Fig 3. Pin configuration for TSSOP8 (MSOP8) 6.2 Pin description Table 3.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer The logic threshold voltage levels at SX on this I2C-bus are independent of the IC supply voltage VCC. The maximum I2C-bus supply voltage is 15 V. When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal 3 mA with a VOL of 0.74 V maximum.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer Remark: Two or more SX or SY I/Os must not be interconnected. The PCA9600 design does not support this configuration. Bidirectional I2C-bus signals do not allow any direction control pin so, instead, slightly different logic LOW voltage levels are used at SX/SY to avoid latching of this buffer. A ‘regular I2C-bus LOW’ applied at the RX/RY of a PCA9600 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage level.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer When the device driving the PCA9600 is an I2C-bus compatible device, then the PCA9600 is an improvement on the P82B96 as shown in Table 4. There will always be exceptions however, and if the device driving the bus buffer is not I2C-bus compatible (e.g.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 9. Characteristics Table 6. Characteristics Tamb = −40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit Power supply VCC supply voltage operating 2.5 - 15 V ICC supply current VCC = 5 V; buses HIGH - 5.2 6.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer Table 6. Characteristics …continued Tamb = −40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit ISX = ISY = 3 mA; Figure 6 - 0.7 0.74 V ISX = ISY = 0.3 mA; Figure 5 - 0.6 0.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer Table 6. Characteristics …continued Tamb = −40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 °C. Symbol Parameter Buffer response Conditions Min Typ Max Unit time[5] VCC = 5 V; pin TX pull-up resistor = 160 Ω; pin SX pull-up resistor = 2.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer VCC ≤ 1 mA SX (SY) Vref 002aac838 Fig 4. Equivalent circuit at SX/SY 002aac839 800 VOL (mV) 002aac840 800 VOL (mV) 700 (1) (2) 700 (1) (2) 600 600 500 500 400 −50 −25 0 25 50 75 100 125 Tj (°C) 400 −50 VOL at SX typical and limits over temperature. −25 (1) Maximum. (2) Typical. (2) Typical. VOL as a function of junction temperature (IOL = 0.3 mA) 002aag005 600 50 75 Fig 6.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 002aac075 1400 VCC(max) (mV) 1200 001aai062 1000 II (μA) 800 (1) (2) 1000 600 800 400 600 200 400 −50 −25 0 25 50 75 100 125 Tj (°C) 0 −50 −25 0 25 50 75 100 125 Tj (°C) (1) Maximum. (2) Typical. Fig 9. VCC bus release limit over temperature; maximum values PCA9600 Product data sheet Fig 10. Current sourced out of SX/SY as a function of junction temperature if these pins are externally pulled to 0.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 10. Application information Refer to PCA9600 data sheet and application notes AN10658 and AN255 for more detailed application information. VCC (2.5 V to 15 V) 5V TX (SDA) I2C-bus SDA R1 'SDA' (new levels) RX (SDA) PCA9600 001aai063 Fig 11. Interfacing a standard 3 mA I2C-bus or one with TTL levels (e.g. SMBus) to higher voltage or higher current sink (e.g.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer +V cable drive VCC2 VCC1 R2 R2 VCC VCC SCL R2 TX TX SX TY TY RX SX I2C-BUS MASTER SY SDA RX R2 R1 R1 R1 RY R1 SY SDA C2 C2 PCA9600 PCA9600 C2 I2C-BUS SLAVE(S) RY cable SCL propagation delay ≈ 5 ns/m C2 GND BAT54A GND BAT54A 002aac851 Fig 14. Driving ribbon or flat telephone cables Table 7. Examples of bus capability Refer to Figure 14.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 10.1 Calculating system delays and bus clock frequency local master bus buffered expansion bus VCCM remote slave bus VCCB VCCS Rm Rb Rs SCL MASTER SCL SX PCA9600 TX/RX TX/RX PCA9600 SLAVE SX I2C-BUS I2C-BUS Cm Cb Cs master bus capacitance buffered bus wiring capacitance slave bus capacitance GND (0 V) 002aac847 Effective delay of SCL at slave: 120 + 17VCCM + (2.5 + 4 × 109 × Cb) × VCCB + 10VCCS (ns). C = F; V = V.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer local master bus buffered expansion bus VCCM remote slave bus VCCB VCCS Rm Rb Rs SDA MASTER SDA SX PCA9600 TX/RX TX/RX PCA9600 SLAVE SX I2C-BUS I2C-BUS Cm Cb Cs master bus capacitance buffered bus wiring capacitance slave bus capacitance GND (0 V) 001aai158 Effective delay of SDA at master: 115 + 0.2(Rs × Cs) + 0.7[(Rb × Cb) + (Rm × Cm)] (ns). C = F; R = Ω. Fig 17.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer from the master reaching the slave (Figure 15) minus the effective delay (stretch) of the SCL rising edge (Figure 16) plus total delays in the slave's response data, carried on SDA, reaching the master (Figure 17).
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer The actual LOW period will be 407 + 126 = 533 ns, which exceeds the minimum Fm+ 500 ns requirement. This system requires the bus LOW period, and therefore cycle time, to be increased by 33 ns so the system must run slightly below the 1 MHz limit. The possible maximum speed has a cycle period of 1033 ns or 968 kHz. 12 V 12 V twisted-pair telephone wires, USB, or flat ribbon cables; up to 15 V logic levels, include VCC and GND 3.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 002aac932 7 VCC 6 (V) VCC 6 (V) (1) 5 002aac933 7 (1) 5 4 4 3 3 (2) 2 (2) 2 1 1 (1) 0 (2) (2) −1 (1) 0 0 (2) −1 100 200 300 400 500 600 700 800 900 time (ns) 0 100 200 300 400 500 600 700 800 900 time (ns) (1) TX output. (1) TX/RX output. (2) SX input. (2) SX input. Fig 19. Propagation SX to TX with VRX = VCC = 3.3 V (SX pull-up to 3.3 V; TX pull-up to 5.7 V) Fig 20.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer testing but it was not damaged. Whenever there is current flowing in any of these diodes it is possible that there can be faulty operation of any IC. For that reason we put a specification on the negative voltage that is allowed to be applied.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 10.2.1 Example with questions and answers Question: On a falling edge of TX we measure undershoot at −800 mV at the linked TX, RX pins of the PCA9600 that is generating the LOW, but the PCA9600 data sheet specifies minimum −0.3 V. Does this mean that we violate the data sheet absolute value? Answer: For PCA9600 the −0.3 V Absolute Maximum rating is not intended to apply to transients, it is a DC rating.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer Question: We have 2 meters of cable in a bus that joins the TX/RX sides of two PCA9600 devices. When one TX drives LOW the other PCA9600 TX/RX is driven to −0.8 V for over 50 ns.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer Question: If we add 100 Ω to 200 Ω at signal line, the overshoot becomes slightly smaller. Is this a good idea? Answer: No, it is not necessary to add any resistance.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 11. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp L 4 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 12.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 10.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9600 v.5 20110505 Product data sheet - PCA9600 v.4 Modifications: • Section 2 “Features and benefits”, eighth bullet item: deleted phrase “450 V MM per JESD22-A115” • Table 6 “Characteristics”, sub-section “Output logic LOW level, Pins SX and SY”: – Unit for VOL, condition ISX = ISY = 0.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
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PCA9600 NXP Semiconductors Dual bidirectional bus buffer 17. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 8 9 10 10.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .