PCA9698 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Rev. 3 — 3 August 2010 Product data sheet 1. General description The PCA9698 provides 40-bit parallel input/output (I/O) port expansion for I2C-bus applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable of sourcing 10 mA and sinking 25 mA with a total package load of 1 A to allow direct driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 40 configurable I/O pins that default to inputs at power-up Outputs: Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink) with controlled edge rate output structure. Default to totem-pole on power-up. Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be programmed to active HIGH through the I2C-bus.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 4. Ordering information Table 1. Ordering information Tamb = −40 °C to +85 °C Type number Topside mark Package Name Description Version PCA9698DGG PCA9698DGG TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 PCA9698BS PCA9698BS HVQFN56 plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 × 8 × 0.85 mm SOT684-1 5.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT configuration port register data (Cx[y]) output port register data (Ox[y]) OE OEPOL I/O configuration register data from shift register D Q VDD OUTx FF write configuration pulse CK Q IOx_y output port register data from shift register D D Q Q FF FF Mx[y] OCH CK write pulse CK STOP pulse INTERRUPT MANAGEMENT INT input port register D Q FF read pulse input port register data (Ix[y]) CK polarity inv
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 6. Pinning information 6.
PCA9698 NXP Semiconductors 43 IO4_4 44 VSS 45 IO4_5 46 IO4_6 47 IO4_7 48 INT/SMBALERT 49 RESET 50 SDA 51 SCL 52 IO0_0 53 IO0_1 54 IO0_2 terminal 1 index area 55 VSS 56 IO0_3 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT IO0_4 1 42 IO4_3 IO0_5 2 41 IO4_2 IO0_6 3 40 IO4_1 VSS 4 39 VDD IO0_7 5 38 IO4_0 IO1_0 6 37 IO3_7 IO1_1 7 IO1_2 8 IO1_3 9 34 IO3_4 IO1_4 10 33 IO3_3 36 IO3_6 PCA9698BS 35 IO3_5 VDD 11 32 VSS IO2_7 28 VSS 27 IO2_6 26 IO2_5 25
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Table 2. Pin description …continued Symbol Pin Type Description 22 input address input 2 30 23 input active LOW output enable INT/SMBALERT 55 48 output active LOW interrupt output/ active LOW SMBus alert output RESET 56 49 input active LOW reset input TSSOP56 HVQFN56 AD2 29 OE [1] HVQFN56 package die supply ground is connected to both VSS pins and exposed center pad.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.2 Alert response, GPIO All Call and Device ID addresses Three other different addresses can be sent to the PCA9698. • Alert Response address: allows to perform an ‘SMBus Alert’ operation as defined in the SMBus specification. This address is always used to perform a Read operation. See Section 7.11 “SMBus Alert output (SMBALERT)” for more information.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.3.1 5-bank register category • • • • • IP – Input registers OP – Output registers PI – Polarity Inversion registers IOC – I/O Configuration registers MSK – Mask interrupt registers If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically incremented after a read or write. This allows the user to program and/or read the 5 register banks sequentially.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Table 3.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.4.1 IP0 to IP4 - Input Port registers These registers are read-only. They reflect the incoming logic levels of the port pins regardless of whether the pin is defined as an input or an output by the I/O Configuration register. If the corresponding Px[y] bit in the PI registers is set to 0, or the inverted incoming logic levels if the corresponding Px[y] bit in the PI register is set to 1.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.4.3 PI0 to PI4 - Polarity Inversion registers These registers allow inversion of the polarity of the corresponding Input Port register. Px[y] = 0: The corresponding Input Port register data polarity is retained. Px[y] = 1: The corresponding Input Port register data polarity is inverted. Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7). Table 6.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.4.5 MSK0 to MSK4 - Mask interrupt registers These registers mask the interrupt due to a change in the I/O pins configured as inputs. ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7). Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input (Cx[y] in IOC register = 1).
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.4.7 ALLBNK - All Bank control register Table 10. Bit ALLBNK - All Bank control register (address 29h) description 7 6 5 4 3 2 1 0 Symbol BSEL X X B4 B3 B2 B1 B0 Default 1 0 0 0 0 0 0 0 This register allows all the I/Os configured as outputs to be programmed with the same logic value. This programming is applied to all the banks or a selection of banks.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT • If ALLBNK = 1XX0 1100: All I/Os configured as outputs in Bank 2 and 3 will be programmed with 1s, overwriting values programmed in the Output Port registers 2 and 3, while I/Os configured as outputs in Bank 0, 1, and 4 are programmed with values in Output Port registers 0, 1, and 4. 7.4.8 MODE - PCA9698 mode selection register Table 11.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.5 Device ID - PCA9698 ID field The Device ID field is a 3 byte read-only (24 bits) word giving the following information: • 12 bits with the manufacturer name, unique per manufacturer (e.g., NXP) • 9 bits with the part identification, assigned by manufacturer (e.g., PCA9698) • 3 bits with the die revision, assigned by manufacturer (e.g.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.6 GPIO All Call A ‘GPIO All Call’ command allows the programming of multiple advanced GPIOs with different I2C-bus addresses at the same time. This allows to optimize code programming when the master needs to send the same instruction to several devices. To respond to such a command and sequence, the PCA9698 needs to have its IOAC bit (register 2Ah, bit 3) set to 1.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT • When all the devices have been accessed, the master must generate a STOP command. • At the STOP command, all the PCA9698s that have been accessed will update their Output Port registers that have been programmed and change the output states all at the same time.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.11 SMBus Alert output (SMBALERT) The interrupt output pin (INT) can also be used as an Alert line (SMBALERT). The SMBALERT pins of multiple devices with this feature can be connected together to form a wired-AND signal and can be used in conjunction with the SMBus Alert Response Address. ‘SMBus Alert’ message is 2 bytes long and allows the master to determine which device generated the Alert (SMBALERT going LOW).
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.12 Output enable input (OE) The configurable active LOW or active HIGH output enable pin allows to enable or disable all the I/Os at the same time.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 7.15 Address map Table 12.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Table 12.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 8. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 8.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 13).
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 8.4 Bus transactions Data is transmitted to the PCA9698 registers using ‘Write Byte’ transfers (see Figure 15, Figure 16, Figure 17, and Figure 18). Data is read from the PCA9698 registers using ‘Read Byte’ and ‘Receive Byte’ transfers (see Figure 19 and Figure 20). PCA9698 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 August 2010 © NXP B.V. 2010.
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PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT acknowledge from slave slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 A AI 0 START condition 0 0 1 D2 D1 D0 A bank X determined by D2, D1, D0 acknowledge from slave DATA BANK X A P acknowledge from slave R/W STOP condition write to port tv(Q) data X valid data out from port 002aab945 OE is LOW (with OEPOL = 0) or HIGH (with OEPOL = 1) to observe a change in the outputs. OCH = 0.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT acknowledge from slave slave address command register SDA S A6 A5 A4 A3 A2 A1 A0 0 A X R/W START condition 0 1 0 1 acknowledge from slave 0 D1 D0 A acknowledge from slave DATA A P AI = 'don't care' STOP condition 00 for output structure configuration programming 01 for all bank control register programming 10 for mode selection register programming 002aab947 The programming becomes effective at the Ackno
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT acknowledge from slave slave address SDA S A6 A5 A4 A3 A2 A1 A0 0 A X R/W START condition acknowledge from slave slave address acknowledge from slave command register 0 1 0 1 no acknowledge from master data from register DATA 0 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 1 A AI = 'don't care' repeated START condition last byte R/W 00 for output structure configuration register reading 01 for for all bank control regis
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT acknowledge from slave GPIO All Call address SDA S 1 1 0 1 1 1 0 START condition 0 A 1 R/W acknowledge from slave(s) command register acknowledge from slave(s) acknowledge from slave(s) 0 D5 D4 D3 D2 D1 D0 A DATA BANK 0 A DATA BANK 1 A 00 1000 for Output Port register programming bank 0 01 0000 for Polarity Inversion register programming bank 0 01 1000 for Configuration register programming bank 0 10 0000
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 9. Application design-in information 5V VDD 1.6 kΩ 1.6 kΩ 1.1 kΩ (optional) 2 kΩ 2 kΩ 1.1 kΩ (optional) VDD VDD MASTER CONTROLLER SCL PCA9698 SCL IO0_0 SUBSYSTEM 1 (e.g., temp. sensor) SDA SDA IO0_1 INT RESET IO0_2 RESET INT INT/SMBALERT IO0_3 OE OE RESET SUBSYSTEM 2 (e.g., counter) IO0_4 VSS IO0_5 A IO1_0 controlled switch (e.g.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 10. Limiting values Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). PCA9698 Product data sheet Symbol Parameter Conditions VDD supply voltage VI input voltage VSS − 0.5 5.5 V II input current - ±20 mA VI/O voltage on an input/output pin VSS − 0.5 5.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 11. Static characteristics Table 14. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.3 - 5.5 V VDD = 2.3 V - 135 200 μA VDD = 3.3 V - 250 400 μA VDD = 5.5 V - 550 800 μA VDD = 2.3 V - 0.15 11 μA VDD = 3.3 V - 0.25 12 μA - 0.75 15.5 μA - 1.70 2.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Table 14. Static characteristics …continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VOL = 0.4 V 6 - - mA - 3 5 pF Interrupt INT IOL LOW-level output current Co output capacitance Inputs RESET and OE VIL LOW-level input voltage −0.5 - +0.8 V VIH HIGH-level input voltage 2 - 5.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 002aab957 600 IDD (μA) 002aab958 50 Isink (mA) 40 Tamb = −40 °C +25 °C +85 °C 400 30 fSCL = 1 MHz 20 200 400 kHz 10 100 kHz 0 2.0 0 3.0 4.0 5.0 6.0 0 0.2 0.4 VDD (V) 0.6 VOL (V) All I/Os unloaded; address pins static HIGH or LOW Fig 28. Supply current as a function of supply voltage 002aab959 50 Isink (mA) 40 Tamb = −40 °C +25 °C +85 °C 30 Fig 29.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 002aab965 50 Isource (mA) 40 002aab963 400 Tamb = −40 °C +25 °C +85 °C VOL (mV) 300 (1) 30 200 20 (2) 100 10 (3) 0 0.2 (4) 0 −50 0 0.4 0.6 VDD − VOH (V) 0 50 100 Tamb (°C) (1) VDD = 5 V; Isink = 10 mA (2) VDD = 2.3 V; Isink = 10 mA (3) VDD = 5 V; Isink = 1 mA (4) VDD = 2.3 V; Isink = 1 mA Fig 34. I/O source current as a function of HIGH-level output voltage (VDD = 5 V) Fig 35.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 12. Dynamic characteristics Table 15. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus [3] Min Max Fast-mode I2C-bus Fast-mode Plus Unit I2C-bus Min Max Min Max fSCL SCL clock frequency 0 100 0 400 0 1000 tBUF bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 - kHz μs tHD;STA hold time (repeated) START condition 4.0 - 0.6 - 0.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % 50 % trec(rst) tw(rst) trst 50 % IOx_y output off 002aac018 Fig 39. Reset timing 13. Test information VDD PULSE GENERATOR VI VO RL 500 Ω 2VDD open VSS DUT RT CL 50 pF 500 Ω 002aac019 RL = load resistance. CL = load capacitance includes jig and probe capacitance.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 14. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm A B D SOT684-1 terminal 1 index area A E A1 c detail X C e1 e 1/2 e b 15 L y y1 C v M C A B w M C 28 29 14 e e2 Eh 1/2 1 e 42 terminal 1 index area 56 43 X Dh 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 43. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Abbreviations Table 18.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 18. Revision history Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9698 v.3 20100803 Product data sheet - PCA9698 v.2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
PCA9698 NXP Semiconductors 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT 21. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . .